IDT IDT54FCT573D Fast cmos octal transparent latch Datasheet


IDT54/74FCT373/A/C
IDT54/74FCT533/A/C
IDT54/74FCT573/A/C
FAST CMOS OCTAL
TRANSPARENT LATCHES
Integrated Device Technology, Inc.
FEATURES
DESCRIPTION
• IDT54/74FCT373/533/573 equivalent to FAST speed
and drive
• IDT54/74FCT373A/533A/573A up to 30% faster than
FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• Octal transparent latch with 3-state output control
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and
IDT54/74FCT573/A/C are octal transparent latches built using an advanced dual metal CMOS technology. These octal
latches have 3-state outputs and are intended for bus oriented
applications. The flip-flops appear transparent to the data
when Latch Enable (LE) is HIGH. When LE is LOW, the data
that meets the set-up time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAMS
IDT54/74FCT373 AND IDT54/74FCT573
D0
D1
D
D2
D
D3
D
O
D
O
G
D4
D
O
G
D5
D
O
G
D6
D
O
G
D7
D
O
G
O
G
O
G
G
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
2602 cnv* 01
IDT54/74FCT533
D0
D1
D
D2
D
D3
D
O
D
O
G
D4
D
O
G
D5
D
O
G
D6
D
O
G
D7
D
O
G
O
G
O
G
G
LE
OE
O0
O1
O2
O3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
O5
O6
O7
2602 cnv* 02
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1992 Integrated Device Technology, Inc.
O4
7.12
MAY 1992
DSC-4624/2
1
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
VCC
O0
2
3
19
O7
18
D7
4
17
D6
D1
4
O6
O1
5
O5
D5
O2
6
D2
D3
D2
D3
7
8
O3
GND
9
12
O4
10
11
LE
D4
1
20 19
18
17
D7
D6
16
O6
7
15
O5
8
14
D5
L20-2
9 10 11 12 13
O3
GND
6
2
DIP/SOIC/CERPACK
TOP VIEW
D4
5
3
O4
O1
O2
P20-1
D20-1 16
SO20-2 15
&
E20-1 14
13
LE
D0
D1
VCC
O7
20
OE
1
O0
INDEX
OE
D0
IDT54/74FCT373
LCC
TOP VIEW
19
O0
18
4
17
O1
O2
D3
5
D4
6
D5
7
D6
8
D2
4
O3
O4
D3
5
D4
6
O5
O6
D5
D6
7
8
9
12
O7
10
11
LE
3
2
1
20 19
18
O1
17
O2
16
O3
15
O4
14
O5
L20-2
9 10 11 12 13
D7
GND
D7
GND
P20-1
D20-1 16
SO20-2 15
&
14
E20-1
13
O0
2
3
D1
D2
DIP/SOIC/CERPACK
TOP VIEW
O6
D0
INDEX
O7
VCC
OE
VCC
20
LE
1
D0
OE
D1
IDT54/74FCT573
LCC
TOP VIEW
VCC
O0
19
O7
D0
2
3
18
D7
D1
4
17
D6
D1
4
O1
5
O6
O1
5
O2
6
O5
7
D3
8
O2
D2
D3
6
D2
P20-1
D20-1 16
SO20-2 15
&
14
E20-1
13
O3
GND
9
12
O4
10
11
LE
3 2
D5
D4
VCC
O7
20
D0
1
OE
INDEX
OE
O0
IDT54/74FCT533
1
20 19
18
L20-2
7
17
D7
D6
16
O6
15
O5
D5
14
8
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
7.12
D4
O4
LE
O3
GND
9 10 11 12 13
2602 cnv* 03–08
2
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLE (FCT373 and FCT573)(1)
FUNCTION TABLE (FCT533)(1)
Inputs
LE
DN
Outputs
OE
ON
DN
Inputs
LE
OE
Outputs
ON
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
L
X
X
H
Z
X
X
H
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
2602 tbl 05
2602 tbl 06
PIN DESCRIPTION
Pin Names
DN
Description
Data Inputs
LE
Latch Enable Input (Active HIGH)
OE
Output Enable Input (Active LOW)
ON
3-State Outputs
ON
Complementary 3-State Outputs
2602 tbl 07
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial
VTERM(2) Terminal Voltage
–0.5 to +7.0
with Respect to
GND
VTERM(3) Terminal Voltage
–0.5 to VCC
with Respect to
GND
TA
Operating
0 to +70
Temperature
TBIAS
Temperature
–55 to +125
Under Bias
TSTG
Storage
–55 to +125
Temperature
PT
Power Dissipation
0.5
IOUT
DC Output
Current
120
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Military
–0.5 to +7.0
Unit
V
–0.5 to VCC
V
–55 to +125
°C
–65 to +135
°C
–65 to +150
°C
0.5
W
120
mA
Symbol
Parameter
CIN
Input
Capacitance
COUT
Output
Capacitance
Conditions
VIN = 0V
Typ.
6
Max.
10
Unit
pF
VOUT = 0V
8
12
pF
NOTE:
2602 tbl 02
1. This parameter is measured at characterization but not tested.
NOTES:
2602 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
7.12
3
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
VIL
Input LOW Level
II H
Input HIGH Current
Symbol
VIH
II L
IOZH
Min.
2.0
Typ.(2)
—
Max.
—
Unit
V
Guaranteed Logic LOW Level
—
—
0.8
V
VCC = Max.
—
—
5
µA
VI = VCC
Input LOW Current
Off State (High Impedance)
VCC = Max.
Output Current
IOZL
VI = 2.7V
—
—
5(4)
VI = 0.5V
—
—
–5(4)
VI = GND
—
—
–5
VO = VCC
—
—
10
VO = 2.7V
—
—
10(4)
VO = 0.5V
—
—
–10(4)
VO = GND
—
—
–10
µA
VIK
Clamp Diode Voltage
VCC = Min., IN = –18mA
—
–0.7
–1.2
V
IOS
Short Circuit Current
VCC = Max.(3) , VO = GND
–60
–120
—
mA
VOH
Output HIGH Voltage
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VHC
VCC
—
V
VCC = Min.
IOH = –300µA
VHC
VCC
—
VIN = VIH or VIL
IOH = –12mA MIL.
2.4
4.3
—
IOH = –15mA COM'L.
2.4
4.3
—
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
—
GND
VLC
VCC = Min.
IOL = 300µA
—
GND
VLC(4)
VIN = VIH or VIL
IOL = 32mA MIL.
—
0.3
0.5
IOL = 48mA COM'L.
—
0.3
0.5
VOL
Output LOW Voltage
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
7.12
V
2602 tbl 03
4
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC – 0.2V
Symbol
ICC
∆ICC
ICCD
IC
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current(4)
Total Power Supply Current (6)
Test Conditions(1)
VCC = Max.
VIN ≥ VHC; V IN ≤ V LC
VCC = Max.
VIN = 3.4V(3)
VCC = Max.
Outputs Open
OE = GND
One Input Toggling
50% Duty Cycle
VCC = Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE = GND
LE = VCC
One Bit Toggling
VCC = Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE = GND
LE = VCC
Eight Bits Toggling
Min.
Typ.(2)
Max.
Unit
—
0.2
1.5
mA
—
0.5
2.0
mA
VIN ≥ VHC
VIN ≤ VLC
—
0.15
0.25
mA/
MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
VIN = 3.4V
VIN = GND
—
1.7
4.0
mA
—
2.0
5.0
VIN ≥ VHC
VIN ≤ VLC
(FCT)
VIN = 3.4V
VIN = GND
—
3.2
6.5 (5)
—
5.2
14.5 (5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.12
2602 tbl 04
5
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT373/A/C/FCT573/A/C
FCT373/573
Com'l.(2)
Symbol
Parameter
tPLH
tPHL
Propagation Delay
DN to ON
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
LE to ON
Output Enable Time
tH
tW
Conditions(1)
CL = 50pF
RL = 500Ω
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
FCT373A/573A
Mil.(2)
Com'l.(2)
FCT373C/573C
Mil.(2)
Com'l. (2)
Mil.(2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.5
8.0
1.5
8.5
1.5
5.2
1.5
5.6
1.5
4.2
1.5
5.1
ns
2.0 13.0
2.0 15.0
2.0
8.5
2.0
9.8
2.0
5.5
2.0
8.0
ns
1.5 12.0
1.5 13.5
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5
7.5
1.5 10.0
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
6.0
—
5.0
—
6.0
—
5.0
—
6.0
—
ns
2602 tbl 08
SWITCHING CHARACTERISTICS OVER OPERATING RANGE FOR FCT533/A/C
FCT533
Com'l.(2)
Symbol
Parameter
tPLH
tPHL
Propagation Delay
DN to ON
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Propagation Delay
LE to ON
Output Enable Time
tH
tW
Output Disable Time
Set-up Time HIGH
or LOW, DN to LE
Hold Time HIGH
or LOW, DN to LE
LE Pulse Width HIGH
Conditions(1)
CL = 50pF
RL = 500Ω
FCT533A
Mil.(2)
Com'l.(2)
FCT533C
Mil.(2)
Com'l.(2)
Mil.(2)
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.5 10.0
1.5 12.0
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
ns
2.0 13.0
2.0 14.0
2.0
8.5
2.0
9.8
2.0
6.9
2.0
8.0
ns
1.5 11.0
1.5 12.5
1.5
6.5
1.5
7.5
1.5
5.5
1.5
6.3
ns
1.5
7.0
1.5
8.5
1.5
5.5
1.5
6.5
1.5
5.0
1.5
5.9
ns
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
2.0
—
ns
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
6.0
—
6.0
—
5.0
—
6.0
—
5.0
—
6.0
—
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
2602 tbl 09
7.12
6
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
500Ω
V OUT
VIN
Pulse
Generator
D.U.T.
50pF
RT
500Ω
SET-UP, HOLD AND RELEASE TIMES
Closed
All Other Tests
Open
3V
1.5V
0V
tH
TIMING
INPUT
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
tW
t REM
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
Open Drain
Disable Low
Enable Low
PULSE WIDTH
DATA
INPUT
ASYNCHRONOUS CONTROL
Switch
DEFINITIONS:
2537 tbl 10
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
CL
t SU
Test
t SU
1.5V
3V
1.5V
0V
tH
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
1.5V
SAME PHASE
INPUT TRANSITION
t PLH
t PHL
CONTROL
INPUT
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t PZH
VOL
t PLH
t PHL
OUTPUT SWITCH
NORMALLY OPEN
HIGH
3V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
t PLZ
t PZL
0V
VOH
1.5V
OUTPUT
1.5V
3.5V
1.5V
3.5V
0.3V
V OL
t PHZ
0.3V
1.5V
0V
V OH
0V
0V
NOTES
2537 drw 04
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.12
7
IDT54/74FCT373/533/573/A/C
FAST CMOS OCTAL TRANSPARENT LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
FCT
XXXX
XX
Temp. Range
Device Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
P
D
SO
L
E
Plastic DIP
CERDIP
Small Outline IC
Leadless Chip Carrier
CERPACK
373
573
533
373A
573A
533A
373C
573C
533C
Non-Inverting Octal Transparent Latch
Non-Inverting Octal Transparent Latch
Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Non-Inverting Octal Transparent Latch
Fast Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Non-Inverting Octal Transparent Latch
Super Fast Inverting Octal Transparent Latch
54
74
–55°C to +125°C
0°C to +70°C
2602 cnv* 14
7.12
8
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