TI1 ADS820 10-bit, 20mhz sampling analog-to-digital converter Datasheet

ADS820
ADS
820
U
SBAS037B – DECEMBER 1995 – REVISED FEBRUARY 2005
10-Bit, 20MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● NO MISSING CODES
● INTERNAL REFERENCE
● LOW DIFFERENTIAL LINEARITY ERROR:
0.2LSB
● LOW POWER: 195mW
● HIGH SNR: 60dB
● WIDEBAND TRACK/HOLD: 65MHz
The ADS820 is a low-power, monolithic 10-bit, 20MHz Analog-to-Digital (A/D) converter utilizing a small geometry CMOS
process. This complete converter includes a 10-bit quantizer
with internal track-and-hold, reference, and a power down
feature. It operates from a single +5V power supply and can
be configured to accept either differential or single-ended
input signals.
The ADS820 employs digital error correction to provide excellent Nyquist differential linearity performance for demanding
imaging applications. Its low distortion, high SNR, and high
oversampling capability give it the extra margin needed for
telecommunications and video applications.
APPLICATIONS
●
●
●
●
SET-TOP BOXES
CABLE MODEMS
VIDEO DIGITIZING
CCD IMAGING
Camcorders
Copiers
Scanners
Security Cameras
● IF AND BASEBAND DIGITIZATION
This high performance converter is specified for AC and
DC-performance at a 20MHz sampling rate. The ADS820
is available in an SO-28 package.
CLK
MSBI
OE
Error
Correction
Logic
3-State
Outputs
Timing
Circuitry
IN
Pipeline
A/D
T&H
IN
10-Bit
Digital
Data
+3.25V
REFT
CM
REFB
+1.25V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995-2005, Texas Instruments Incorporated
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
+VS ....................................................................................................... +6V
Analog Input ............................................................ 0V to (+VS + 300mV)
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Logic Input ............................................................... 0V to (+VS + 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature .................................................................... +125°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
External Top Reference Voltage (REFT) ................................. +3.4V Max
External Bottom Reference Voltage (REFB) ............................ +1.1V Min
NOTES: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
PACKAGE/ORDERING INFORMATION(1)
PRODUCT
ADS820
PACKAGE-LEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
SO-8
DW
–40°C to +85°C
ADS820U
ADS820U
Rails, 28
"
"
"
"
ADS820U/1K
Tape and Reel, 1000
"
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
ELECTRICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
ADS820U
PARAMETER
Resolution
Specified Temperature Range
ANALOG INPUT
Differential Full-Scale Input Range
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small Signal
Full Power
CONDITIONS
TEMP
MIN
ACCURACY(2)
Gain Error
Gain Tempco
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
TAMBIENT
–40
+1.25
–20dBFS(1) Input
0dB Input
+25°C
+25°C
f = 10MHz
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
f = 10MHz (–1dBFS input)
UNITS
+85
Bits
°C
fS = 2.5MHz
∆ +VS = ±5%
+3.25
V
V
400
65
MHz
MHz
1.25 || 4
MΩ || pF
±0.6
±1.0
±85
0.01
±2.1
0.02
+25°C
Full
∆ +VS = ±5%
2.25
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
+25°C
Full
+25°C
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
MAX
10
Input Impedance
DIGITAL INPUT
Logic Family
Convert Command
TYP
10k
±1.5
±2.5
0.1
±3.0
0.1
20M
Sample/s
Convert Cycle
±1.0
±1.0
±1.0
±1.0
LSB
LSB
LSB
LSB
±2.0
LSB
6.5
±0.15
±0.15
±0.2
±0.2
Tested
±0.5
+25°C
Full
+25°C
Full
Full
Full
+25°C
Full
+25°C
Full
67
64
59
57
77
74
63
62
%
%
ppm/°C
%FSR/%
%
%FSR/%
dBFS
dBFS
dBFS
dBFS
NOTE: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D Converter Full-Scale Range of 4Vp-p. (3) IMD is
referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (4) Based on
(SINAD – 1.76)/6.02. (5) No “rollover” of bits.
2
ADS820
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SBAS037B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
ADS820U, E
PARAMETER
CONDITIONS
TEMP
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
f = 10MHz (–1dBFS input)
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
f = 10MHz (–1dBFS input)
Differential Gain Error
Differential Phase Error
Effective Bits(4)
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time(5)
OUTPUTS
Logic Family
Logic Coding
Logic Levels
NTSC or PAL
NTSC or PAL
fIN = 3.58MHz
1.5x Full-Scale Input
Logic Selectable
Logic LOW, CL = 15pF
Logic HIGH, CL = 15pF
3-State Enable Time
3-State Disable Time
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Power Consumption
MIN
TYP
+25°C
Full
+25°C
Full
58
56
58
56
60.5
60
60
60
dB
dB
dB
dB
+25°C
Full
+25°C
Full
+25°C
+25°C
58
55
56
54
60.5
60
58
57
0.5
0.1
9.5
2
7
2
dB
dB
dB
dB
%
degrees
Bits
ns
ps rms
ns
+25°C
+25°C
+25°C
TTL/HCT Compatible CMOS
SOB or BTC
Full
Full
Full
+25°C
Full
+25°C
Full
Thermal Resistance, θJA
SO-28
+4.75
UNITS
20
2
0.4
+VS
40
10
V
V
V
ns
ns
+5
39
40
195
200
+5.25
47
55
235
275
V
mA
mA
mW
mW
0
2.5
Full
Operating
Operating
Operating
Operating
Operating
MAX
75
°C/W
NOTE: (1) dBFS refers to dB below Full Scale. (2) Percentage accuracies are referred to the internal A/D Converter Full-Scale Range of 4Vp-p. (3) IMD is
referred to the larger of the two input signals. If referred to the peak envelope signal (≈ 0dB), the intermodulation products will be 7dB lower. (4) Based on
(SINAD – 1.76)/6.02. (5) No “rollover” of bits.
ADS820
SBAS037B
www.ti.com
3
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
SO
PIN
DESIGNATOR
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DNC
DNC
GND
+VS
CLK
+VS
OE
Bit 7
8
21
REFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Bit 8
9
20
+VS
19
MSBI
Bit 9
10
19
MSBI
Bit 10 (LSB)
11
18
OE
20
21
+VS
REFB
DNC
12
17
+VS
DNC
13
16
CLK
22
CM
GND
14
15
+VS
23
REFT
24
25
26
27
28
+VS
GND
IN
IN
GND
GND
1
28
GND
Bit 1(MSB)
2
27
IN
Bit 2
3
26
IN
Bit 3
4
25
GND
Bit 4
5
24
+VS
Bit 5
6
23
REFT
Bit 6
7
22
CM
ADS820
DNC: Do Not Connect
DESCRIPTION
Ground
Bit 1, Most Significant Bit (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10, Least Significant Bit (LSB)
Do not connect.
Do not connect.
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
HIGH: High Impedance State. LOW or Floating:
Normal Operation. Internal pull-down resistor.
Most Significant Bit Inversion, HIGH: MSB inverted for complementary output. LOW or Floating: Straight output. Internal pull-down resistor.
+5V Power Supply
Bottom Reference Bypass. For external bypassing of internal +1.25V reference.
Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
Complementary Input
Ground
TIMING DIAGRAM
tCONV
Convert
Clock
tL
tD
tH
Data Latency
(6.5 Clock Cycles)
Hold
Hold
Hold
Hold
Hold
Hold
Track "N + 1" Track "N + 2" Track "N + 3" Track "N + 4" Track "N + 5" Track "N + 6" Track
(1)
Track
Internal
Track-and-Hold
Hold
"N"
t2
Output
Data
Data Valid
N–8
Data Valid
N–7
Data Valid
N–6
N–5
N–4
N–3
N–2
N–1
N
t1
Data Invalid
SYMBOL
tCONV
tL
tH
tD
t1
t2
NOTE: (1) “
4
DESCRIPTION
MIN
Convert Clock Period
Clock Pulse LOW
Clock Pulse HIGH
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
50
24
24
TYP
MAX
UNITS
100µs
ns
ns
ns
ns
ns
ns
25
25
2
3.9
12.5
” indicates the portion of the waveform that will stretch out at slower sample rates.
ADS820
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SBAS037B
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fIN = 500kHz
fS = 10MHz
fIN = 4.8MHz
–20
–40
Amplitude (dB)
Amplitude (dB)
–20
–60
–80
–100
–40
–60
–80
–100
–120
–120
0
1.0
2.0
3.0
4.0
5.0
0
2.0
4.0
Frequency (MHz)
6.0
SPECTRAL PERFORMANCE
0
fIN = 9.8MHz
f1 = 4.5MHz
–20
–20
–40
Amplitude (dB)
Amplitude (dB)
10.0
TWO-TONE INTERMODULATION
0
–60
–80
–100
f2 = 4.4MHz
–40
–60
–80
–100
–120
–120
0
2.0
4.0
6.0
8.0
10.0
0.0
2.50
Frequency (MHz)
5.00
7.50
10.00
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
2.0
2.0
fIN = 10MHz
fIN = 500kHz
1.0
DLE (LSB)
1.0
DLE (LSB)
8.0
Frequency (MHz)
0
0
–1.0
–1.0
–2.0
–2.0
24
224
424
624
824
24
1024
ADS820
SBAS037B
224
424
624
824
1024
Code
Code
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5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
SWEPT POWER SFDR
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
100
85
fIN = 10MHz
80
80
75
SFDR (dBFS)
SFDR, SNR (dB)
SFDR
70
65
SNR
60
40
20
60
55
100k
0
1M
10M
–50
100M
–40
–30
–20
–10
0
10
Input Amplitude (dBm)
Frequency (Hz)
SWEPT POWER SNR
INTEGRAL LINEARITY ERROR
60
4.0
fIN = 500kHz
fIN = 10MHz
50
2.0
ILE (LSB)
SNR (dB)
40
30
0
20
–2.0
10
0
–48.125
–4.0
–40
–30
–20
–10
0
24
10
424
624
1024
DYNAMIC PERFORMANCE
vs SINGLE-ENDED FULL-SCALE INPUT RANGE
DYNAMIC PERFORMANCE
vs DIFFERENTIAL FULL-SCALE INPUT RANGE
80
SFDR (fIN = 500kHz)
SFDR (fIN = 500kHz)
75
Dynamic Range (dB)
75
70
SFDR (fIN = 10MHz)
65
SNR (fIN = 500kHz)
70
SFDR (fIN = 10MHz)
65
SNR (fIN = 500kHz)
60
60
SNR (fIN = 10MHz)
SNR (fIN = 10MHz)
55
55
1
2
3
4
1
5
2
3
4
5
Differential Full-Scale Input Range (Vp-p)
Single-Ended Full-Scale Input Range (Vp-p)
NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V.
6
824
Code
80
Dynamic Range (dB)
224
Input Amplitude (dBm)
NOTE: REFTEXT varied, REFB is fixed at internal value of +1.25V.
ADS820
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SBAS037B
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE
0.3
90
fIN = 500kHz
80
0.2
SFDR (dBFS)
DLE (LSB)
fIN = 10MHz
0.1
fIN = 500kHz
70
60
fIN = 10MHz
0
50
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
75
100
Temperature (°C)
Temperature (°C)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
62
70
fIN = 500kHz
60
65
SINAD (dB)
SNR (dB)
fIN = 500kHz
60
fIN = 10MHz
58
fIN = 10MHz
56
55
54
50
–50
–25
0
25
50
75
–50
100
–25
0
Temperature (°C)
25
50
Temperature (°C)
POWER DISSIPATION vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
42
210
200
IQ (mA)
Power (mW)
40
38
190
180
36
170
–50
–25
0
25
50
75
100
–50
Temperature (°C)
0
25
50
75
100
Temperature (°C)
ADS820
SBAS037B
–25
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7
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, Sampling Rate = 20MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
OFFSET ERROR vs TEMPERATURE
–1.75
Offset (% FSR)
Gain (% FSR)
–0.05
–0.55
–1.05
–1.55
–2.0
–2.25
–2.50
–50
–25
0
25
50
75
100
–50
–25
0
Temperature (°C)
0
1M
–1
0.8M
Counts
Track-Mode Input Response (dB)
1.2M
–2
0.4M
–4
0.2M
–5
1M
10M
100M
0.0
N–2
1G
Frequency (Hz)
8
75
100
0.6M
–3
100k
50
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
1
10k
25
Temperature (°C)
N–1
N
N+1
N+2
Code
ADS820
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SBAS037B
THEORY OF OPERATION
Op Amp
Bias
The ADS820 is a high-speed, sampling A/D converter with
pipelining. It uses a fully differential architecture and digital
error correction to ensure 10-bit resolution. The differential
track-and-hold circuit is shown in Figure 1. The switches are
controlled by an internal clock that has a non-overlapping,
two-phase signal, φ1 and φ2. At the sampling time the input
signal is sampled on the bottom plates of the input capacitors. In the next clock phase, φ2, the bottom plates of the
input capacitors are connected together and the feedback
capacitors are switched to the op amp output. At this time,
the charge redistributes between CI and CH, completing one
track-and-hold cycle. The differential output is a held DC
representation of the analog input at the sample time. The
track-and-hold circuit can also convert a single-ended input
signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has nine stages with
each stage containing a 2-bit quantizer and a 2-bit Digital-toAnalog Converter (DAC), as shown in Figure 2. Each 2-bit
quantizer stage converts on the edge of the sub-clock, which
is twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
IN
IN
φ1
φ1
CH
φ2
CI
IN
IN
φ1
φ2
OUT
φ1
OUT
φ1
CI
φ2
CH
φ1
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1
φ2
φ1
FIGURE 1. Input Track-and-Hold Configuration with Timing
Signals.
Digital Delay
Input
T&H
2-Bit
Flash
STAGE 1
VCM
2-Bit
DAC
+
Σ
–
x2
Digital Delay
STAGE 2
B1 (MSB)
2-Bit
DAC
B2
Digital Error Correction
2-Bit
Flash
+
Σ
–
x2
B3
B4
B5
B6
B7
B8
B9
Digital Delay
2-Bit
Flash
STAGE 8
B10 (LSB)
2-Bit
DAC
+
Σ
–
x2
STAGE 9
2-Bit
Flash
Digital Delay
FIGURE 2. Pipeline A/D Converter Architecture.
ADS820
SBAS037B
www.ti.com
9
time-align it with the data created from the following quantizer stages. This aligned data is fed into a digital error
correction circuit that can adjust the output data based on the
information found on the redundant bits. This technique gives
the ADS820 excellent differential linearity and ensures no
missing codes at the 10-bit level.
There is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS820 can be configured in various
ways and driven with different circuits, depending on the
nature of the signal and the level of performance desired. The
ADS820 has an internal reference that sets the full-scale
input range of the A/D converter. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full-scale range of +1.25V
to +3.25V. Since each input is 2Vp-p and 180° out-of-phase
with the other, a 4V differential input signal to the quantizer
results. The positive full-scale reference (REFT) and the
negative full-scale reference (REFB) are brought out for
external bypassing, as shown in Figure 3. In addition, the
common-mode (CM) voltage may be used as a reference to
provide the appropriate offset for the driving circuitry. However, care must be taken not to appreciably load this reference node. For more information regarding external references, single-ended inputs, and ADS820 drive circuits, refer
to the applications section.
DIGITAL OUTPUT DATA
The 10-bit output data is provided at CMOS logic levels. The
standard output coding is Straight Offset Binary where a fullscale input signal corresponds to all “1’s” at the output. This
condition is met with pin 19 LOW or Floating due to an
internal pull-down resistor. By applying a high voltage to this
pin, a BTC output will be provided where the most significant
bit is inverted. The digital outputs of the ADS820 can be set
to a high impedance state by driving OE (pin 18) with a logic
HIGH. Normal operation is achieved with pin 18 LOW or
Floating due to internal pull-down resistors. This function is
provided for testability purposes and is not meant to drive
digital buses directly or be dynamically changed during the
conversion process.
OUTPUT CODE
DIFFERENTIAL INPUT(1)
SOB
PIN 19
FLOATING or LOW
BTC
PIN 19
HIGH
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
0111111111
0111111111
0111111110
0110000000
0100000000
0010000000
0000000001
0000000000
1111111111
1110000000
1100000000
1010000000
1000000001
1000000000
+FS (IN = +3.25V, IN = +1.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1.25V, IN = +3.25V)
NOTE: (1) In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS820.
ADS820
APPLICATIONS
+3.25V
23
REFT
DRIVING THE ADS820
0.1µF
The ADS820 has a differential input with a common mode of
+2.25V. For AC-coupled applications, the simplest way to
create this differential input is to drive the primary winding of
a transformer with a single-ended input. A differential output
is created on the secondary if the center tap is tied to the
(CM) voltage of +2.25V, as per Figure 4. This transformercoupled input arrangement provides good high frequency
2kΩ
+2.25V
22
To
Internal
Comparators
CM
2kΩ
21
0.1µF
REFB
+1.25V
FIGURE 3. Internal Reference Structure.
22 CM
0.1µF
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising
and falling edge of the externally applied convert command
clock controls the various interstage conversions in the
pipeline. Therefore, the duty cycle of the clock should be held
at 50% with low jitter and fast rise and fall times of 2ns or
less. This is especially important when digitizing a highfrequency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten some
of the interstage settling times, thus degrading the SNR and
DNL performance.
10
26 IN
AC Input
Signal
ADS820
22pF
Mini-Circuits
TT1-6-KK81
or equivalent
27 IN
22pF
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
ADS820
www.ti.com
SBAS037B
AC performance. It is important to select a transformer that
gives low distortion and does not exhibit core saturation at
full-scale voltage levels. Since the transformer does not
appreciably load the ladder, there is no need to buffer the CM
output in this instance. In general, it is advisable to keep the
current draw from the CM output pin below 0.5µA to avoid
nonlinearity in the internal reference ladder. A FET input
operational amplifier, such as the OPA130, can provide a
buffered reference for driving external circuitry. The analog
IN and IN inputs should be bypassed with 22pF capacitors to
minimize track-and-hold glitches and to improve high-input
frequency performance.
each input. The cutoff frequency of the filter is determined by
fC = 1/(2πRSER • (CSH + CADC)) where RSER is the resistor in
series with the input, CSH is the external capacitor from the
input to ground, and CADC is the internal input capacitance of
the A/D converter (typically 4pF).
Resistors R1 and R2 are used to derive the necessary
common-mode voltage from the buffered top and bottom
references. The total load of the resistor string should be
selected so that the current does not exceed 1mA. Although
the circuit in Figure 5 uses two resistors of equal value so that
the common-mode voltage is centered between the top and
bottom reference (+2.25V), it is not necessary to do so. In all
cases the center point, VCM, should be bypassed to ground in
order to provide a low-impedance ac ground.
Figure 5 illustrates another possible low-cost interface circuit
that utilizes resistors and capacitors in place of a transformer.
Depending on the signal bandwidth, the component values
should be carefully selected in order to maintain the performance outlined in the data sheet. The input capacitors, CIN,
and the input resistors, RIN, create a high-pass filter with the
lower corner frequency at fC = 1/(2πRINCIN). The corner
frequency can be reduced by either increasing the value of
RIN or CIN. If the circuit operates with a 50Ω or 75Ω impedance level, the resistors are fixed and only the value of the
capacitor can be increased. Usually AC-coupling capacitors
are electrolytic or tantalum capacitors with values of 1µF or
higher. It should be noted that these large capacitors become
inductive with increased input frequency, which could lead to
signal amplitude errors or oscillation. To maintain a low accoupling impedance throughout the signal band, a small
value (e.g. 1µF) ceramic capacitor could be added in parallel
with the polarized capacitor.
If the signal needs to be DC-coupled to the input of the
ADS820, an operational amplifier input circuit is required. In
the differential input mode, any single-ended signal must be
modified to create a differential signal. This can be accomplished by using two operational amplifiers; one in the
noninverting mode for the input and the other amplifier in the
inverting mode for the complementary input. The low distortion circuit in Figure 6 will provide the necessary input shifting
required for signals centered around ground. It also employs
a diode for output level shifting to ensrue a low distortion
+3.25V output swing. Another DC-coupled circuit is shown in
Figure 7. Other amplifiers can be used in place of the
OPA860s if the lowest distortion is not necessary. If output
level shifting circuits are not used, care must be taken to
select operational amplifiers that give the necessary performance when swinging to +3.25V with a ±5V supply operational amplifier. The OPA620 and OPA621, or the lower
power OPA820 can be used in place of the OPA860s in
Figure 6. In that configuration, the OPA820 will typically
swing to within 100mV of positive full scale.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track and
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series with
CIN
0.1µF
RSER1(1)
49.9Ω
RIN1
25Ω
RIN2
25Ω
CIN
0.1µF
C1
0.1µF
R1
(6kΩ)
+3.25V
Top Reference
IN
CSH1
22pF
R3
1kΩ
C2
0.1µF
RSER2(1)
49.9Ω
ADS8xx
VCM
R2
(6kΩ)
IN
CSH2
22pF
+1.25V
Bottom Reference
C3
0.1µF
NOTE: (1) indicates optional component.
FIGURE 5. AC-Coupled Differential Input Circuit.
ADS820
SBAS037B
www.ti.com
11
+5V
604Ω
+5V
301Ω
BAS16(1)
(3)
Optional
High Impedance
Input Amplifier
301Ω
301Ω
27 IN
OPA842
2.49kΩ
0.1µF
22pF
+5V(2)
0.1µF
–5V
DC-Coupled
Input Signal
604Ω
+5V
ADS820
(3)
OPA842
604Ω
49.9Ω
OPA130
+5V
–5V
24.9Ω
2.49kΩ +2.25V
22 CM
+5V
301Ω
BAS16(1)
(3)
Input Level
Shift Buffer
301Ω
26 IN
OPA842
0.1µF
–5V
22pF
604Ω
NOTES: (1) A Philips BAS16 diode or equivalent may be used.
(2) Supply bypassing not shown. (3) OPA620 or OPA650 may be
substituted. See “Driving the ADS820” section.
301Ω
FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.
DC-Coupled
Input Signal
2kΩ
+5V
–5V
7
4
1
3
243Ω
–5V
B
C
2
E
+1
OTA
26 IN
6
1kΩ
22pF
OPA860
8
200Ω
1nF
5
500Ω
+5V
1kΩ
ADS820
2
50Ω
OPA130
1kΩ
C1
15pF
200Ω
200Ω
500Ω
8
2
E
3
B
3
22 CM
0.1µF
5
OTA
+1
C
VOUT
6
243Ω
–5V
OPA860
27 IN
22pF
NOTE: Power supplies and bypassing not shown. The measured SNR performance with 12.5MHz input signal is 57dB with this driver circuit.
FIGURE 7. A Wideband DC-Coupled, Single-Ended to Differential Input Driver Circuit.
12
ADS820
www.ti.com
SBAS037B
The ADS820 can also be configured with a single-ended input
full-scale range of +0.25V to +4.25V by tying the complementary input to the common-mode reference voltage, as shown
in Figure 8. This configuration will result in increased evenorder harmonics, especially at higher input frequencies. However, this trade-off may be quite acceptable for time-domain
applications. The driving amplifier must give adequate performance with a +0.25V to +4.25V output swing in this case.
set halfway between the two references. This feature can be
used to adjust the gain error, improve gain drift, or to change
the full-scale input range of the ADS820. Changing the fullscale range to a lower value has the benefit of easing the
swing requirements of external input amplifiers. The external
references can vary as long as the value of the external top
reference (REFTEXT) is less than or equal to +3.4V, the value
of the external bottom reference (REFBEXT) is greater than or
equal to +1.1V, and the difference between the external
references are greater than or equal to 800mV.
For the differential configuration, the full-scale input range
will be set to the external reference values that are
selected. For the single-ended mode, the input range is
2 • (REFTEXT – REFBEXT), with the common-mode being
centered at (REFTEXT + REFBEXT)/2. Refer to the typical
performance curves for expected performance versus fullscale input range.
22 CM
0.1µF
ADS820
Single-Ended
Input Signal
26 IN
27 IN
22pF
The circuit in Figure 9 works completely on a single +5V
supply. As a reference element, it uses micro-power reference REF1004-2.5, which is set to a quiescent current of
0.1mA. Amplifier A2 is configured as a follower to buffer the
+1.25V generated from the resistor divider. To provide the
necessary current drive, a pull-down resistor, RP, is added.
Full Scale = +0.25V to +4.25V with internal references.
FIGURE 8. Single-Ended Input Connection.
EXTERNAL REFERENCES AND
ADJUSTMENT OF FULL-SCALE RANGE
Amplifier A1 is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor again
relieves the op amp from providing the full current drive. The
value of the pull-up and pull-down resistors is not critical and
can be varied to optimize power consumption. The need for
pull-up/down resistors depends only on the drive capability of
the selected drive amplifiers and thus can be omitted.
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V and
+3.25V references may be overridden by external references
that have at least 18mA (at room temperature) of output drive
capability. In this instance, the common-mode voltage will be
+5V
A1
1/2
OPA2234
+5V
RP
220Ω
Top
Reference
+2.5V to +3.25V
2kΩ
10kΩ
6.2kΩ
10kΩ
REF1004
+2.5V
A2
0.1µF
1/2
OPA2234
10kΩ(1)
+1.25V
10kΩ
Bottom
Reference
RP
220Ω
10kΩ(1)
NOTE: (1) Use parts alternatively for adjustment capability.
FIGURE 9. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
ADS820
SBAS037B
www.ti.com
13
PC-BOARD LAYOUT AND BYPASSING
A well-designed, clean PC-board layout will assure proper
operation and clean spectral response. Proper grounding
and bypassing, short lead lengths, and the use of ground
planes are particularly important for high frequency circuits.
Multilayer PC boards are recommended for best performance but if carefully designed, a two-sided pc board with
large, heavy ground planes can give excellent results. It is
recommended that the analog and digital ground pins of the
ADS820 be connected directly to the analog ground plane. In
our experience, this gives the most consistent results. The
A/D converter power-supply commons should be tied together at the analog ground plane. Power supplies should be
bypassed with 0.1µF ceramic capacitors as close to the pin
as possible.
DYNAMIC PERFORMANCE DEFINITIONS
1. Signal-to-Noise-and-Distortion Ratio (SINAD):
10 log
Sinewave Signal Power
Noise + Harmonic Power (first 15 harmonics)
2. Signal-to-Noise Ratio (SNR):
10 log
Sinewave Signal Power
Noise Power
3. Intermodulation Distortion (IMD):
DYNAMIC PERFORMANCE TESTING
The ADS820 is a high-performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high-resolution FFT measurements to be made without using
data windowing functions. A low jitter signal generator such
as the HP8644A for the test signal, phase-locked with a low
jitter HP8022A pulse generator for the A/D converter clock,
14
gives excellent results. Low-pass filtering (or bandpass filtering) of test signals is absolutely necessary to test the low
distortion of the ADS820. Using a signal amplitude slightly
lower than full scale will allow a small amount of “headroom”
so that noise or DC-offset voltage will not overrange the
A/D converter and cause clipping on signal peaks.
10 log
Highest IMD Pr oduct Power ( to 5th order )
Sinewave Signal Power
IMD is referenced to the larger of the test signals f1 or f2. Five
“bins” either side of peak are used for calculation of fundamental and harmonic power. The “0” frequency bin (DC) is
not included in these calculations, as it is of little importance
in dynamic signal processing applications.
ADS820
www.ti.com
SBAS037B
FIGURE 10. ADS820 Interface Schematic with AC-Coupling and External Buffers.
ADS820
SBAS037B
www.ti.com
15
R2
50Ω
AC Input
Signal
Mini-Circuits
TT1-6-KK81
or equivalent
0.1µF
0.1µF
Ext
Clk
22pF
R1
50Ω
22pF
(1)
0.1µF
GND
IN
IN
GND
+VS
REFT
CM
REFB
+VS
MSBI
OE
+VS
CLK
+VS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS820
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
MSB
LSB
DNC
DNC
GND
NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
0.1µF
0.1µF
0.1µF
0.1µF
+5V
Dir
19
1
G+
3
2
17
18
4
5
15
16
6
14
8
7
12
13
9
2
11
19
1
18
–541
4
16
G+
5
15
Dir
6
14
3
7
13
17
9
8
12
–541
11
PACKAGE OPTION ADDENDUM
www.ti.com
21-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
ADS820E
OBSOLETE
SSOP
DB
28
TBD
Call TI
Call TI
ADS820E/1K
OBSOLETE
SSOP
DB
28
TBD
Call TI
Call TI
ADS820U
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
ADS820UG4
ACTIVE
SOIC
DW
28
20
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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