ON NTB125N02R Power mosfet 125 a, 24 v n−channel to−220, d2pak Datasheet

NTB125N02R, NTP125N02R
Power MOSFET
125 A, 24 V N−Channel
TO−220, D2PAK
Features
• Planar HD3e Process for Fast Switching Performance
• Body Diode for Low trr and Qrr and Optimized for Synchronous
•
•
•
•
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125 AMPERES, 24 VOLTS
RDS(on) = 3.7 mW (Typ)
Operation
Low Ciss to Minimize Driver Loss
Optimized Qgd and RDS(on) for Shoot−through Protection
Low Gate Charge
Pb−Free Packages are Available
D
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
24
Vdc
Gate−to−Source Voltage − Continuous
VGS
±20
Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current −
Continuous @ TC = 25°C, Chip
Continuous @ TC = 25°C, Limited by Package
Continuous @ TA = 25°C, Limited by Wires
Single Pulse (tp = 10 ms)
RqJC
PD
1.1
113.6
°C/W
W
ID
ID
ID
ID
125
120.5
95
250
A
A
A
A
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
46
2.72
18.6
°C/W
W
A
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RqJA
PD
ID
63
1.98
15.9
°C/W
W
A
Operating and Storage Temperature Range
TJ, Tstg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 15.5 Apk,
L = 1 mH, RG = 25 W)
EAS
120
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
S
MARKING
DIAGRAMS
4
TO−220AB
CASE 221A
STYLE 5
1
2
1
125N2RG
AYWW
3
4
2
D2PAK
CASE 418AA
STYLE 2
125N2G
AYWW
3
°C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
PIN ASSIGNMENT
125N2x
x
A
Y
WW
G
= Device Code
=R
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
PIN
FUNCTION
1
Gate
2
Drain
3
Source
4
Drain
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 7
G
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
Publication Order Number:
NTB125N02R/D
NTB125N02R, NTP125N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Symbol
Characteristics
Min
Typ
Max
25
−
28
15
−
−
−
−
−
−
1.5
10
−
−
±100
1.0
−
1.5
5.0
2.0
−
−
−
−
−
3.7
4.9
3.7
4.7
−
−
4.6
6.2
−
44
−
Ciss
−
2710
3440
Coss
−
1105
1670
Crss
−
227
640
td(on)
−
11
22
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 110 Adc)
(VGS = 4.5 Vdc, ID = 55 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 4.5 Vdc, ID = 20 Adc)
RDS(on)
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)
Vdc
mV/°C
mW
gFS
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 20 Vdc, VGS = 0 V, f = 1 MHz)
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 40 Adc, RG = 3 W)
Turn−Off Delay Time
Fall Time
Gate Charge
(VGS = 4.5 Vdc, ID = 40 Adc,
VDS = 10 Vdc) (Note 3)
ns
tr
−
39
80
td(off)
−
27
40
tf
−
21
40
QT
−
23.6
28
Q1
−
5.1
−
Q2
−
11
−
VSD
−
−
−
0.82
0.99
0.65
1.2
−
−
Vdc
trr
−
36.5
−
ns
ta
−
17.7
−
tb
−
18.8
−
QRR
−
0.024
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 20 Adc, VGS = 0 Vdc) (Note 3)
(IS = 55 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
mC
3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping†
NTP125N02R
TO−220AB
50 Units / Rail
NTP125N02RG
TO−220AB
(Pb−Free)
50 Units / Rail
NTB125N02R
D2PAK
50 Units / Rail
NTB125N02RG
D2PAK
50 Units / Rail
Device
(Pb−Free)
D2PAK
800 Units / Tape & Reel
D2PAK
(Pb−Free)
800 Units / Tape & Reel
NTB125N02RT4
NTB125N02RT4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTB125N02R, NTP125N02R
200
200
3.5 V
4.5 V
160
5.0 V
6.0 V
8.0 V
10 V
120
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
4.0 V
3.0 V
80
VGS = 2.5 V
40
0
2
8
6
4
80
TJ = 125°C
TJ = 25°C
40
0
10
TJ = −55°C
0.8
2.4
1.6
3.2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.01
VGS = 10 V
0.008
TJ = 125°C
0.006
TJ = 25°C
0.004
TJ = −55°C
0.002
0
80
40
120
160
200
4.0
0.01
VGS = 4.5 V
TJ = 125°C
0.008
0.006
TJ = 25°C
TJ = −55°C
0.004
0.002
0
40
80
120
160
200
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
100,000
1.8
1.6
VGS = 0 V
ID = 55 A
VGS = 4.5 V
TJ = 150°C
10,000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
120
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
VDS ≥ 10 V
160
1.4
1.2
1.0
TJ = 125°C
1000
TJ = 100°C
100
0.8
0.6
−50
10
−25
0
25
50
75
100
125
150
0
4.0
8.0
12
16
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
24
7000
VDS = 0 V VGS = 0 V
Ciss
C, CAPACITANCE (pF)
6000
5000
Crss
4000
Ciss
3000
2000
Coss
1000
Crss
TJ = 25°C
0
10
0
5
VGS
5
10
15
20
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB125N02R, NTP125N02R
10
8.0
VGS
6.0
QT
4.0
Q1
Q2
2.0
ID = 40 A
TJ = 25°C
0
0
8
VDS
16
24
32
40
48
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
60
IS, SOURCE CURRENT (AMPS)
100
tr
td(off)
tf
td(on)
10
1
10
100
VGS = 0 V
TJ = 25°C
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
ID, DRAIN CURRENT (AMPS)
t, TIME (ns)
VDS = 10 V
ID = 40 A
VGS = 10 V
VGS = 20 V
SINGLE PULSE
TC = 25°C
100 ms
100
1 ms
10 ms
10
dc
RDS(on) Limit
Thermal Limit
Package Limit
1.0
0.1
1.0
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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4
100
1.0
NTB125N02R, NTP125N02R
Normalized to RqJC at Steady State
0.1
r(t),
EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)
1
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
Figure 12. Thermal Response
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5
0.1
1
10
NTB125N02R, NTP125N02R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
J
K
M
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D 3 PL
0.13 (0.005)
T B
M
STYLE 2:
PIN 1.
2.
3.
4.
M
VARIABLE
CONFIGURATION
ZONE
U
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
0.310
−−−
0.100 BSC
0.018 0.025
0.090
0.110
0.280
−−−
0.575 0.625
0.045 0.055
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.92
1.14
1.40
7.87
−−−
2.54 BSC
0.46
0.64
2.29
2.79
7.11
−−−
14.60 15.88
1.14
1.40
NTB125N02R, NTP125N02R
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
−T−
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
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7
For additional information, please contact your
local Sales Representative.
NTB125N02R/D
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