ETC1 BUS-61560-390W Mil-std-1553b notice 2 advanced integrated mux hybrids with enhanced rt features (aim-hyer) Datasheet

BUS-61559 SERIES
MIL-STD-1553B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’er)
DESCRIPTION
DDC’s BUS-61559 series of Advanced
Integrated Mux Hybrids with enhanced
RT Features (AIM-HY’er) comprise a
complete interface between a microprocessor and a MIL-STD-1553B
Notice 2 bus, implementing Bus
Controller (BC), Remote Terminal (RX,
and Monitor Terminal (MT) modes.
Packaged in a single 78-pin DIP or
82-pin flat package the BUS-61559
series contains dual low-power transceivers and encoder/decoders, complete BC/RT/MT protocol logic, memory
management and interrupt logic, 8K x 16
of shared static RAM, and a direct,
buffered interface to a host processor bus.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
3838. Other salient features of the
BUS-61559 serve to provide the benefits of reduced board space requirements enhanced software flexibility,
and reduced host processor overhead
FEATURES
buffers to provide a direct interface to
a host processor bus. Alternatively,
the buffers may be operated in a fully
transparent mode in order to interface
to up to 64K words of external shared
RAM and/or connect directly to a component set supporting the 20 MHz
STANAG-3910 bus.
• Complete Integrated 1553B
Notice 2 Interface Terminal
• Functlonal Superset of BUS61553 AlM-HYSeries
• Internal Address and Data
The memory management scheme
for RT mode prevails an option for
separation of broadcast data, in compliance with 1553B Notice 2. A circular buffer option for RT message data
blocks offloads the host processor for
bulk data transfer applications.
Buffers for Dlrect Interface to
Processor Bus
• RT Subaddress Circular Buffers
to Support Bulk Data Transfers
• Optlonal Separatlon of
Another feature besides those listed
to the right, is a transmitter inhibit control for the individual bus channels.
RT Broadcast Data
• Internal Interrupt Status and
The BUS-61559 series hybrids operate over the full military temperature
range of -55 to +125”C and MIL-PRF38534 processing is available. The
hybrids are ideal for demanding military and industrial microprocessor-toThe BUS-61559 contains internal
1553 applications
address latches and bidirectional data
(ILLEGALIZATION ILLENA
ENABLE)
BUS-25679
8
1
7
2
5
4
3
• Internal ST Command
Illegalization
• MIL-PRF-38534 Processing
Available
8K x 16
DUAL
PORT
RAM
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
LOW-POWER
TRANSCEIVER
A
(BROADCAST
ENABLE)
MEMORY ADDRESS
RTFAIL
(RTFAIL,
RTFLAG)
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
RTFLAG
(PROCESSOR
DATA)
A15-A∅
(PROCESSOR
ADDRESS)
ADDR_LAT (ADDRESS
MEMORY
IOEN, READYD
MANAGEMENT,
INT
SHARED
MEMEN-OUT,MEMWR, MEMOE
RAM/
PROCESSOR
MEMENA-IN
INTERFACE,
SSFLAG
INTERRUPT
LOGIC
TAGCLK
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
BU-61559 BLOCK DIAGRAM
© 1990, 1999 Data Device Corporation
ADDRESS
LATCHES/
BUFFERS*
D15-D∅
LATCH
CONTROL)
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
RTAD 4-∅, RTADP
BRO_ENA
DATA
BUFFERS*
MEMORY DATA
TX_INH_A
(RT ADDRESS)
CLK IN (16MHz)
LOW-POWER
TRANSCEIVER
A
TX_INH_A
BUS-25679
8
1
7
2
5
4
3
ILLEGALLIZATION
LOGIC
Time Tag Registers
(PROCESSOR
CONTROL)
(INTERRUPT
REQUEST)
(MEMORY
CONTROL)
(SUBSYSTEM
FLAG)
(TIME TAG
CLOCK)
ORDERING INFORMATION
BUS-615XX- XX0X*
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See page xiii.)
1 = MIL-PRF-38534 Compliant
2 = B**
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B** with PIND Testing
7 = B** with Solder Dip
8 = B** with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See page xiii.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply and Packaging
59 = +5 V/-15 V DDIP
60 = +5 V/-12 V DIP
69 = +5 V/-15 V Flat Pack
70 = +5 V/-12 V Flat Pack
71 = +5 V Flat Pack
*-601 version also available = MIL-STD-1760 compatible with fully compliant
MIL-PRF-38534 Processing Available
2
NOTES
3
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
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World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
PRINTED IN THE U.S.A.
K-ABR
4
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