Cadeka CLC1001 Ultra-low noise amplifier Datasheet

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
Comlinear CLC1001
®
Ultra-Low Noise Amplifier
The COMLINEAR CLC1001(single) is a high-performance, voltage feedback amplifier with ultra-low input voltage noise, 0.6nV/√Hz. The CLC1001
provides 2.1GHz gain bandwidth product and 410V/μs slew rate making it
well suited for high-speed data acquisition systems requiring high levels of
sensitivity and signal integrity. This COMLINEAR high-performance amplifier
also offers low input offset voltage.
The COMLINEAR CLC1001 is designed to operate from 4V to 12V supplies.
It consumes only 12.5mA of supply current per channel and offers a power
saving disable pin that disables the amplifier and decreases the supply current to below 225μA. The CLC1001 amplifier operates over the extended
temperature range of -40°C to +125°C.
APPLICATIONS
n Transimpedance amplifiers
n Pre-amplifier
n Low noise signal processing
n Medical instrumentation
n Probe equipment
n Test equipment
n Ultrasound channel amplifier
If a lower minimum stable gain is required, the CLC1002 offers a minimum
stable gain of 5.
Typical Application - Single Supply Photodiode Amplifier
Comlinear CLC1001 Ultra-Low Noise Amplifier
General Description
FEATURES
n 0.6 nV/√Hz input voltage noise
n 1mV maximum input offset voltage
n 2.1GHz gain bandwidth product
n Minimum stable gain of 10
n 410V/μs slew rate
n 130mA output current
n -40°C to +125°C operating temperature
range
n Fully specified at 5V and ±5V supplies
n CLC1001: Lead-free SOT23-6, SOIC-8
n Future option CLC2001
Rev 1D
Ordering Information
Part Number
Package
Pb-Free
RoHS Compliant
Operating Temperature Range
Packaging Method
CLC1001IST6X
SOT23-6
Yes
Yes
-40°C to +85°C
Reel
CLC1001ISO8X*
SOIC-8
Yes
Yes
-40°C to +85°C
Reel
CLC1001ISO8*
SOIC-8
Yes
Yes
-40°C to +85°C
Rail
CLC1001AST6X
SOT23-6
Yes
Yes
-40°C to +125°C
Reel
CLC1001ASO8X*
SOIC-8
Yes
Yes
-40°C to +125°C
Reel
CLC1001ASO8*
SOIC-8
Yes
Yes
-40°C to +125°C
Rail
*Preliminary Product Information
Moisture sensitivity level for all parts is MSL-1.
©2008 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
SOT23 Pin Assignments
SOT23 Pin Configuration
1
-V S
2
+IN
3
+
-
6
+VS
5
DIS
-IN
4
Pin Name
Description
1
OUT
Output
2
-VS
Negative supply
3
+IN
Positive input
4
-IN
Negative input
5
DIS
Disable. Enabled if pin is left floating or pulled
above VON, disabled if pin is grounded or pulled
below VOFF.
6
+VS
Positive supply
Comlinear CLC1001 Ultra-Low Noise Amplifier
OUT
Pin No.
SOIC Pin Assignments
SOIC Pin Configuration
Pin No.
Pin Name
Description
1
NC
No connect
NC
1
8
DIS
2
-IN1
Negative input
+IN1
Positive input
2
7
+VS
3
-IN1
4
-VS
Negative supply
NC
No connect
+IN1
3
6
OUT
5
-V S
OUT
Output
5
NC
6
4
7
+VS
Positive supply
8
DIS
Disable. Enabled if pin is left floating or pulled
above VON, disabled if pin is grounded or pulled
below VOFF.
Rev 1D
©2007-2008 CADEKA Microcircuits LLC www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Supply Voltage
Input Voltage Range
Min
Max
Unit
0
-Vs -0.5V
14
+Vs +0.5V
V
V
Comlinear CLC1001 Ultra-Low Noise Amplifier
Parameter
Reliability Information
Parameter
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
6-Lead SOT23
8-Lead SOIC
Min
Typ
-65
Max
Unit
150
150
260
°C
°C
°C
177
100
°C/W
°C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
ESD Protection
Product
SOT23-6
Human Body Model (HBM)
Charged Device Model (CDM)
2kV
2kV
Rev 1D
Recommended Operating Conditions
Parameter
Min
Operating Temperature Range (CLC1001I)
Operating Temperature Range (CLC1001A)
Supply Voltage Range
-40
-40
4
©2007-2008 CADEKA Microcircuits LLC Typ
Max
Unit
+85
+125
12
°C
°C
V
www.cadeka.com
3
Data Sheet
Electrical Characteristics at +5V
TA = 25°C, Vs = +5V, Rf = 200Ω, RL = 500Ω to VS/2, G = 10; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
-3dB Gain Bandwidth Product
G = +40, VOUT = 0.2Vpp
2000
MHz
BWSS
-3dB Bandwidth
G = +10, VOUT = 0.2Vpp
265
MHz
BWLS
Large Signal Bandwidth
G = +10, VOUT = 2Vpp
105
MHz
BW0.1dBSS
0.1dB Gain Flatness Small Signal
G = +10, VOUT = 0.2Vpp
37
MHz
BW0.1dBLS
0.1dB Gain Flatness Large Signal
G = +10, VOUT = 2Vpp
36
MHz
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
2.4
ns
tS
Settling Time to 0.1%
VOUT = 1V step
11
ns
OS
Overshoot
VOUT = 1V step
6
%
SR
Slew Rate
4V step
360
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
1Vpp, 10MHz
-80
dBc
HD3
3rd Harmonic Distortion
1Vpp, 10MHz
-83
dBc
THD
Total Harmonic Distortion
1Vpp, 10MHz
-79
dB
en
Input Voltage Noise
> 100kHz
0.6
nV/√Hz
in
Input Current Noise
> 100kHz
4.2
pA/√Hz
DC Performance
Input Offset Voltage
0.1
mV
dVIO
Average Drift
2.7
µV/°C
Ib
Input Bias Current
28
µA
dIb
Average Drift
45
nA/°C
Io
Input Offset Current
0.5
µA
PSRR
Power Supply Rejection Ratio
DC
83
dB
AOL
Open-Loop Gain
VOUT = VS / 2
82
dB
IS
Supply Current
per channel
12
mA
1V step, 1% settling
100
ns
900
ns
Disable Characteristics
tON
Turn On Time
tOFF
Turn Off Time
OFFISO
Off Isolation
OFFCOUT
Off Output Capacitance
VOFF
Power Down Voltage
VON
ISD
2Vpp, 5MHz
80
dB
5.7
pF
Disabled if DIS pin is grounded or pulled below VOFF
Disabled if DIS < 1.5
V
Enable Voltage
Enabled if DIS pin is floating or pulled above VON
Enabled if DIS > 3
V
Disable Supply Current
No Load, DIS pin tied to ground
130
µA
Non-inverting
2.6
MΩ
1.6
pF
0.8 to
5.1
V
85
dB
RL = 500Ω
0.93 to 4
V
RL = 2kΩ
0.9 to
4.1
V
±130
mA
±150
mA
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio
DC , Vcm=1.5V to 4V
Output Characteristics
VOUT
Output Voltage Swing
IOUT
Output Current
ISC
Short-Circuit Output Current
VOUT = VS / 2
Notes:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC www.cadeka.com
4
Rev 1D
VIO
Comlinear CLC1001 Ultra-Low Noise Amplifier
GBWP
Data Sheet
Electrical Characteristics at ±5V
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω , G = 10; unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
-3dB Gain Bandwidth Product
G = +40, VOUT = 0.2Vpp
2100
MHz
BWSS
-3dB Bandwidth
G = +10, VOUT = 0.2Vpp
284
MHz
BWLS
Large Signal Bandwidth
G = +10, VOUT = 2Vpp
117
MHz
BW0.1dBSS
0.1dB Gain Flatness Small Signal
G = +10, VOUT = 0.2Vpp
42
MHz
BW0.1dBLS
0.1dB Gain Flatness Large Signal
G = +10, VOUT = 2Vpp
47
MHz
Time Domain Response
tR, tF
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
2.2
ns
tS
Settling Time to 0.1%
VOUT = 1V step
11
ns
OS
Overshoot
VOUT = 1V step
3
%
SR
Slew Rate
4V step
410
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
2Vpp, 10MHz
-81
dBc
HD3
3rd Harmonic Distortion
2Vpp, 10MHz
-75
dBc
THD
Total Harmonic Distortion
2Vpp, 5MHz
-74
dB
en
Input Voltage Noise
> 100kHz
0.6
nV/√Hz
in
Input Current Noise
> 100kHz
4.2
pA/√Hz
DC Performance
VIO
dVIO
Ib
Input Offset Voltage(1)
-1
0.35
Average Drift
1
4.4
Input Bias Current (1)
-60
mV
µV/°C
30
60
44
µA
Average Drift
Io
Input Offset Current
PSRR
Power Supply Rejection Ratio
DC
78
83
AOL
Open-Loop Gain (1)
VOUT = VS / 2
74
83
IS
Supply Current (1)
per channel
12.5
1V step, 1% settling
125
ns
840
ns
nA/°C
0.8
(1)
6
µA
dB
dB
16
mA
Disable Characteristics
tON
Turn On Time
tOFF
Turn Off Time
OFFISO
Off Isolation
OFFCOUT
Off Output Capacitance
VOFF
Power Down Voltage
VON
ISD
2Vpp, 5MHz
80
dB
5.6
pF
Disabled if DIS pin is grounded or pulled below VOFF
Disabled if DIS < 1.3
V
Enable Voltage
Enabled if DIS pin is floating or pulled above VON
Enabled if DIS > 3
Disable Supply Current (1)
No Load, DIS pin tied to ground
180
V
225
µA
Input Characteristics
RIN
Input Resistance
CIN
Input Capacitance
CMIR
Common Mode Input Range
CMRR
Common Mode Rejection Ratio (1)
Non-inverting
DC , Vcm=-3.5V to 4V
4
MΩ
1.5
pF
-4.3 to
5.1
V
75
90
dB
-3.8
±4
Output Characteristics
VOUT
Output Voltage Swing
IOUT
Output Current
ISC
Short-Circuit Output Current
RL = 500Ω (1)
RL = 2kΩ
VOUT = VS / 2
3.8
V
±4
V
±130
mA
±160
mA
Notes:
1. 100% tested at 25°C
©2007-2008 CADEKA Microcircuits LLC www.cadeka.com
5
Rev 1D
dIb
Comlinear CLC1001 Ultra-Low Noise Amplifier
GBWP
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
Non-Inverting Frequency Response
Inverting Frequency Response
Normalized Gain (dB)
Normalized Gain (dB)
3
0
G = +10
G = +20
-3
G = +40
-6
0
G = -10
-3
G = -20
G = -40
-6
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
10
Frequency (MHz)
100
1000
Frequency (MHz)
Frequency Response vs. CL
Frequency Response vs. RL
3
3
Normalized Gain (dB)
0
CL = 100pF
Rs = 13Ω
-3
CL = 47pF
Rs = 20Ω
CL = 22pF
Rs = 33Ω
-6
VOUT = 0.2Vpp
0
Rl = 1K
Rl = 2K
-3
Rl = 5K
Rev 1D
Normalized Gain (dB)
CL = 470pF
Rs = 4.3Ω
-6
CL = 10pF
Rs = 43Ω
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
100
1000
-3dB Bandwidth vs. Output Voltage
1
300
0
250
-1
-3dB Bandwidth (MHz)
Normalized Gain (dB)
10
Frequency (MHz)
Frequency Response vs. VOUT
VOUT = 4Vpp
-2
VOUT = 3Vpp
-3
VOUT = 2Vpp
-4
-5
200
150
100
50
-6
0
-7
0.1
1
10
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC 100
1000
Comlinear CLC1001 Ultra-Low Noise Amplifier
3
0.0
1.0
2.0
3.0
4.0
VOUT (VPP)
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6
Data Sheet
Typical Performance Characteristics
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
Non-Inverting Frequency Response at VS = 5V
Inverting Frequency Response at VS = 5V
Normalized Gain (dB)
Normalized Gain (dB)
3
0
G = +10
-3
G = +20
G = +40
-6
0
G = -10
-3
G = -20
G = -40
-6
VOUT = 0.2Vpp
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
10
100
1000
Frequency (MHz)
Frequency Response vs. CL at VS = 5V
Frequency Response vs. RL at VS = 5V
3
3
Normalized Gain (dB)
0
CL = 100pF
Rs = 15Ω
-3
CL = 47pF
Rs = 22Ω
CL = 22pF
Rs = 36Ω
-6
VOUT = 0.2Vpp
0
Rl = 1K
Rl = 2K
-3
Rl = 5K
Rev 1D
Normalized Gain (dB)
CL = 470pF
Rs = 5Ω
-6
CL = 10pF
Rs = 50Ω
VOUT = 0.2Vpp
-9
-9
0.1
1
10
100
1000
0.1
1
Frequency (MHz)
100
1000
-3dB Bandwidth vs. Output Voltage at VS = 5V
1
300
0
250
-1
-3dB Bandwidth (MHz)
Normalized Gain (dB)
10
Frequency (MHz)
Frequency Response vs. VOUT at VS = 5V
VOUT = 2Vpp
-2
VOUT = 1.5Vpp
-3
VOUT = 1Vpp
-4
-5
200
150
100
50
-6
-7
0
0.1
1
10
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC 100
1000
Comlinear CLC1001 Ultra-Low Noise Amplifier
3
0.0
0.5
1.0
1.5
2.0
VOUT (VPP)
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7
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
Input Voltage Noise at VS = 5V
2.6
2.4
2.4
2.2
2.2
Input Voltage Noise (nV/√Hz)
2.6
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0.2
0
0
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
Input Voltage Noise (>10kHz)
1
10
Input Voltage Noise at VS = 5V (>10kHz)
0.85
0.8
0.8
Input Voltage Noise (nV/√Hz)
0.85
0.75
0.7
0.65
0.6
0.55
0.75
0.7
0.65
Rev 1D
Input Voltage Noise (nV/√Hz)
0.1
Frequency (MHz)
Frequency (MHz)
0.6
0.55
0.5
0.5
0.01
0.1
10
10
1
0.01
0.1
1
10
10
Frequency (MHz)
Frequency (MHz)
ROUT vs. Frequency
ROUT (Ω)
10
1
0.1
0.01
0.001
0.01
0.1
1
10
100
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC Comlinear CLC1001 Ultra-Low Noise Amplifier
Input Voltage Noise (nV/√Hz)
Input Voltage Noise
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8
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
2nd Harmonic Distortion vs. RL
3rd Harmonic Distortion vs. RL
-65
-75
RL = 500Ω
Distortion (dBc)
Distortion (dBc)
-75
-85
-95
RL = 1kΩ
-105
RL = 500Ω
-85
-95
RL = 1kΩ
-105
VOUT = 1Vpp
VOUT = 1Vpp
-115
-115
5
10
15
20
5
10
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT
-55
-60
20MHz
-70
20MHz
-65
10MHz
-75
10MHz
Distortion (dBc)
-70
-80
-85
5MHz
-90
-95
-75
-80
-85
-90
Rev 1D
Distortion (dBc)
20
3rd Harmonic Distortion vs. VOUT
-65
5MHz
-95
-100
-100
RL = 500Ω
-105
0.5
RL = 500Ω
-105
0.75
1
1.25
1.5
1.75
2
2.25
2.5
0.5
0.75
Output Amplitude (Vpp)
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp)
2nd Harmonic Distortion vs. Gain
3rd Harmonic Distortion vs. Gain
-50
-50
-55
-55
-60
-60
AV+40
-65
Distortion (dBc)
-65
Distortion (dBc)
15
Frequency (MHz)
AV+20
-70
-75
-80
-85
-90
5
-80
-85
RL = 500Ω
-100
10
15
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC 20
AV+10
VOUT = 1VPP
-95
RL = 500Ω
-100
AV+20
-90
AV+10
VOUT = 1VPP
-95
AV+40
-70
-75
5
10
Comlinear CLC1001 Ultra-Low Noise Amplifier
-65
15
20
Frequency (MHz)
www.cadeka.com
9
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
2nd Harmonic Distortion vs. RL at VS = 5V
3rd Harmonic Distortion vs. RL at VS = 5V
-65
RL = 500Ω
RL = 500Ω
-75
Distortion (dBc)
Distortion (dBc)
-75
-85
-95
RL = 1kΩ
-105
-85
-95
RL = 1kΩ
-105
VOUT = 1Vpp
VOUT = 1Vpp
-115
-115
5
10
15
20
5
10
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT at VS = 5V
-55
-60
-60
20MHz
-65
-65
Distortion (dBc)
-70
-70
20MHz
-75
-80
-85
5MHz
0.5
-85
10MHz
-90
-100
RL = 500Ω
-95
-80
RL = 500Ω
-105
0.75
1
1.25
1.5
1.75
5MHz
-95
10MHz
-90
-75
Rev 1D
Distortion (dBc)
20
3rd Harmonic Distortion vs. VOUT at VS = 5V
-55
2
2.25
2.5
0.5
0.75
Output Amplitude (Vpp)
1
1.25
1.5
1.75
2
2.25
2.5
Output Amplitude (Vpp)
2nd Harmonic Distortion vs. Gain at VS = 5V
3rd Harmonic Distortion vs. Gain at VS = 5V
-50
-50
-55
-55
AV+40
-60
-60
AV+20
-65
Distortion (dBc)
-65
Distortion (dBc)
15
Frequency (MHz)
-70
-75
-80
-85
AV+10
-70
AV+20
-75
-80
-85
AV+10
-90
-90
VOUT = 1VPP
-95
-100
5
AV+40
VOUT = 1VPP
-95
RL = 500Ω
RL = 500Ω
-100
15
10
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC 20
5
10
Comlinear CLC1001 Ultra-Low Noise Amplifier
-65
15
20
Frequency (MHz)
www.cadeka.com
10
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
Small Signal Pulse Response
Small Signal Pulse Response at VS = 5V
2.6
0.05
2.55
Voltage (V)
0.1
Voltage (V)
2.65
0
2.5
-0.05
2.45
-0.1
2.4
-0.15
2.35
0
50
100
150
200
0
50
100
Time (ns)
Large Signal Pulse Response
200
Large Signal Pulse Response at VS = 5V
3
4
2
3.5
1
3
Voltage (V)
Voltage (V)
150
Time (ns)
0
2.5
2
-2
1.5
-3
Rev 1D
-1
1
0
50
100
150
200
0
50
100
Time (ns)
5.5
200
Disable Response
1.5
5.5
1.5
Disable
Enable
4.5
150
Time (ns)
Enable Response
4.5
1.5
Disable Voltage (V)
Output
3.5
Output
2.5
0.5
1.5
0
0.5
Output Voltage (V)
0.5
2.5
1
Output Voltage (V)
Enable Voltage (V)
1
3.5
0
0.5
-0.5
-0.5
-50
0
50
100
Time (ns)
©2007-2008 CADEKA Microcircuits LLC 150
200
Comlinear CLC1001 Ultra-Low Noise Amplifier
0.15
-0.5
-100
-0.5
0
100
200
300
400
500
600
700
800
900
Time (ns)
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11
Data Sheet
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 200Ω, RL = 500Ω, G = 10; unless otherwise noted.
Enable Response at VS = 5V
1.5
5.5
Enable
4.5
1.5
Disable
4.5
0.5
1.5
Disable Voltage (V)
Output
2.5
1
3.5
Output
2.5
0.5
1.5
0
0
0.5
0.5
-0.5
-0.5
-50
0
50
100
150
-0.5
200
-0.5
-100
0
100
Time (ns)
300
400
500
600
700
800
900
Off Isolation at VS = 5V
-45
-50
-50
-55
-55
-60
-60
Off Isolation (dB)
-45
-65
-70
-75
-80
-85
-65
-70
-75
-80
Rev 1D
Off Isolation (dB)
200
Time (ns)
Off Isolation
-85
-90
-90
-95
-95
VOUT = 2Vpp
-100
VOUT = 2Vpp
-100
10
1
100
10
1
Frequency (MHz)
PSRR vs. Frequency
100
80
80
60
60
PSRR (dB)
100
40
20
40
20
0
0.001
100
Frequency (MHz)
CMRR vs. Frequency
CMRR (dB)
Output Voltage (V)
3.5
Output Voltage (V)
Enable Voltage (V)
1
0
0.01
0.1
1
Frequency (MHz)
©2007-2008 CADEKA Microcircuits LLC 10
100
Comlinear CLC1001 Ultra-Low Noise Amplifier
5.5
Disable Response at VS = 5V
0.001
0.01
0.1
1
10
100
Frequency (MHz)
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12
Data Sheet
Application Information
total input voltage noise (amp+resistors) versus Rf and
Rg. As the value of Rf increases, the total input referred
noise also increases.
+Vs
Input
6.8μF
0.1μF
+
Output
-
RL
0.1μF
Rg
Rg
G = +21
G = +41
1.5
1.25
1
0.75
0.5
100
1000
G = 1 + (Rf/Rg)
The noise caused by a resistor is modeled with either a
voltage source in series with the resistance:
4kTR
6.8μF
Or a current source in parallel with it:
Output
0.1μF
6.8μF
-Vs
RL
Rf
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Figure 2. Typical Inverting Gain Circuit
Achieving Low Noise in an Application
Making full use of the low noise of the CLC1001 requires
careful consideration of resistor values. The feedback and
gain set resistors (Rf and Rg) and the non-inverting source
impedance (Rsource) all contribute noise to the circuit and
can easily dominate the overall noise if their values are
too high. The datasheet is specified with an Rg of 22.1Ω,
at which point the noise from Rf and Rg is about equal to
the noise from the CLC1001. Lower value resistors could
be used at the expense of more distortion. Figure 3 shows
©2007-2008 CADEKA Microcircuits LLC iR =
Rev 1D
Input
2
1.75
Figure 3: Input Referred Voltage Noise vs. Rf and Rg
6.8μF
0.1μF
+
G = +11
2.25
Rf (Ohms)
Figure 1. Typical Non-Inverting Gain Circuit
R1
2.5
Rf
-Vs
+Vs
2.75
Comlinear CLC1001 Ultra-Low Noise Amplifier
Figures 1 and 2 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Input Referred Noise (nV/rtHz)
Basic Operation
4kT
R
Op amp noise is modeled with three noise sources, en, in
and ii. These three sources are analogous to the DC input
voltage and current errors Vos, Ibn and Ibi.
The noise models must be analyzed in-circuit to determine the effect on the op amp output noise.
Since noise is statistical in nature rather than a continuous
signal, the set of noise sources in circuit add in an RMS
(root mean square) fashion rather than in a linear fashion.
For uncorrelated noise sources, this means you add the
squares of the noise voltages. A typical non-inverting application (see figure 1) results in the following noise at the
output of the op amp:
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13
Data Sheet
e2o = en2
1+
Rf
Rg
2
+ in2Rs 2 1+
Rf
Rg
2
+ ii2R2f
The effective load resistor (Rloadeff) will need to include
the effect of the feedback network. For instance,
op amp noise terms en , in and ii
Rloadeff in figure 3 would be calculated as:
op amp noise terms en, in and ii
RL || (Rf + Rg)
Rf
2
e2Rg
Rf
2
e2Rf
High source impedances are sometimes unavoidable, but
they increase noise from the source impedance and also
make the circuit more sensitive to the op amp current
noise. Analyze all noise sources in the circuit, not just the
op amp itself, to achieve low noise in your application.
Power Dissipation
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value ThetaJA
(ӨJA) is used along with the total die power dissipation.
TJunction = TAmbient + (ӨJA × PD)
Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power
can be calculated as above with the desired signal amplitudes using:
(VLOAD)RMS = VPEAK / √2
( ILOAD)RMS = ( VLOAD)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS
Assuming the load is referenced in the middle of the power rails or Vsupply/2.
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the packages available.
2.5
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Psupply = Vsupply × IRMS supply
Vsupply = VS+ - VSPower delivered to a purely resistive load is:
Pload = ((VLOAD)RMS2)/Rloadeff
©2007-2008 CADEKA Microcircuits LLC Maximum Power Dissipation (W)
Where TAmbient is the temperature of the working environment.
2
SOIC-8
1.5
SOT23-6
1
0.5
0
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
Figure 4. Maximum Power Derating
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14
Rev 1D
Power dissipation should not be a factor when operating under the stated 500Ω load condition. However, applications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operating range.
PD = PQuiescent + PDynamic - PLoad
Comlinear CLC1001 Ultra-Low Noise Amplifier
These measurements are basic and are relatively easy to
with
lab equipment. For design purposes
+
external resistor noiseperform
terms for
Rs,standard
Rg and Rf
+
1+
+
Rg
Rg
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
external resistor noise terms for RS, Rg and Rf
Here, PD can be found from
2
eRs
Data Sheet
Driving Capacitive Loads
3
Rs
-
Output
CL
Rf
Input Voltage (V)
+
2
4
1
2
Output
0
0
Input
-1
-2
-2
-4
RL
-3
-6
0
Rg
50
100
150
200
250
300
350
400
450
Time (us)
Figure 6. Overdrive Recovery
Figure 5. Addition of RS for Driving
Capacitive Loads
Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB
peaking in the frequency response. The Frequency Response vs. CL plots, on page 7, illustrates the response of
the CLC1001.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
RS (Ω)
-3dB BW (MHz)
10
43
266
22
33
228
47
20
192
• Place the 0.1µF capacitor within 0.1 inches of the power pin
100
13
155
470
4.3
84
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic capacitance
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the
amplifier to return to its normal or linear operating point.
The recovery time varies, based on whether the input or
output is overdriven and by how much the range is exceeded. The CLC1001 will typically recover in less than
25ns from an overdrive condition. Figure 6 shows the
CLC1001 in an overdriven condition.
©2007-2008 CADEKA Microcircuits LLC • Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB002
CEB003
Products
CLC1001 in SOT23-5
CLC1001 in SOIC-8
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15
Rev 1D
CL (pF)
Comlinear CLC1001 Ultra-Low Noise Amplifier
Input
6
G = 10
Output Voltage (V)
Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplifier and the load to help improve
stability and settling performance. Refer to Figure 5.
Data Sheet
Evaluation Board Schematics
Comlinear CLC1001 Ultra-Low Noise Amplifier
Evaluation board schematics and layouts are shown in Figures 7-11. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplifier is not
directly connected to the ground plane.
Figure 9. CEB002 Bottom View
Rev 1D
Figure 7. CEB002/CEB003 Schematic
Figure 8. CEB002 Top View
©2007-2008 CADEKA Microcircuits LLC Figure 10. CEB003 Top View
Figure 11. CEB003 Bottom View
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16
Data Sheet
Mechanical Dimensions
SOT23-6 Package
Comlinear CLC1001 Ultra-Low Noise Amplifier
SOIC-8 Package
Rev 1D
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2007-2008 by CADEKA Microcircuits LLC. All rights reserved.
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