MOTOROLA MC74HCTXXXADW Octal 3-state noninverting d flip-flop with lsttl-com Datasheet

SEMICONDUCTOR TECHNICAL DATA
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High–Performance Silicon–Gate CMOS
The MC54/74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with the
rising edge of Clock. The Output Enable does not affect the state of the
flip–flops, but when Output Enable is high, the outputs are forced to the
high–impedance state. Thus, data may be stored even when the outputs
are not enabled.
The HCT374A is identical in function to the HCT574A, which has the
input pins on the opposite side of the package from the output pins. This
device is similar in function to the HCT534A, which has inverting outputs.
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 276 FETs or 69 Equivalent Gates
• Improvements over HCT374
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
2
3
4
5
7
6
8
9
1
13
12
14
15
17
16
18
19
1
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
20
ORDERING INFORMATION
Ceramic
MC54HCTXXXAJ
Plastic
MC74HCTXXXAN
SOIC
MC74HCTXXXADW
SSOP
MC74HCTXXXASD
TSSOP
MC74HCTXXXADT
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
Q1
Q2
Q4
1
SD SUFFIX
SSOP PACKAGE
CASE 940C–03
20
Q0
Q3
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
LOGIC DIAGRAM
D0
NONINVERTING
OUTPUTS
Q5
Q6
20
VCC
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
CLOCK
GND
Q7
1
11
FUNCTION TABLE
PIN 20 = VCC
PIN 10 = GND
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OUTPUT ENABLE
1
Design Criteria
Value
Units
Internal Gate Count*
69
ea.
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
µW
.0075
pJ
Speed Power Product
Inputs
Output
Enable
L
L
L
H
2/97
 Motorola, Inc. 1997
1
Clock
D
Q
L,H,
X
H
L
X
X
H
L
No Change
Z
X = don’t care
Z = high impedance
* Equivalent to a two–input NAND gate.
REV 7
Output
MC54/74HCT374A
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MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
V
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
SSOP or TSSOP Package†
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
SSOP or TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
VCC
V
– 55 to
25_C
85_C
125_C
U i
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout|
6.0 mA
4.5
0.26
0.33
0.4
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
VOH
VOL
Iin
MOTOROLA
Maximum Low–Level Output
Voltage
Maximum Input Leakage Current
2
V
µA
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT374A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
IOZ
Maximum Three–State
Leakage Current
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.5
± 5.0
± 10
µA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
5.5
4.0
40
160
µA
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
≥ –55_C
25_C to 125_C
2.9
2.4
5.5
55
mA
A
NOTE: 1. Total Supply Current = ICC + Σ∆ICC.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
S b l
Symbol
– 55 to
25_C
P
Parameter
85_C
125_C
U i
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
(Figures 1 and 4)
31
39
47
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 2 and 5)
30
38
45
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
P
Power
Di
Dissipation
i i C
Capacitance
i
(P
(Per Fli
Flip–Flop)*
Fl )*
pF
F
65
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, Input tr = tf = 6.0 ns)
Guaranteed Limit
S b l
Symbol
– 55 to
25_C
P
Parameter
85_C
125_C
U i
Unit
tsu
Minimum Setup Time, Data to Clock
(Figure 3)
12
15
18
ns
th
Minimum Hold Time, Clock to Data
(Figure 3)
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
(Figure 1)
12
15
18
ns
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
ns
tr, tf
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC54/74HCT374A
SWITCHING WAVEFORMS
tr
tf
3V
2.7 V
1.3 V
0.3 V
tw
CLOCK
OUTPUT
ENABLE
VCC
GND
GND
Q
1/fmax
tPLH
tPZL
tPLZ
tPZH
tPHZ
Q
tTLH
HIGH
IMPEDANCE
1.3 V
tPHL
90%
1.3 V
10%
Q
1.3 V
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 1.
Figure 2.
VALID
3V
DATA
1.3 V
GND
tsu
th
3V
CLOCK
1.3 V
GND
Figure 3.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH
1 kΩ
OUTPUT
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 4.
Figure 5.
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D
Q
D
C
CLOCK
Q
D3
8
D
C
Q
D4
13
D
C
Q
D5
14
D
C
Q
D6
17
D
C
Q
D7
18
D
C
Q
D
C
Q
C
11
OUTPUT 1
ENABLE
MOTOROLA
D2
7
2
Q0
5
Q1
6
Q2
9
Q3
4
12
Q4
15
Q5
16
Q6
19
Q7
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT374A
OUTLINE DIMENSIONS
20
11
1
10
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
A
L
C
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
N
H
G
D
J
K
M
MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
0_
15 _
0.25
1.02
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
DIM
A
B
C
D
E
F
G
J
K
L
M
N
K
SEATING
PLANE
M
N
E
G
F
J
D
0.25 (0.010)
M
T A
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R X 45 _
C
–T–
18X
G
High–Speed CMOS Logic Data
DL129 — Rev 6
K
SEATING
PLANE
M
T B
M
M
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A–
20
20 PL
0.25 (0.010)
20 PL
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
5
MOTOROLA
MC54/74HCT374A
OUTLINE DIMENSIONS
SD SUFFIX
PLASTIC SSOP PACKAGE
CASE 940C–03
ISSUE B
K REF
0.12 (0.005)
20X
20
L/2
T U
M
S
V
0.25 (0.010)
S
N
M
11
N
B
L
F
DETAIL E
PIN 1
IDENT
1
10
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K
–U–
A
–V–
0.20 (0.008)
J
T U
M
J1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF K DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR INTRUSION SHALL NOT
REDUCE DIMENSION K BY MORE THAN 0.07 (0.002)
AT LEAST MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE
ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
K1
S
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N–N
0.076 (0.003)
–T–
SEATING
PLANE
–W–
C
D
G
DETAIL E
H
20X
0.15 (0.006) T U
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
K REF
0.10 (0.004)
S
M
T U
S
V
S
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
K
K1
2X
L/2
20
11
J J1
B
–U–
L
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
N
F
DETAIL E
–W–
C
D
G
H
DETAIL E
0.100 (0.004)
–T– SEATING
INCHES
MIN
MAX
0.278
0.288
0.205
0.212
0.068
0.078
0.002
0.008
0.024
0.037
0.026 BSC
0.023
0.030
0.003
0.008
0.003
0.006
0.010
0.015
0.010
0.013
0.301
0.311
0_
8_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
A
–V–
MILLIMETERS
MIN
MAX
7.07
7.33
5.20
5.38
1.73
1.99
0.05
0.21
0.63
0.95
0.65 BSC
0.59
0.75
0.09
0.20
0.09
0.16
0.25
0.38
0.25
0.33
7.65
7.90
0_
8_
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT374A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
7
MC74HCT374A/D
MOTOROLA
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