Sony CXA3067 Wide band fsk receiver Datasheet

CXA3067M
Wide Band FSK Receiver
Description
The CXA3067M is an integrated circuit designed
for CATV wide band FSK receiver. This monolithic
IC is composed of local oscillator, double balanced
mixer, limiter, FM detector, data shaper and PLL
circuit in a single chip.
Features
• Built in PLL
• 3 bits 3 states frequency selection
• Applied for 4 reference frequency
•
•
•
•
(7.15625/7.15909/14.3125/14.31818 MHz)
Compatible with external reference clock and X’tal
oscillator
Balanced oscillator and double balanced mixer for
low L.O. leakage
Low power consumption
SOP 30 pin package
30 pin SOP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VCC
–0.3 to +5.5
• Storage temperature
Tstg –55 to +150
Operating Conditions
• Supply voltage
VCC
• Operating temperature
Topr
4.75 to 5.3
–25 to +75
V
°C
V
°C
Function
• Oscillator
• Mixer
• PLL
• Limiter
• FSK detector
• Data shaper
Applications
FSK receiver for CATV
Structure
Bipolar silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E97657A89-TE
CXA3067M
FSET2
FSET3
REFSW
MIXIN
RFVCC
RFEM
RFIN
RFGND
IFGND
IFVCC
NOUT
POUT
LF2
LF1
DETIN
Pin configuration and Block diagram
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
V.REG
DATA
SHAPER
FREQ
SELECT
MIX
MAIN
DIVIDER
PHASE
DET
REF
DIVIDER
DET
CHARGE
PUMP
SCALER
OSC
LIM
FSET1
RDSW
CPLF
VT
OSC1
9
10
11
12
13
14
15
LIMOUT
XTAL
8
GND
7
BYP
6
LIMIN
5
DVCC
4
MIXOUT
3
DGND
2
OSC2
1
REFIN
REF
OSC
—2—
CXA3067M
Pin Description and Equivalent Circuit
Pin
No.
1
Symbol
REFIN
Typical
voltage (V)
Equivalent circuit
Description
DVCC
11
3.4
External clock input
and X’tal connection for
reference oscillator.
1
500
2
2
XTAL
4.0
9
X’tal connection for
reference oscillator.
DGND
11 DVCC
20k
3
FSET1
2.5
(OPEN)
3
20k
9 DGND
11 DVCC
20k
4
RDSW
3.0
(OPEN)
4
25k
30k
9 DGND
11
5
CPLF
The pin for channel selection.
The condition of pin 3 has
3 states.
Connect to 5 V source for “Hi”
selection and connect to GND for
“Low” selection and leave open.
Reference frequency selection.
Connect to GND when reference
frequency is 14.3125 MHz or
14.31818 MHz and leave open
when reference frequency is
7.15625 MHz or 7.15909 MHz.
DVCC
Charge pump output.
Connect to loop filter.
10k
2.0
100
5
100
6
6
VT
Connect to loop filter.
OSC tuning voltage output.
0.3 to VCC
9
DGND
—3—
CXA3067M
Pin
No.
Symbol
Typical
voltage (V)
Equivalent circuit
7
7
OSC1
Description
8
3.7
26 RFVCC
700
700
3k
Oscillator.
3k
8
OSC2
3.7
23 RFGND
9
DGND
0
PLL circuit GND.
26 RFVCC
330
330
10
10
MIXOUT
Mixer output.
Output impedance is 330 Ω.
4.0
23 RFGND
11
DVCC
5
PLL circuit power supply.
21
12
LIMIN
IFVCC
2.4
12
330
Limiter input.
Input impedance is 330 Ω.
13
10k
13
BYP
10k
2.4
22
IFGND
14
GND
0
GND.
21 IFVCC
15
LIMOUT
3.1
15
22 IFGND
—4—
Limiter output.
CXA3067M
Pin
No.
Symbol
Typical
voltage (V)
Equivalent circuit
Description
21 IFVCC
32k
16
16
DETIN
Detector input.
Connect to a discriminator.
5.0
22 IFGND
21
IFVCC
12p
12p
18
17
LP1
4.2
18
LP2
4.2
17
The capacitor is connected
between pins 17 and 18 for
the filter.
22
4.1
(Hi)
19
IFGND
21 IFVCC
50
19
POUT
0.22
(Low)
22 IFGND
FSK data output.
4.1
(Hi)
20
21 IFVCC
50
Pins 19 and 20 are each
other reversal condition.
20
NOUT
0.22
(Low)
21
IFVCC
5.0
22
IFGND
0
23
RFGND
0
22 IFGND
Power supply for limiter, detector,
data shaper circuit.
GND for limiter, detector,
data shaper circuit.
GND for RFamp, Mixer,
oscillator circuit.
—5—
CXA3067M
Pin
No.
Symbol
Typical
voltage (V)
24
RFIN
1.9
Equivalent circuit
Description
26
RFamp input.
RFVCC
27
24
25
RFEM
1.1
MIX
5k
25
Gain adjustment.
Normally, by-pass capacitor is
connected at pin 25 to GND.
233
23
27
MIXIN
5.0
26
RFVCC
5.0
RFGND
11 DVCC
28
REFSW
0.7
(OPEN)
28
9
DGND
11 DVCC
20k
29
FSET3
2.5
(OPEN)
29
20k
9 DGND
11 DVCC
20k
30
FSET2
2.5
(OPEN)
30
20k
9 DGND
—6—
RFamp output and mixer input.
Power supply for RFamp, mixer,
oscillator circuit.
Reference frequency selection.
Decoupling capacitor is
connected at pin 28 to GND
when reference frequency is
7.15909 MHz or 14.31818 MHz
and pin 28 is connected to GND
directly when reference
frequency is 7.15625 MHz or
14.3125 MHz.
The pin of channel selection.
The condition of pin 29 has
3 states.
Connect to 5 V source for “Hi”
selection and connect to GND for
“Low” selection and leave open.
The pin of channel selection.
The condition of pin 30 has
3 states.
Connect to 5 V source for “Hi”
selection and connect to GND for
“Low” selection and leave open.
CXA3067M
Electrical Characteristics
See Electrical Characteristics Test Circuit (VCC=5.0 V, Ta=+25 °C)
Item
RFVCC
Current consumption
IFVCC
Current consumption
DVCC
Current consumption
Circuit
Symbol
Pin No.
RFICC
26, 27
1
IFICC
21
1
DICC
11
1
Input sensitivity 1
Vi1
2
Input sensitivity 2
Vi2
2
Input level
Vil
2
Local OSC leakage
from RF input 1
Local OSC leakage
from RF input 2
LOleak1
24
2
IFVCC
V2=5 V
DVCC
V4=1 V
V3=5 V
fMOD=10 kHz, fDEV=±75 kHz
Jitter is 1 % for fMOD
50 Ω Termination
RF=53.35 M to 169.5 MHz
fMOD=10 kHz, fDEV=±75 kHz
Jitter is 1 % for fMOD
50 Ω Termination
RF=221.95 M to 302 MHz
fMOD=10 kHz, fDEV=±75 kHz
Jitter is 1 % for fMOD
50 Ω Termination
RF=53.35 M to 302 MHz
Measurement on RFIN pin
Typ.
Max.
Unit
14
24
34
mA
3
6.7
10
mA
3.5
7
10
mA
–32
dBmV
–25
dBmV
SW1 : ON
+10
dBmV
–10
dBmV
+5
dBmV
Measurement on RFIN pin
LOleak2
24
2
SW1 : ON
RF=221.95 M to 302 MHz
4.8
7
mA
RF=53.35 M to 169.5 MHz
24
30
34
dB
3
RF=221.95 M to 229.8 MHz
22
25
28
dB
3
RF=302 MHz
16
19
22
dB
1
Grf1
24→27
3
RFamp voltage gain 2
Grf2
24→27
RFamp voltage gain 3
Grf3
24→27
RFamp input resistance
rπ (rf)
24
RFamp input capacitance
Cπ (rf)
24
Mixer input resistance
rπ (mix)
Mixer input capacitance
Cπ (mix)
Mixer voltage gain
Gmix
RFamp voltage gain 1
NF
rfmix
0 dBmV=1 mV, 0 dBµV=1 µV
RFVCC
3
27
Irf
Note)
RFVCC
V1=5 V
Min.
RF=53.35 M to 169.5 MHz
RFamp bias current
RFamp+Mixer noise figure
Conditions
No.
V1=5 V
I=4.8 mA, RF=100 MHz
670
Ω
Load Resistance=510 Ω
4.7
pF
27
RF=100 MHz
1.7
kΩ
27
RF=100 MHz
5.7
pF
Load Resistance=510 Ω
l=4.8 mA, RF=100 MHz
27→10
4
24→10
5
RF=108.5 MHz→
9
IF=10.7 MHz
RF=108.5 MHz→
IF=10.7 MHz
∗1
13
7
∗1) Noise figure is uncorrected for image.
0 dBmV=60 dBµV
0 dBm=47 dBmV
—7—
17
dB
dB
CXA3067M
Item
Circuit
Symbol
Pin No.
Mixer output resistance
rL (mix)
10
Limiter input resistance
rπ (lim)
12
Limiter voltage gain
Glim
15
6
19, 20
2
FSK Data
output voltage “H”
FSK Data
output voltage “L”
Conditions
Min.
Typ.
Max.
Unit
IF=10.7 MHz
222
332
442
Ω
IF=10.7 MHz
222
332
442
Ω
No.
IF=10.7 MHz
70
dB
4.1
V
Load Capacitance=2 pF
OUTH
Load Resistance=10 kΩ,
3.8
fMOD=10 kHz, fDEV=±75 kHz
Load Capacitance=2 pF
OUTL
19, 20
2
Load Resistance=10 kΩ,
0.22
0.6
V
12
30
nsec
12
30
nsec
315
MHz
fMOD=10 kHz, fDEV=±75 kHz
Load Capacitance=2 pF
FSK Data output rise time
Tr
19, 20
2
Load Resistance=10 kΩ,
fMOD=10 kHz, fDEV=±75 kHz
Road Capacitance=2 pF
FSK Data output fall time
Tf
19, 20
2
Road Resistance=10 kΩ,
fMOD=10 kHz, fDEV=±75 kHz
Oscillation frequency
OSC
VT output voltage range
VT
7, 8
40
6
0.3
2.5
VCC
V
±25
±50
±75
µA
Source current→ SW2 : OFF
Charge pump current
Icp
5
7
SW3 : OFF
Sink current → SW2 : ON
SW3 : ON
REFCLOCK input level 1
CLK 1
1
Sin wave input
0.3
0.4
3.0
Vp-p
REFCLOCK input level 2
CLK 2
1
Square wave input
0.3
0.4
3.0
Vp-p
REFOSC loop gain
Gref
FSET1/2/3 “Hi” level
input voltage
FSET1/2/3 “Low” level
input voltage
FSET1/2/3 “Hi” level
input current
FSET1/2/3 “Low” level
input current
RDSW “Low” level
input voltage
RDSW “Low” level
input current
REFSW “Low” level
input voltage
1, 2
3
30
Vin2=14 MHz
dB
FSETVH 3, 29, 30
1
3.8
VCC
V
FSETVL 3, 29, 30
1
0
0.4
V
FSETIH
3, 29, 30
1
FSET “Hi”=V5=5 V
120
250
380
µA
FSETIL
3, 29, 30
1
FSET “Low”=V5=0 V
–380
–250
–120
µA
RDVL
4
1
0.4
V
RDIL
4
1
–43
µA
REFVL
28
1
0.4
V
0
RDSW “L”=V6=0 V
–122
0
—8—
–83
CXA3067M
Electrical Characteristics Test Circuit
V1
5V
V2
5V
A
A
V5
19
17
16
RFGND
IFGND
OSC2
DGND
MIXOUT
DVCC
LIMIN
BYP
GND
LIMOUT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LF1
NOUT
LF2
RFIN
OSC1
1
IFVCC
RFEM
VT
18
DETIN
20
RFVCC
21
CPLF
22
MIXIN
23
RDSW
24
REFSW
25
FSET1
26
FSET3
27
XTAL
28
FSET2
29
REFIN
30
A
POUT
A
V4
1V
A
V6
A
V3
5V
Measurement : Current consumption
Measurement circuit 1
Spectrum
analyzer
4.7µ
10k
10n
DVCC
LIMIN
BYP
GND
LIMOUT
7
8
9
10
11
12
13
14
15
POUT
LF1
56p
1T362
51k
5.6µ
10n
51p
10n
51
DETIN
MIXOUT
6
LF2
IFGND
DGND
5
NOUT
RFGND
OSC2
4
IFVCC
RFIN
OSC1
3
51p
2
SELECTION
330
16
RFEM
17
VT
18
RFVCC
19
CPLF
20
MIXIN
21
RDSW
22
REFSW
23
FSET1
24
FSET3
25
XTAL
26
FSET2
27
REFIN
28
1
10n
10n
29
680p
2p
SELECTION
30
POS
NEG
10n
10k
1n
10n
51
10n
SW1
Passive
probe
10.8P
10M Oscilloscope
10 : 1
2p
Vin
5V
51k
fref
Measurement : Input sensitivity, local osc leakage,
FSK DATA output voltage,
Measurement circuit 2
—9—
rise time, fall time
CXA3067M
4.7µ
5V
GV=Vout1/Vin1 (RFamp voltage gain)
GV=Vout2/Vin2 (REFOSC loop gain)
1n
10n
51
10n
Vin1
Vout1
LIMIN
BYP
GND
LIMOUT
5
6
7
8
9
10
11
12
13
14
15
51
10n
LF1
NOUT
5V
Vout2
DETIN
DVCC
4
LF2
MIXOUT
3
POUT
IFGND
DGND
2
IFVCC
RFGND
1
10n
OSC2
16
RFIN
17
OSC1
18
RFEM
19
VT
20
RFVCC
21
CPLF
22
MIXIN
23
RDSW
24
REFSW
25
FSET1
26
FSET3
27
XTAL
28
FSET2
29
REFIN
30
Vin2
Measurement : RFamp voltage gain
: REFOSC loop gain
Measurement circuit 3
Number of
L2
0.5
3.8 φ
6.5 T
GV=Vout2/Vout1
Vin
1n
10n
20
17
16
DVCC
LIMIN
BYP
GND
LIMOUT
5
6
7
8
9
10
11
12
13
14
15
10n
51p
10n
100p
1T362
51k
3.3n
10n
Vout2
330
51k
fref
27k 30n
DETIN
MIXOUT
4
LF2
IFGND
DGND
3
POUT
RFGND
OSC2
2
IFVCC
RFIN
OSC1
1
51p
RFEM
VT
18
RFVCC
19
CPLF
21
MIXIN
22
RDSW
23
REFSW
24
FSET1
25
FSET3
26
XTAL
27
FSET2
28
10n
REFIN
29
51
10n
30
120p
510
Vout1
LF1
1.5 T
NOUT
3φ
51
0.5
10n
L1
10n
5V
windings
4.7µ
Coil
L1
Wire
diameter diameter
L2
Measurement : Mixer voltage gain
Measurement circuit 4
—10—
CXA3067M
Coil
Number of
windings
0.5
3φ
1.5 T
L2
0.5
3.8 φ
6.5 T
Noise Figure meter
5V
4.7µ
L1
Noise Source
10n
20
19
17
16
MIXOUT
DVCC
LIMIN
BYP
GND
LIMOUT
5
6
7
8
9
10
11
12
13
14
15
1T362
51k
51
10n
110p
51k
fref
LF2
10n
10n
51p
10n
100p
3.3n
DETIN
IFGND
DGND
4
POUT
RFGND
OSC2
3
IFVCC
RFIN
OSC1
2
51p
RFEM
VT
1
10n
RFVCC
18
LF1
21
CPLF
22
MIXIN
23
RDSW
24
REFSW
25
FSET1
26
FSET3
27
XTAL
28
FSET2
29
REFIN
30
NOUT
120p
1n
10n
51
10n
10n
510
L1
40p
2.2µ
10n
L2
27k 30n
Measurement : RFamp +Mixer NF
Measurement circuit 5
5V
10n
10n
4.7µ
GV=Vout/Vin
10n
19
17
RFGND
IFGND
OSC2
DGND
MIXOUT
DVCC
LIMIN
BYP
GND
LIMOUT
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LF2
10n
10n
330
DETIN
RFIN
OSC1
1
POUT
RFEM
VT
16
RFVCC
18
LF1
20
NOUT
21
CPLF
22
MIXIN
23
RDSW
24
REFSW
25
FSET1
26
FSET3
27
XTAL
28
FSET2
29
REFIN
30
IFVCC
10n
Vout
51
Wire
diameter diameter
Vin
Measurement : Limiter voltage gain
Measurement circuit 6
—11—
CXA3067M
4.7µ
BYP
GND
LIMOUT
4
5
6
7
8
9
10
11
12
13
14
15
10n
1T362
A
DETIN
10n
51p
100P
V4
4V
LF1
LIMIN
3
POUT
DVCC
2
NOUT
MIXOUT
1
51p
IFGND
16
DGND
17
RFGND
LF2
18
OSC2
19
RFIN
20
OSC1
IFVCC
21
VT
22
RFVCC
23
CPLF
24
MIXIN
25
RDSW
26
REFSW
27
FSET1
28
FSET3
29
51k
SW2
30
RFEM
1n
10n
10n
6.5 T
XTAL
3.8 φ
FSET2
0.5
V1
5V
windings
REFIN
L2
Number of
10n
Coil
51
Wire
diameter diameter
fref
14MHz
51k
V5
2.5V
V6
0V
L2
SW3
V7
10V
Measurement : Charge pump current
Measurement circuit 7
—12—
CXA3067M
Function Explanation
The CXA3067M is an integrated circuit designed for CATV wide band FSK receiver. This monolithic IC is
composed of local oscillator, double balanced mixer, limiter, FM detector, data shaper and PLL circuit in a
single chip.
The function of each other section is described below.
1. RFamp circuit
This circuit amplifies RF signal, and RF signal is input to pin 24 (RFIN).
Since pin 27 is an open collector, connect power supply through a coil which composes tune circuit or a
choke coil or a resistor.
RF signal is selected a desired frequency by this tune circuit.
The desired frequency is input to mixer circuit through coupling capacitor.
2. Mixer circuit
This is a double-balanced mixer having small leakage of local signal.
The RF signal is converted to IF signal by the signal supplied from oscillator.
The output impedance is approximately 330 Ω.
Normally, connect a ceramic filter to 10 pin (MIXOUT).
3. Local oscillator circuit
The balanced oscillator circuit with pins 7 and 8 (OSC1, OSC2).
Connect an LC resonance circuit comprising a varicap diode to pins 7 and 8.
4. PLL circuit
The PLL circuit fixes the local oscillator frequency to desired frequency.
It consists of the main divider, reference divider, phase comparator, charge pump, reference oscillator.
As stated in the accompanying document, desired frequency (channel) can be selected through the
combination of the conditions of pins 1, 29 and 30 (FSET 1; 2; 3).
As stated in the accompanying document, reference frequency can be selected through the combination
the conditions of pin 3 (RDSW) and pin 28 (REFSW).
5. Limiter circuit
This circuit amplifies the mixer IF output through ceramic filter.
For quadrature FM detection, this circuit amplifies IF signal by necessary level.
The input impedance is approximately 330 Ω.
6. Detector circuit
For quadrature FM detection, the phase of limiter output (pin 15) is shifted 90° by discriminator as the
output is input to pin 16.
7. Data shaper
This circuit output performs the waveform shaping of the demodulated FSK signal and outputs the resulting
signal as a rectangular wave.
—13—
CXA3067M
Description of PLL Block
1. The followings “channel No.” can be selected through the combination of the conditions of pins 1, 29 and 30
(FSET 1; 2; 3).
FSET conditions have 3 states (OPEN, Hi, Low).
Channel Selection
Channel No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Local
OSC frequency
[MHz]
42.65
83.70
98.20
100.00
108.20
117.20
117.80
119.20
133.40
139.20
168.70
180.20
211.25
219.10
312.70
Receiving
frequency
[MHz]
53.55
73.00
87.50
89.30
97.50
106.50
128.50
108.50
122.70
128.50
158.00
169.50
221.95
229.80
302.00
Note) OPEN : No connect
L : Connect to GND
H : Connect to VCC
—14—
FSET 1
FSET 2
FSET 3
OPEN
L
H
OPEN
L
H
OPEN
L
H
OPEN
L
H
OPEN
L
H
OPEN
OPEN
OPEN
L
L
L
H
H
H
OPEN
OPEN
OPEN
L
L
L
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
L
L
L
L
L
L
CXA3067M
2. The followings Reference frequency can be selected through the combination the conditions of pin 3
(RDSW) and pin 28 (REFSW).
When the pin 28 is connected to GND directly, the pin 28 is state of DCGND.
When the pin 28 is connected to GND through decoupling capacitor, the pin 28 is state of ACGND.
Reference Frequency selection
f (ref)
7.15625 MHz
7.15909 MHz
14.3125 MHz
14.31818 MHz
RDSW
OPEN
OPEN
GND
GND
REFSW
DCGND
ACGND
DCGND
ACGND
∗1
∗2
∗1
∗2
Note ∗1) Connect to GND directly.
30
29
28
27
REFSW
Note ∗2) Connect to GND through decoupling capacitor
30
29
28
REFSW
—15—
27
CXA3067M
3. The comparison frequency is 25.021853 kHz at reference frequency 7.15625 MHz/14.3125 MHz, and
25.031783 kHz at reference frequency 7.15909 MHz/14.31818 MHz.
The frequency division ratio of the reference divider is 286.
The frequency division ratio of the scaler is 1 or 2;
When the reference frequency is 7.15625 MHz/7.15909 MHz, the frequency division ratio of the scaler is 1.
When the reference frequency is 14.3125 MHz/14.31818 MHz, the frequency division ratio of the scaler is 2.
Reference frequency=7.15625 MHz
The comparison frequency=7.15625/286=25.021853 kHz
Ch
fOSC [MHz]
Divider
512
256
128
64
32
16
8
4
2
1
1
42.65
1705
8192 4096 2048 1024
0
0
0
1
1
0
1
0
1
0
1
0
0
1
2
83.7
3345
0
0
1
1
0
1
0
0
0
1
0
0
0
1
3
98.2
3925
0
0
1
1
1
1
0
1
0
1
0
1
0
1
4
100
3997
0
0
1
1
1
1
1
0
0
1
1
1
0
1
5
108.2
4324
0
1
0
0
0
0
1
1
1
0
0
1
0
0
6
117.2
4684
0
1
0
0
1
0
0
1
0
0
1
1
0
0
7
117.8
4708
0
1
0
0
1
0
0
1
1
0
0
1
0
0
8
119.2
4764
0
1
0
0
1
0
1
0
0
1
1
1
0
0
9
133.4
5331
0
1
0
1
0
0
1
1
0
1
0
0
1
1
10
139.2
5563
0
1
0
1
0
1
1
0
1
1
1
0
1
1
11
168.7
6742
0
1
1
0
1
0
0
1
0
1
0
1
1
0
12
180.2
7202
0
1
1
1
0
0
0
0
1
0
0
0
1
0
13
211.25
8443
1
0
0
0
0
0
1
1
1
1
1
0
1
1
14
219.1
8756
1
0
0
0
1
0
0
0
1
1
0
1
0
0
15
312.7
12497
1
1
0
0
0
0
1
1
0
1
0
0
0
1
Reference frequency=7.15909 MHz
The comparison frequency=7.15909/286=25.031783 kHz
Ch
fOSC [MHz]
Divider
8192 4096 2048 1024
512
256
128
64
32
16
8
4
2
1
1
42.65
1704
0
0
0
2
83.7
3344
0
0
1
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
3
98.2
3923
0
0
0
1
1
1
1
0
1
0
1
0
0
1
4
100
3995
0
1
0
1
1
1
1
1
0
0
1
1
0
1
1
5
108.2
4323
6
117.2
4682
0
1
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
1
7
117.8
0
4706
0
1
0
0
1
0
0
1
1
0
0
0
1
8
0
119.2
4762
0
1
0
0
1
0
1
0
0
1
1
0
1
0
9
133.4
5329
0
1
0
1
0
0
1
1
0
1
0
0
0
1
10
139.2
5561
0
1
0
1
0
1
1
0
1
1
1
0
0
1
11
168.7
6739
0
1
1
0
1
0
0
1
0
1
0
0
1
1
12
180.2
7199
0
1
1
1
0
0
0
0
0
1
1
1
1
1
13
211.25
8439
1
0
0
0
0
0
1
1
1
1
0
1
1
1
14
219.1
8753
1
0
0
0
1
0
0
0
1
1
0
0
0
1
15
312.7
12492
1
1
0
0
0
0
1
1
0
0
1
1
0
0
—16—
CXA3067M
Notes on Application
Take care of the followings because the CXA3067M has limiter voltage gain of approximately 67 dB and uses
high frequency.
1) Separate the input pattern from the output pattern as far as possible and makes wiring short.
2) Ground the decoupling capacitor as close to pin 13 as possible.
Take care of the followings in order to reduce the jitter.
1) Insert the capacitor as close to pin 17 and 18 as possible.
2) Ground the by-pass capacitor as close to IFVCC to supply pin 16 as possible.
Take care of the following, for the purpose of the isolation of local oscillator resonance circuit and X’tal (RFF
CLOCK).
1) Separate the patterns connected pin 1 and pin 2 from the local oscillator resonance circuit.
Take care of the following, in order to reduce the phase noise.
1) Connect the loop filter as close to pins 5 and 6 as possible.
Take care of the following, in order to prevent the parasitic oscillation.
1) Connect the local oscillator resonance circuit as close to pins 7 and 8 as possible.
And compact the local oscillator resonance circuit.
The tuning voltage at the local oscillator resonance circuit.
The output voltage at pin 6 is 0.3 V to VCC.
When the oscillation frequency is the desired frequency, please the output voltage at pin 6 should be been 2.5 V.
Please decide the component value of loop filter by each system.
11
DVCC
10k
100
5
100
6
9
DGND
—17—
ACGND
DCGND
ACGND
OPEN
OPEN
GND
GND
7.15909 MHz
14.3125 MHz
14.31818 MHz
14MHz
X’tal
RF INPUT
1
4
5
6
9
8
LOCAL OSCILLATOR
51k
7
OSC2
10n
11
10.7MHz
CERAFIL
10
12
15
56p
5.6µ
Please refer to another sheets with following circuits.
1) Tuned circuit of RFamp
2) Local osc resonance circuit
3) Loop filter
14
13
330
FIXED DISCRIMINATOR
10.7MHz
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
LOOP FILTER
SELECTION
3
2
51p
CXA3067M
16
17
18
19
20
21
22
23
24
25
26
27
28
29
REFIN
FSET2
XTAL
FSET3
FSET1
REFSW
10n
RDSW
MIXIN
CPLF
RFVCC
VT
RFEM
51k
DGND
1T362
OSC1
RFIN
51
RFGND
30
680p
FSK DATA OUT FSK DATA OUT
10n
IFGND
2p
MIXOUT
IFVCC
SELECTION
10n
4.7µ
1n
VCC (+5V)
NEG
NOUT
DVCC
POUT
LIMIN
LF2
REF CLOCK INPUT
10n
TUNE CIRCUIT OF RFAMP
REFSW
DCGND
RDSW
15p
fref
51
7.15625 MHz
10n
51p
POS
10k
2p
10k
10n
LF1
BYP
—18—
GND
DETIN
LIMOUT
Application
10n
CXA3067M
15p
CXA3067M
The component value of the tune circuit, local oscillator resonance circuit and loop filter.
Channel
No.
Tune circuit
of RFamp
Local oscillator
resonance circuit
Wire
diameter
1
Number of
windings
Coil
diameter
7
0.5
2.5T
3φ
51p
8
3.3n
51p
1T362
330p
510
1n
0.5
20.5T
5φ
82p
2
0.5
2.5T
3φ
3.3n
30n
27k
3.3n
30n
27k
3.3n
100p
100p
0.5
1.5T
3φ
27k
510
0.5 6.5T 3.8φ
8
30n
150p
100p
0.5
1.5T
3φ
3.3n
510
0.5 6.5T 3.8φ
7
27k
82p
100p
0.5
1.5T
3φ
30n
510
0.5 8.5T 3.8φ
6
3.3n
120p
100p
0.5
2.5T
3φ
27k
510
0.5 8.5T 3.8φ
5
30n
120p
100p
0.5
2.5T
3φ
3.3n
510
0.5 8.5T 3.8φ
4
24k
180p
100p
0.5
2.5T
3φ
39n
510
0.5 11.5T 3.8φ
3
Loop filter
30n
27k
3.3n
120p
510
0.5 6.5T 3.8φ
—19—
30n
27k
CXA3067M
Channel
No.
Tune circuit
of RFamp
Local oscillator
resonance circuit
100p
9
0.5
1.5T
3φ
100p
100p
0.5
1.5T
3φ
30n
27k
3.3n
62p
62p
0.5
1.5T
3φ
3.3n
510
0.5 3.5T 3.8φ
12
27k
100p
100p
0.5
1.5T
3φ
30n
510
0.5 5.5T 3.8φ
11
3.3n
510
0.5 5.5T 3.8φ
10
Loop filter
30n
27k
3.3n
56p
510
0.5 3.5T 3.8φ
—20—
30n
30k
CXA3067M
Supply voltage vs. Current consumtion
Frequency response RF amp voltage gain
30
32
28
RFamp gain (dB)
Current consumption (mA)
30
RF BLOCK
25
20
15
10
26
24
22
PLL BLOCK
20
5
IF BLOCK
18
10
0
4.6
4.7
4.8
4.9
5
5.1
Supply voltage (V)
5.2
5.3
100
Reception Frequency (MHz)
5.4
Frequency response limiter voltage gain
Local oscillation leakage at RFIN pin
–50
80
–55
Leakage level (dBm)
90
70
60
50
40
–60
–65
–70
–75
30
–80
20
1
10
Intermediate Frequency (MHz)
100
1
100
Local oscillation frequency (MHz)
S curve response
4.32
4.31
LP1 Output Level (V)
Limiter gain (dB)
300
4.3
4.29
4.28
4.27
4.26
10.6
10.65
10.7
10.75
Intermediate Frequency (MHz)
—21—
10.8
1000
CXA3067M
RFIN Input Impedance (Resistance, Capacitance)
Reception frequency
50 MHz
100 MHz
200 MHz
Resistance
890 Ω
670 Ω
510 Ω
Capacitance
5.2 pF
4.7 pF
4.4 pF
j50
j25
j100
0
50MHz
100MHz
200MHz
–j100
–j25
–j50
SMA
Connector
PCB
1nF
VCC
5V
1nF
1nF
S11
Calibration plane
510Ω
27
26
25
24
IC
CXA3067M
—22—
CXA3067M
MIXIN Input Impedance (Resistance, Capacitance)
Reception frequency
50 MHz
100 MHz
200 MHz
Resistance
2.1 kΩ
1.7 kΩ
900 Ω
Capacitance
5.7 pF
5.7 pF
6.1 pF
j50
j25
j100
0
50MHz
100MHz
200MHz
–j100
–j25
–j50
SMA
Connector
PCB
1nF
VCC
11kΩ
60V
27
26
S11
Calibration plane
25
24
RFVCC
IC
CXA3067M
—23—
CXA3067M
Unit : mm
30PIN SOP(PLASTIC)
+ 0.4
2.3 – 0.15
+ 0.4
18.8 – 0.1
0.1
30
+ 0.2
0.1 – 0.05
(9.3)
A
0.5 ± 0.2
10.3 ± 0.4
16
+ 0.3
7.6 – 0.1
Package Outline
15
1
0.45 ± 0.1
1.27
0.2
M
+ 0.1
0.2 – 0.05
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
SOP-30P-L03
LEAD TREATMENT
EIAJ CODE
SOP030-P-0375
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.7g
JEDEC CODE
—24—
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