AD ADIS16365/PCBZ Tri-axis inertial sensor Datasheet

Tri-Axis Inertial Sensor
ADIS16365
Preliminary Technical Data
Tri-axis gyroscope with digital range scaling
±75°/sec, ±150°/sec, ±300°/sec settings
14-bit resolution
Tri-axis accelerometer
±17 g measurement range
14-bit resolution
350 Hz bandwidth
Factory calibrated sensitivity, bias, and alignment
Calibration temperature range: −40°C to +85°C
External clock input for sample synchronization
Digitally controlled bias calibration
Digitally controlled sample rate
Digitally controlled filtering
Programmable condition monitoring
Auxiliary digital input/output
Digitally activated self-test
Programmable power management
Embedded temperature sensor
SPI-compatible serial interface
Auxiliary 12-bit ADC input and DAC output
Single-supply operation: 4.75 V to 5.25 V
2000 g shock survivability
Operating temperature range: −40°C to +105°C
FUNCTIONAL BLOCK DIAGRAM
AUX_ADC
AUX_DAC
ADIS16365
TEMPERATURE
SENSORS
ALARMS
TRI-AXIS MEMS
ANGULAR
RATE SENSOR
CS
SIGNAL
CONDITIONING
AND
CONVERSION
CALIBRATION
AND
DIGITAL
PROCESSING
SCLK
SPI
PORT
DIN
TRI-AXIS MEMS
ACCELERATION
SENSOR
DIGITAL
CONTROL
DOUT
POWER
MANAGEMENT
VCC
GND
SELF-TEST
RST DIO1 DIO2 DIO3 DIO4/
CLKIN
07570-001
FEATURES
Figure 1.
APPLICATIONS
Guidance and control
Platform control and stabilization
Motion control and analysis
Inertial measurement units
General navigation
Image stabilization
Robotics
GENERAL DESCRIPTION
The ADIS16365 iSensor® is a complete triple axis gyroscope and
triple axis accelerometer inertial sensing system. This sensor
combines the Analog Devices, Inc., iMEMS® and mixed signal
processing technology to produce a highly integrated solution
that provides calibrated, digital inertial sensing. An SPI
interface and simple output register structure allow for easy
access to data and configuration controls.
The SPI port provides access to the following embedded sensors:
X-, Y-, and Z-axis angular rates; X-, Y-, and Z-axis linear acceleration; internal temperature; power supply; and auxiliary analog
input. The inertial sensors are precision-aligned across axes and
are calibrated for offset and sensitivity over the industrial
temperature range of −40 to +85°C. An embedded controller
dynamically compensates for all major influences on the
sensors, thus maintaining highly accurate sensor outputs
without further testing, circuitry, or user intervention.
The following programmable features simplify system integration: in-system autobias calibration, digital filtering and sample
rate, self-test, power management, condition monitoring, and
auxiliary digital input/output.
This compact module is approximately 23 mm × 23 mm ×
23 mm and provides a convenient flex-based connector system.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADIS16365
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Initial Hook-Up and Configuration ........................................ 10
Applications ....................................................................................... 1
Data Collection ........................................................................... 10
Functional Block Diagram .............................................................. 1
Device Configuration ................................................................ 11
General Description ......................................................................... 1
Burst Mode Data Collection ..................................................... 11
Specifications..................................................................................... 3
Output Data Registers ............................................................... 12
Timing Specifications .................................................................. 6
Calibration................................................................................... 12
Timing Diagrams.......................................................................... 6
Operation Control Registers ..................................................... 13
Absolute Maximum Ratings............................................................ 7
Input/Output Functions ............................................................ 14
ESD Caution .................................................................................. 7
Diagnostics .................................................................................. 15
Pin Configuration and Function Descriptions ............................. 8
Outline Dimensions ....................................................................... 17
Typical Performance Characteristics ............................................. 9
Ordering Guide .......................................................................... 17
Basic Operation............................................................................... 10
Physical Installation ................................................................... 10
Rev. PrA | Page 2 of 20
Preliminary Technical Data
ADIS16365
SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, angular rate = 0°/sec, dynamic range = 300°/sec, ±1 g, unless otherwise noted.
Table 1.
Parameter
GYROSCOPE SENSITIVITY
Initial Sensitivity
Temperature Coefficient
Gyroscope Axis Nonorthogonality
Gyroscope Axis Misalignment
Nonlinearity
GYROSCOPE BIAS
In-Run Bias Stability
Angular Random Walk
Temperature Coefficient
Linear Acceleration Effect
Voltage Sensitivity
GYROSCOPE NOISE PERFORMANCE
Output Noise
Rate Noise Density
GYROSCOPE FREQUENCY RESPONSE
3 dB Bandwidth
Sensor Resonant Frequency
GYROSCOPE SELF-TEST STATE
Change in output bias
Internal Self-Test Cycle Time
ACCELEROMETER SENSITIVITY
Dynamic Range
Initial Sensitivity
Temperature Coefficient
Axis Nonorthogonality
Axis Misalignment
Nonlinearity
ACCELEROMETER BIAS
In-Run Bias Stability
Velocity Random Walk
Temperature Coefficient
ACCELEROMETER NOISE PERFORMANCE
Output Noise
Noise Density
ACCELEROMETER FREQUENCY RESPONSE
3 dB Bandwidth
Sensor Resonant Frequency
ACCELEROMETER SELF-TEST STATE
Output Change When Active
TEMPERATURE SENSOR
Scale Factor
Conditions
Each axis
25°C, dynamic range = ±300°/sec
25°C, dynamic range = ±150°/sec
25°C, dynamic range = ±75°/sec
Min
Typ
Max
Unit
0.0405
0.05
0.025
0.0125
40
TBD
±0.5
0.1
0.0505
°/sec/LSB
°/sec/LSB
°/sec/LSB
ppm/°C
Degree
Degree
% of FS
25°C, difference from 90° ideal
25°C, relative to base plate and guide pins
Best fit straight line
25°C, 1 σ
25°C
Any axis, 1 σ (MSC_CTRL bit [7] = 1)
VCC = 4.75 V to 5.25 V
0.007
2.4
0.1
0.05
0.25
°/sec
°/√hr
°/sec/°C
°/sec/g
°/sec/V
25°C, ±300°/sec range, 1-tap filter setting
25°C, ±150°/sec range, 4-tap filter setting
25°C, ±75°/sec range, 16-tap filter setting
25°C, f = 25 Hz, ±300°/sec, no filtering
TBD
TBD
TBD
TBD
°/sec rms
°/sec rms
°/sec rms
°/sec/√Hz rms
350
14
Hz
kHz
±300°/sec range setting
±833
±1500
25
±2167
LSB
ms
Each axis
25°C
TBD
25°C, difference from 90° ideal
25°C, relative to base plate and guide pins
Best fit straight line
±17
0.33
40
±0.25
±0.5
±0.2
TBD
g
mg/LSB
ppm/°C
Degree
Degree
% of FS
25°C, 1 σ
25°C, 1 σ
TBD
TBD
TBD
mg
m/sec/√hr
mg/°C
25°C, no filtering
25°C, no filtering
TBD
TBD
mg rms
mg/√Hz rms
TBD
TBD
Hz
kHz
TBD
LSB
6.88
LSB/°C
+25°C output = 0x0000
Rev. PrA | Page 3 of 20
ADIS16365
Parameter
ADC INPUT
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Range
Input Capacitance
DAC OUTPUT
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error
Output Range
Output Impedance
Output Settling Time
LOGIC INPUTS 1
Input High Voltage, VINH
Input Low Voltage, VINL
Logic 1 Input Current, IINH
Logic 0 Input Current, IINL
All Except RST
RST
Input Capacitance, CIN
DIGITAL OUTPUTS1
Output High Voltage, VOH
Output Low Voltage, VOL
SLEEP TIMER
Timeout Period 2
FLASH MEMORY
Endurance 3
Data Retention 4
START-UP TIME 5
Power-On
Reset Recovery
Sleep Mode Recovery
CONVERSION RATE
Sample Rate Settings
Clock Accuracy
SYNC Input Clock
Preliminary Technical Data
Conditions
Min
Typ
Max
12
±2
±1
±4
±2
0
During acquisition
5 kΩ/100 pF to GND
+3.3
20
12
±4
±1
±5
±0.5
For Code 101 to Code 4095
+3.3
2
10
2.0
CS signal to wake up from sleep mode
VIH = 3.3 V
VIL = 0 V
±0.2
−40
−1
10
ISOURCE = 1.6 mA
ISINK = 1.6 mA
0.8
0.55
±10
−60
2.4
0.5
TJ = 85°C
Time until data is available
Fast mode, SMPL_PRD ≤ 0x07
Normal mode, SMPL_PRD ≥ 0x08
Fast mode, SMPL_PRD ≤ 0x07
Normal mode, SMPL_PRD ≥ 0x08
SMPL_PRD = 0x01 to 0xFF
Unit
Bits
LSB
LSB
LSB
LSB
V
pF
Bits
LSB
LSB
mV
%
V
Ω
μs
V
V
V
μA
μA
mA
pF
0.4
V
V
128
Sec
10,000
20
Cycles
Years
TBD
TBD
TBD
TBD
TBD
0.413
ms
ms
ms
ms
ms
819.2
SPS
1.2
kHz
TBD
Rev. PrA | Page 4 of 20
Preliminary Technical Data
Parameter
POWER SUPPLY
Operating Voltage Range, VCC
Power Supply Current
ADIS16365
Conditions
Low power mode at 25°C
Fast mode at 25°C
Sleep mode at 25°C
1
Min
Typ
Max
Unit
4.75
5.0
24
49
500
5.25
V
mA
mA
μA
The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.
Guaranteed by design.
Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
3
Retention lifetime equivalent at junction temperature (TJ) 85°C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature.
5
The times presented in this section do not include the sensor’s transient response time, which is associated with a 50 Hz single-pole system. System accuracy goals
should be given consideration when determining the amount of time it takes to start acquiring accurate readings. These times do not include the time it takes to
arrive at thermal stability, which can also introduce transient errors.
2
3
Rev. PrA | Page 5 of 20
ADIS16365
Preliminary Technical Data
TIMING SPECIFICATIONS
TA = 25°C, VDD = +5 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDF, tDR
tSFS
Fast Mode
(SMPL_PRD < 0x09)
Min 1
Typ
Max
0.01
2.0
9
48.8
100
24.4
48.8
5
12.5
5
12.5
5
Description
Stall period between data
Chip select to clock edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK Rise/Fall times
DOUT rise/fall times
CS high after SCLK edge
Low Power Mode
(SMPL_PRD > 0x0A)
Min1
Typ
Max
0.01
0.3
75
48.8
100
24.4
48.8
5
12.5
5
12.5
5
Burst Mode
Min
Typ Max
0.01
1.0
1/fSCLK
48.8
100
24.4
48.8
5
12.5
5
12.5
5
1
Unit
MHz
μs
ns
ns
ns
ns
ns
ns
ns
1
Guaranteed by design, not tested.
TIMING DIAGRAMS
CS
tCS
tSFS
1
2
3
4
5
6
15
16
SCLK
tDAV
MSB
DB14
DB13
tDSU
DIN
W/R
DB12
DB11
A4
A3
DB10
DB2
DB1
LSB
tDHD
A5
D2
A2
D1
07570-002
DOUT
LSB
Figure 2. SPI Timing and Sequence
tSTALL
DATA FRAME
CS
DATA FRAME
SCLK
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
W/R
A5
A4
A3
DOUT
WRITE = 1
READ = 0
REGISTER ADDRESS
A2
A1
A0
DC7
DC6
DC5
DC4
DC3
DC2
DC1
DC0
DATA FROM PREVIOUS SEQUENCE
07570-003
W/R
DATA FOR WRITE COMMANDS
DON’T CARE FOR READ COMMANDS
Figure 3. DIN Bit Sequence
CS
1
2
3
4
5
11
ZGYRO_OUT
ZTEMP_OUT
12
SCLK
DIN
DOUT
0x3E00
PREVIOUS
DON’T CARE
SUPPLY_OUT
XGYRO_OUT
YGYRO_OUT
Figure 4. Burst Mode Read Sequence
Rev. PrA | Page 6 of 20
AUX_ADC
07570-004
DIN
Preliminary Technical Data
ADIS16365
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Acceleration
Any Axis, Unpowered
Any Axis, Powered
VCC to GND
Digital Input/Output Voltage to GND
Analog Inputs to GND
Operating Temperature Range
Storage Temperature Range
1
Rating
2000 g
2000 g
−0.3 V to +6.0 V
−0.3 V to +5.3 V
−0.3 V to +3.6 V
−40°C to +85°C
−65°C to +125°C1,2
Extended exposure to temperatures outside the specified temperature
range of −40°C to +85°C can adversely affect the accuracy of the factory
calibration. For best accuracy, store the parts within the specified operating
range of −40°C to +85°C.
2
Although the device is capable of withstanding short-term exposure to
150°C, long-term exposure threatens internal mechanical integrity.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Package Characteristics
Package Type
24-Lead Module
ESD CAUTION
Rev. PrA | Page 7 of 20
θJA
39.8°C/W
θJC
14.2°C/W
Device Weight
16 grams
ADIS16365
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DIO3
SCLK
DIN
DIO1
DIO2
VCC
GND
GND
DNC
DNC
AUX_ADC
DNC
1
3
5
7
9
11
13
15
17
19
21
23
2
4
6
8
10
12
14
16
18
20
22
24
DIO4/CLKIN
DOUT
CS
RST
VCC
VCC
GND
DNC
DNC
AUX_DAC
DNC
DNC
TOP VIEW
(Not to Scale)
NOTES
1. CONNECTOR PINS ARE NOT VISIBLE FROM THE TOP VIEW.
2. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT
FOR THE MATING SOCKET CONNECTOR.
3. DNC = DO NOT CONNECT.
07570-005
ADIS16365
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
16, 17, 18, 19, 22, 23, 24
3
4
5
6
7
8
9
10, 11, 12
13, 14, 15
20
21
1
Type 1
I/O
I/O
N/A
I
O
I
I
I/O
I
I/O
S
S
O
I
Mnemonic
DIO3
DIO4/CLKIN
DNC
SCLK
DOUT
DIN
CS
DIO1
RST
DIO2
VCC
GND
AUX_DAC
AUX_ADC
Description
Configurable Digital Input/Output
Configurable Digital Input/Output or Clock Input
Do Not Connect
SPI Serial Clock
SPI Data Output
SPI Data Input
SPI Chip Select
Configurable Digital Input/Output
Reset
Configurable Digital Input/Output
Power Supply
Power Ground
Auxiliary, 12-Bit, DAC Output
Auxiliary, 12-Bit, ADC Input
S = supply, O = output, I = input.
PIN 1
PIN 23
TOP VIEW
Z
X
Y
PIN 24
FLEX
2
TO HOUSING
23
Figure 6. Pin Configuration, Connector Top View
Rev. PrA | Page 8 of 20
1
POINT OF PERCUSSION
(WHEN LINEAR ACCELEROMETER
ORIGIN ALIGNMENT ENABLED)
07570-006
PIN 2
Preliminary Technical Data
ADIS16365
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7.
Figure 10.
Figure 8.
Figure 11.
Figure 9.
Figure 12.
Rev. PrA | Page 9 of 20
ADIS16365
Preliminary Technical Data
BASIC OPERATION
3.3V
5V
MICROCONTROLLER/
DSP/FPGA
ADIS16365
SS
CS
SCLK
SCLK
MOSI
DIN
MISO
DOUT
IRQ
DIO1
VCC
07570-009
The ADIS16365 runs off an internal clock and requires no
external initialization. Once the power supply reaches 4.75 V,
the ADIS16365 executes an internal initialization sequence and
then starts producing data. At this point, the DIO1 will start
pulsing as well, repeating each time new data loads into the
output registers. This data-ready signal serves as an interrupt
service signal, telling the system processor that the device is
awake and producing data.
07570-007
Figure 15. Electrical Hook-Up Diagram
DIO1
Figure 13. Start-Up Sequence
PHYSICAL INSTALLATION
The ADIS16365 provides slots on each side for attachment.
These slots accommodate either 2-56 or 2 mm machine screws.
Attach the body of the ADIS16365 to the proper surface prior to
inserting the electrical connector, which is located at the end of
the flex.
4
BSC
Table 6. Typical Processor SPI Configuration Settings
DRILL AND TAP FOR
2mm MACHINE SCREWS.
2×
Processor Setting
Master
SCLK Rate < 2MHz
(See Table 2)
CPOL = 1
CPHA = 1
MSB-first
16-bit data cycles
ALIGNMENT PINS FOR
SAMTEC CLM-112-02-LM-D-A.
2×
26.700
BSC
All of the output data and configuration options have 16-bit
registers assigned to govern their operation. Each byte has its
own unique 6-bit address, which provides user access using the
serial peripheral interface (SPI). While SPI is a common digital
interface, most digital processor platforms accommodate
several configuration options. The parameters listed in Table 6
are configuration options that SPI-compatible digital processor
platforms offer in configuration registers. This table is a guide
for determining how to configure them for communication
with the ADIS16365.
27.700
BSC
10
FOR 1.5mm
ALIGNMENT PINS.
2×
8.350
Notes
The ADIS16365 operates as a slave.
Derived from a master clock, which is
divided down to meet this requirement.
Clock polarity.
Clock phase.
Bit sequence.
For an 8-bit processor, this requires two
back-to-back 8-bit spi_read commands,
while keeping the chip-select line low.
DATA COLLECTION
0.500 BSC
2×
07570-008
16.810
2×
4
BSC
Figure 14. Typical Hole Pattern for the ADIS16365 Attachment
INITIAL HOOK-UP AND CONFIGURATION
The electrical connection uses a 24-pin header that mates to
either the CLM or MLE family of connectors from Samtec. The
evaluation system for this product uses Samtec part number:
CLM-112-02-LM-D-A. Samtec is the appropriate source for
suggested pad layout geometries for this mating connector.
Although this device runs off a +5 V power supply, the digital
lines are compatible with +3.3 V-digital I/O systems.
The ADIS16365 produces data outputs in 16-bit segments,
based on the previous 16-bit configuration sequence. The bit
assignments for the configuration sequence are in Figure 3. For
a read command, only the first eight bits require definition. The
first two bits are zero, and the next six bits represent the register’s
lower byte, listed in Table 7. When using 8-bit microcontrollers,
use two back-to-back SPI read calls, while keeping the chip
select line low. A typical code example for an 8-bit microcontroller may look like the following:
Chip_Select = 0;
high_byte = spi_read(0x06);
low_byte = spi_read(0x00);
Chip_Select = 1;
delay 0.01ms (stall time)
Rev. PrA | Page 10 of 20
Preliminary Technical Data
ADIS16365
DEVICE CONFIGURATION
BURST MODE DATA COLLECTION
The ADIS16365 SPI provides device configuration control as
well, eight bits at a time. Each function has a configurable
register, which governs its operation, as listed in Table 7. In
Figure 3, the first byte contains the write bit and register
address. For example, the first byte of a write to the SMPL_PRD
is 0x80 (write bit high) plus 0x36 (low-byte address), which is
0xB6. The second byte of the DIN sequence contains the data,
which loads into the specified location. For the lowest sample
rate setting, 0xFF is the code. The entire DIN sequence for
setting the slowest sample rate is 0xB6FF.
Burst mode data collection offers a more process-efficient
method for collecting data from the ADIS16365. In 12 sequential data cycles, separated by only one SCLK time period, all 11output registers clock out on DOUT. In Figure 4, this sequence
starts when the DIN sequence is 0x3E00. After that, the
contents of each output register, comes out of DOUT, starting
with SUPPLY_OUT and ending with AUX_ADC. The
addressing sequence determines the order of the outputs in
burst mode.
Many of the configuration registers have also been assigned
mirror locations in the flash memory, which effectively provides
them with a backup storage function. To assure the backup of
these registers, the COMMAND register provides an initiation
bit for manual flash updates. The ENDURANCE register
provides a running count of these events.
Table 7. User Register Map
Name
ENDURANCE
SUPPLY_OUT
XGYRO_OUT
YGYRO_OUT
ZGYRO_OUT
XACCL_OUT
YACCL_OUT
ZACCL_OUT
XTEMP_OUT
YTEMP_OUT
ZTEMP_OUT
AUX_ADC
R/W
R
R
R
R
R
R
R
R
R
R
R
R
Flash Backup
Yes
No
No
No
No
No
No
No
No
No
No
No
XGYRO_OFF
YGYRO_OFF
ZGYRO_OFF
XACCL_OFF
YACCL_OFF
ZACCL_OFF
ALM_MAG1
ALM_MAG2
ALM_SMPL1
ALM_SMPL2
ALM_CTRL
AUX_DAC
GPIO_CTRL
MSC_CTRL
SMPL_PRD
SENS/AVG
SLP_CNT
STATUS
COMMAND
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
No
N/A
Address
0x00
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
0x10
0x12
0x14
0x16
0x18
0x1A
0x1C
0x1E
0x20
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
0x34
0x36
0x38
0x3A
0x3C
0x3E
Size (Bytes)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Function
Flash memory write count
Power supply measurement
X-axis gyroscope output
Y-axis gyroscope output
Z-axis gyroscope output
X-axis accelerometer output
Y-axis accelerometer output
Z-axis accelerometer output
X-axis gyroscope temperature measurement
Y-axis gyroscope temperature measurement
Z-axis gyroscope temperature measurement
Auxiliary ADC output
Reserved
X-axis gyroscope bias offset factor
Y-axis gyroscope bias offset factor
Z-axis gyroscope bias offset factor
X-axis acceleration bias offset factor
Y-axis acceleration bias offset factor
Z-axis acceleration bias offset factor
Alarm 1 amplitude threshold
Alarm 2 amplitude threshold
Alarm 1 sample size
Alarm 2 sample size
Alarm control
Auxiliary DAC data
Auxiliary digital input/output control
Miscellaneous control
Internal sample period (rate) control
Dynamic range/digital filter control
Sleep mode control
System status
System command
Rev. PrA | Page 11 of 20
Reference
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 8
Table 9
Table 9
Table 9
Table 10
Table 10
Table 10
Table 19
Table 19
Table 20
Table 20
Table 21
Table 16
Table 18
Table 17
Table 13
Table 15
Table 14
Table 22
Table 12
ADIS16365
Preliminary Technical Data
OUTPUT DATA REGISTERS
Automatic Bias Null Calibration
Table 8 provides the data configuration for each output data
register in the ADIS16365. Starting with the MSB of the upper
byte, each output data register has the following bit sequence:
new data (ND) flag, error/alarm (EA) flag, followed by 14 data
bits. The data bits are LSB-justified and, in the case of the 12-bit
data formats, the remaining two bits are not used. The ND flag
indicates that unread data resides in the output data registers.
This flag clears and returns to 0 during an output register read
sequence. It returns to 1 after the next internal sample update
cycle completes. The EA flag indicates an error condition. The
STATUS register contains all of the error flags and provides the
ability to investigate the root cause.
This single-command calibration function is in the
COMMAND register and measures all three-gyroscope output
registers, then loads the three bias correction registers with
values that return their outputs to zero (null). See Table 11 for
the DIN command.
Table 8. Output Data Register Formats
Register
SUPPLY_OUT1
XGYRO_OUT2
YGYRO_OUT2
ZGYRO_OUT2
XACCL_OUT
YACCL_OUT
ZACCL_OUT
XTEMP_OUT3
YTEMP_OUT3
ZTEMP_OUT3
AUX_ADC
Bits
12
14
14
14
14
14
14
12
12
12
12
Format
Binary, +5V = 0x
Twos complement
Twos complement
Twos complement
Twos complement
Twos complement
Twos complement
Binary, 25°C = 0x04FE
Binary, 25°C = 0x04FE
Binary, 25°C = 0x04FE
Binary = 0x04FE
Scale
2.418 mV
0.05°/sec
0.05°/sec
0.05°/sec
3.33 mg
3.33 mg
3.33 mg
0.1453°C
0.1453°C
0.1453°C
0.8059 mV
1
5 V = 2730 LSBs (nominal).
Assumes that the scaling is set to 300°/sec. This factor scales with the range.
3
Typical condition, 25°C = 0 LSB.
2
CALIBRATION
Manual Bias Calibration
Precision Automatic Bias Null Calibration
This single-command calibration function is in the COMMAND
register and incorporates a 30-second average of all three gyroscope output registers, then loads the three bias correction
registers with values that return their outputs to zero (null). For
optimal calibration accuracy, the device should be stable (no
motion) for this entire period. Once it has started, a reset is the
only way to stop it prematurely, if required. See Table 11 for the
DIN command.
Restoring Factory Calibration
This single command is in the COMMAND register and restores
the factory calibration by writing 0x0000 into each bias offset
register listed in Table 9 and Table 10. This command also flushes
all of the data from the digital filter taps. See Table 11 for the
DIN command.
Linear Acceleration Bias Compensation (Gyroscopes)
This function enables compensation for low-frequency
acceleration influences on gyroscope bias behavior, using the
MSC_CTRL register. See Table 11 for the DIN command.
Linear Acceleration Origin Alignment
This function enables origin alignment for the accelerometers
to the point of percussion (see Figure 6), using the MSC_CTRL
register. See Table 11 for the DIN command.
The bias offset registers in Table 9 and Table 10 provide a
manual adjustment function for each sensor’s output. For
example, if an output offset of 0.125°/sec is observed in the Zaxis gyroscope, the ZGYRO_OFF register provides the
calibration factor necessary to improve the accuracy. Using the
sensitivity of 0.0125°/sec, an adjustment of −10 LSBs is
required. The twos complement, hexadecimal code of −10 LSBs
is 0x1FF6. See Table 11 for the DIN command.
Table 11. Calibration Commands
Table 9. X,Y,ZGYRO_OFF Register Bits
Bits
[15:13]
[12:0]
Description
(Default = 0x0000)
Not used.
Data bits. Twos complement, 0.0125°/sec per LSB.
Typical adjustment range = ±50°/sec.
Table 10. X,Y,ZACCL_OFF Register Bits
Bits
[15:12]
[11:0]
Description
(Default = 0x0000)
Not used.
Data bits, Twos complement 3.3 mg/LSB.
Typical adjustment range = ±6 g.
Calibration Function
Adjust Z-Axis Gyroscope Bias by −0.125°/sec:
Write 0x1F to 0x1F
Write 0xF6 to 0x1E (ZGYRO_OFF)
Automatic Bias Null:
Write 0x01 to 0x3E (COMMAND)
DIN Word(s)
0x9E1F
0x9FF6
Precision Automatic Bias Null:
Write 0x10 to 0x3E (COMMAND)
0xBE10
Factory Calibration Restore:
Write 0x02 to 0x3E (COMMAND)
0xBE02
Enable Linear Acceleration Bias
Compensation for the Gyroscopes:
Write 0x86 to 0x34 (MSC_CTRL)
Enable Origin Alignment for the
Accelerometer Sensors:
Write 0x46 to 0x34 (MSC_CTRL)
0xB486
0xBE01
0xB446
The last two entries assume factory default conditions for the
MSC_CTRL register. The contents may vary, depending on the
other MSC_CTRL settings. See Table 17 for further description
of each bit in this register.
Rev. PrA | Page 12 of 20
Preliminary Technical Data
ADIS16365
OPERATION CONTROL REGISTERS
An example calculation of the default sample period follows:
Global Commands
In addition to the calibration commands, the COMMAND
register provides initiation bits for several other common
functions. Writing a 1 to the assigned COMMAND bit exercises
its function.
Table 12. COMMAND Bit Descriptions
Bits
[15:8]
[7]
[6:5]
[4]
[3]
[2]
[1]
[0]
Description
Not used
Software reset command
Not used
Precision autonull command
Flash update command
Auxiliary DAC data latch
Factory calibration restore command
Autonull command
SMPL_PRD = 0x03, B7 − B0 = 00000011 ->
B7 = 0 → tB = 0.61035 ms, B6…B0 = 000000011 → NS = 3
tS = tB × (NS + 1) = 0.61035 ms × (3+1) = 2.4414 ms
The contents of this register determine whether the device is in
fast mode or low power mode.” Fast mode occurs when the
contents of SMPL_PRD are less than 0x0A. Refer to Table 1 and
Table 2 for the performance trade-offs associated with each mode.
Setting SMPL_PRD = 0x000 activates the external clock.
Power Management
In addition to offering two different performance modes for
power optimization, the ADIS16365 offers a programmable
shutdown period that the SLP_CNT register controls.
Table 14. SLP_CNT Bit Descriptions
The software reset command restarts the internal processor, which
loads all registers with the contents in their flash memory locations.
The flash update copies the contents of all flash backup registers
into their assigned, nonvolatile, flash memory locations. This
process takes approximately 50 ms and requires a power supply
that is within the specified operating range. After waiting the
appropriate time for the flash update to complete, verify successful
completion by reading the STATUS register. If the flash update
is successful, the flash update error is 0. If the flash update is not
successful, reading this error bit accomplishes two things: (1)
alerting the system processor to try again, and (2) clearing the
error flag, which is required for flash memory access.
The DAC data latch command loads the contents of AUX_DAC
into the DAC latches. Because the AUX_DAC contents must be
updated one byte at a time, this command ensures a stable DAC
output voltage during updates.
Bit
[15:8]
[7:0]
Description
(Default = 0x0000)
Not used
Data bits, 0.5 seconds/LSB (0x08, sleep time = 4 sec)
Once in sleep mode, a reset or power cycle is required to wake up.
Digital Filtering
The signal conditioning circuit of each sensor has an analog
bandwidth of approximately 350 Hz. A programmable-length
Bartlett window FIR filter provides opportunity for additional
noise reduction on all output data registers. The SENS/AVG
register controls the number of taps in power-of-two step sizes,
from zero to six.
Filter setup requires one simple step: write the appropriate M
factor to the assigned bits in the SENS/AVG register. The bit
assignments are listed in Table 15. The frequency response
relationship for this filter is
H B ( f ) = H A2 ( f ) H A ( f ) =
Finally, reading the COMMAND register (see
Figure 4) starts the burst mode read sequence.
sin(π × N × f × t s )
N × sin(π × f × t s )
0
Internal Sample Rate
Table 13. SMPL_PRD Bit Descriptions
Bit
[15:8]
[7]
[6:0]
Description
(Default = 0x0001)
Not used
Time base, 0 = 0.61035 ms, 1 = 18.921 ms
Increment setting (NS)
–40
–60
–80
–100
–120
–140
0.001
N=2
N=4
N = 16
N = 64
0.01
0.1
FREQUENCY (f/fS)
Figure 16. Bartlett Window FIR Frequency Response
Rev. PrA | Page 13 of 20
1
07570-010
tS = tB × NS + 1
–20
MAGNITUDE (dB)
The SMPL_PRD register controls the ADIS16365 internal sample
rate and has two parts: a selectable time base and a multiplier. The
following relationship produces the sample rate:
ADIS16365
Preliminary Technical Data
Dynamic Range
VCC
D
C1
Value
100
010
001
[7:3]
[2:0]
Description
(Default = 0x0000)
Not used
Measurement range (sensitivity) selection
300°/sec (default condition)
150°/sec, filter taps ≥ 4 (Bits[2:0] ≥ 0x02)
75°/sec, filter taps ≥ 16 (Bits[2:0] ≥ 0x04)
Not used
Filter tap setting, number of taps, N = 2M;
for example, 011, N = 23 = 8 taps
INPUT/OUTPUT FUNCTIONS
The ADIS16365 provides several input/output functions,
including a 12-bit ADC, a 12-bit DAC, and four general
purpose, digital input/output lines that have several
configuration options.
D
Figure 17. Equivalent Analog Input Circuit
Conversion Phase: Switch Open
Track Phase: Switch Closed
Table 15. SENS/AVG Bit Descriptions
Bits
[15:11]
[10:8]
R1 C2
07570-011
There are three dynamic range settings: ±75°/sec, ±150°/sec,
and ±300°/sec. The lower dynamic range settings (75, 150) limit
the minimum filter tap sizes to maintain the resolution as the
measurement range decreases. The recommended order for
programming the SENS/AVG register is upper byte (sensitivity),
followed by lower byte (filtering). The contents of the
SENS/AVG register are nonvolatile.
For ac applications, it is recommended that high frequency
components from the analog input signal be removed by using
a low-pass filter on the analog input pin.
In applications where harmonic distortion and signal-to-noise
ratios are critical, the analog input must be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This can necessitate the use of
an input buffer amplifier. When no input amplifier is used to drive
the analog input, the source impedance should be limited to
values lower than 1 kΩ.
Auxiliary DAC
Auxiliary ADC
The auxiliary ADC is a standard 12-bit ADC that digitizes other
system-level analog signals. The output of the ADC can be monitored through the AUX_ADC register, as defined in Table 8.
The ADC is a 12-bit successive approximation converter. The
output data is presented in straight binary format with the fullscale range extending from 0 V to 3.3 V.
Figure 17 shows the equivalent circuit of the analog input
structure of the ADC. The input capacitor (C1) is typically 4 pF
and can be attributed to parasitic package capacitance. The two
diodes provide ESD protection for the analog input. Care must
be taken to ensure that the analog input signals are never outside
the range of −0.3 V to +3.5 V. Signals outside this range cause
the diodes to become forward-biased and to start conducting.
The diodes can handle 10 mA without causing irreversible
damage. The resistor is a lumped component that represents
the on resistance of the switches. The value of this resistance is
typically 100 Ω. Capacitor C2 represents the ADC sampling
capacitor and is typically 16 pF.
The auxiliary DAC provides a 12-bit level adjustment function.
The AUX_DAC register controls the operation of the auxiliary
DAC function, which is useful for systems that require analog
level controls. It offers a rail-to-rail buffered output that has a
range of 0 V to 3.3 V. The DAC can drive its output to within
5 mV of the ground reference when it is not sinking current.
As the output approaches ground, the linearity begins to degrade
(100 LSB beginning point). As the sink current increases, the
nonlinear range increases. The DAC output latch function,
contained in the COMMAND register, provides continuous
operation while writing to each byte of this register. The
contents of this register are volatile, which means that the
desired output level must be set after every reset and power
cycle event.
Table 16. AUX_DAC Bit Descriptions
Bit
[15:12]
[11:0]
Rev. PrA | Page 14 of 20
Description
(Default = 0x0000)
Not used
Data bits, scale factor = 0.8059 mV/code
Offset binary format, 0 V = 0 codes
Preliminary Technical Data
ADIS16365
DIAGNOSTICS
Data-Ready I/O Indicator
The MSC_CTRL register provides controls for a data-ready
function. For example, writing 0x05 to this register enables this
function and establishes DIO2 as an active-low, data-ready line.
The duty cycle is 25% (±10% tolerance).
Table 17. MSC_CTRL Bit Descriptions
Bits
[15:12]
[11]
[10]
[9]
[8]
[7]
[6]
[5:3]
[2]
[1]
[0]
Description
(Default = 0x0000)
Not used
Flash test
Internal self-test enable (clears on completion)
1 = enabled, 0 = disabled
Manual self-test, negative stimulus
1 = enabled, 0 = disabled
Manual self-test, positive stimulus
1 = enabled, 0 = disabled
Linear acceleration bias compensation for gyroscopes
1 = enabled, 0 = disabled
Linear accelerometer origin alignment
1 = enabled, 0 = disabled
Not used
Data-ready enable, 1 = enabled, 0 = disabled
Data-ready polarity, 1 = active high, 0 = active low
Data-ready line select, 1 = DIO2, 0 = DIO1
Self-Test
Self-test exercises the mechanical structure of the sensor and
provides a simple method for verifying the operation of the
entire sensor signal conditioning circuit. There are two different
self-test options: startup and manual. If either of these self-tests
results in a failure, the self-test error flag, located in the STATUS
register, sets to 1. The manual self-test option results in a
repeating pattern, until the bit is set back to 0. While in the
manual self-test loop, SMPL_PRD and AVG_CNT cannot be
changed. See Table 17 for the appropriate MSC_CTRL bit
designations.
Alarm Registers
The alarm function provides monitoring for two independent
conditions. The ALM_CTRL register provides control inputs
for data source, data filtering (prior to comparison), static/
dynamic, and output indicator configurations. The ALM_MAGx
registers establish the trigger threshold and polarity configurations. The ALM_SMPLx registers provide the numbers of
samples to use in the dynamic, rate-of-change configuration.
The rate-of-change calculation is
YC =
General Purpose I/O
1
N DS
N DS
∑
y (n + 1) − y (n) ⇒ Alarm ⇒ is YC > or < M C ?
n =1
The GPIO_CTRL register controls the direction and data of the
general-purpose digital lines, DIO1 through DIO4. For example,
writing a 0x02 to the GPIO_CTRL register sets DIO2 as an
output line and DIO1, DIO3, and DIO4 as input lines. Reading
the data bits in GPIO_CTRL reveals the logic level of each line.
where:
NDS is the number of samples in ALM_SMPLx.
y(n) is the sampled output data.
MC is the magnitude for comparison in ALM_MAGx.
> or < is determined by the MSB in ALM_MAGx.
Table 18. GPIO_CTRL Bit Descriptions
Table 19. ALM_MAG1/ALM_MAG2 Bit Designations
Bit
[15:12]
[11]
[10]
[9]
[8]
[7:4]
[3]
Bit
[15]
[14]
[13:0]
[2]
[1]
[0]
Description
(Default = 0x0000)
Not used
General-Purpose I/O Line 4 data level
General-Purpose I/O Line 3 data level
General-Purpose I/O Line 2 data level
General-Purpose I/O Line 1 data level
Not used
General-Purpose I/O Line 4, data direction control
1 = output, 0 = input
General-Purpose I/O Line 3, data direction control
1 = output, 0 = input
General-Purpose I/O Line 2, data direction control
1 = output, 0 = input
General-Purpose I/O Line 1, data direction control
1 = output, 0 = input
Description
(Default = 0x0000)
Comparison polarity: 1 = greater than, 0 = less than
Not used
Data bits, matches format of trigger source selection
Table 20. ALM_SMPL1/ALM_SMPL2 Bit Designations
Bit
[15:8]
[7:0]
Rev. PrA | Page 15 of 20
Description
(Default = 0x0001)
Not used
Data bits: number of samples (both 0x00 and 0x01 = 1)
ADIS16365
Preliminary Technical Data
Status
Table 21. ALM_CTRL Bit Designations
Bits
[15:12]
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
[11:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
Description
(Default = 0x0000)
Alarm 2 source selection
Disable
Power supply output
X-axis gyroscope output
Y-axis gyroscope output
Z-axis gyroscope output
X-axis accelerometer output
Y-axis accelerometer output
Z-axis accelerometer output
X-axis gyroscope temperature output
Y-axis gyroscope temperature output
Z-axis gyroscope temperature output
Auxiliary ADC input
Alarm 1 source selection (same as Alarm 2)
Rate of change (ROC) enable for Alarm 2
1 = rate of change, 0 = static level
Rate of change (ROC) enable for Alarm 1
1 = rate of change, 0 = static level
Not used
Comparison data filter setting1
1 = filtered data, 0 = unfiltered data
Not used
Alarm output enable
1 = enabled, 0 = disabled
Alarm output polarity
1 = active high, 0 = active low
Alarm output line select
1 = DIO2, 0 = DIO1
The STATUS register provides a series of error flags that
provide indicator functions for common system-level issues.
All of the flags clear (set to 0) after each STATUS register read
cycle. If an error condition remains, the error flag returns to 1
during the next sample cycle.
Table 22. STATUS Bit Descriptions
Bit
[15:10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Incline and vertical angles always use filtered data in this comparison.
Rev. PrA | Page 16 of 20
Description
(Default = 0x0000)
Not used
Alarm 2 status
1 = active, 0 = inactive
Alarm 1 status
1 = active, 0 = inactive
Not used
Flash failure
Self-test diagnostic error flag
1 = error condition, 0 = normal operation
Not used
SPI communications failure
1 = error condition, 0 = normal operation
Flash update failed
1 = error condition, 0 = normal operation
Power supply above 5.25 V
1 ≥ 5.25 V, 0 ≤ 5.25 V (normal)
Power supply below 4.75 V
1 ≤ 4.75 V, 0 ≥ 4.75 V (normal)
Preliminary Technical Data
ADIS16365
OUTLINE DIMENSIONS
31.900
31.700
31.500
23.454
23.200
22.946
9.464
9.210
8.956
(2×)
2.382
BSC
17.41
17.21
17.01
(2×)
1.588
BSC
TOP VIEW
22.964
22.710
22.456
1.588
BSC
10.60
BSC
10.50
BSC
21.410
21.210
21.010
BOTTOM VIEW
5.20
5.00
4.80
(2×)
14.950
14.550
14.150
PIN 24
4.20
4.00
3.80
(2×)
0.05
BSC
PIN 1
7.18
BSC
1.00
BSC
2.00 BSC
12.10
BSC
FRONT VIEW
23.504
23.250
22.996
2.660
2.500
2.340
SIDE VIEW
4.330
BSC
DETAIL A
DETAIL A
1.00
BSC (22×)
1.65 BSC
14.00 BSC
011108-C
0.305
BSC (24×)
4.162 BSC
Figure 18. 24-Lead Module with Connector Interface
(ML-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADIS16365BMLZ 1
ADIS16365/PCBZ1
1
Temperature Range
−40°C to +105°C
Package Description
24-Lead Module with Connector Interface
Interface Board
Z = RoHS Compliant Part.
Rev. PrA | Page 17 of 20
Package Option
ML-24-2
ADIS16365
Preliminary Technical Data
NOTES
Rev. PrA | Page 18 of 20
Preliminary Technical Data
ADIS16365
NOTES
Rev. PrA | Page 19 of 20
ADIS16365
Preliminary Technical Data
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07570-0-6/08(PrA)
Rev. PrA | Page 20 of 20
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