EMC EM78P451SAQ 8-bit microcontroller with otp rom Datasheet

EM78P451S
8-Bit Microcontroller
with OTP ROM
Product
Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
June 2004
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Copyright © 2005 by ELAN Microelectronics Corporation
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Contents
Contents
1
2
3
4
GENERAL DESCRIPTION................................................................................................... 1
FEATURES........................................................................................................................... 1
PIN ASSIGNMENT ............................................................................................................... 2
FUNCTION DESCRIPTION.................................................................................................. 4
4.1
Operational Registers ..................................................................................................4
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.2
R0 (Indirect Address Register) ...................................................................................... 4
R1 (TCC) ....................................................................................................................... 4
R2 (Program Counter) & Stack...................................................................................... 4
R3 (Status Register) ...................................................................................................... 6
R4 (RAM Select Register) ............................................................................................. 6
R5~R8 (Port 5 ~ Port8).................................................................................................. 7
R9 (Port9) ...................................................................................................................... 7
RA (SPIRB: SPI Read Buffer)........................................................................................ 8
RB (SPIWB: SPI Write Buffer)....................................................................................... 8
RC (SPIS: SPI Status Segister)..................................................................................... 8
RD (SPIC: SPI Control Register)................................................................................... 9
RE (TMR1: Timer1 register) ........................................................................................ 10
RF (PWP: Pulse width preset register)........................................................................ 10
R20~R3E (General Purpose Register)........................................................................ 10
R3F (Interrupt Status Register) ................................................................................... 10
Special Purpose Registers .........................................................................................10
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
A (Accumulator) ........................................................................................................... 10
CONT (Control Register) ............................................................................................. 11
IOC5 ~ IOC9 (I/O Port Control Register)..................................................................... 11
IOCC (T1CON: Timer1 control register) ...................................................................... 11
IOCD (Pull-high Control Register) ............................................................................... 12
IOCE (WDT Control Register) ..................................................................................... 12
IOCF (Interrupt Mask Register) ................................................................................... 13
4.3
TCC/WDT Presacler ..................................................................................................14
4.4
I/O Ports .....................................................................................................................15
4.5
SERIAL PERIPHERAL INTERFACE MODE..............................................................17
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.6
Overview & Features ................................................................................................... 17
SPI Function Description ............................................................................................. 19
SPI Signal & Pin Description ....................................................................................... 20
Programmed the related registers............................................................................... 22
SPI Mode Timing ......................................................................................................... 24
Software Application of SPI ......................................................................................... 25
Timer 1 .......................................................................................................................30
4.6.1
4.6.2
Overview...................................................................................................................... 30
Function description .................................................................................................... 30
Product Specification (V1.0) 06.01.2004
• iii
Contents
4.6.3
Programmed the related registers............................................................................... 30
4.7
RESET and Wake-up .................................................................................................31
4.8
Interrupt......................................................................................................................37
4.9
Oscillator ....................................................................................................................38
4.9.1
4.9.2
4.9.3
Oscillator Modes.......................................................................................................... 38
Crystal Oscillator/Ceramic Resonators (XTAL) ........................................................... 38
RC Oscillator Mode ..................................................................................................... 40
4.10 Code Option Register.................................................................................................41
4.11 Instruction Set ............................................................................................................42
5
6
4.12 Timing Diagrams ........................................................................................................45
ABSOLUTE MAXIMUM RATING ....................................................................................... 46
ELECTRICAL CHARACTERISTICS.................................................................................. 46
6.1
7
DC Characteristic .......................................................................................................46
6.2 AC Characteristic .......................................................................................................47
Application Circuit ............................................................................................................ 48
APPENDIX
A
B
Package Types .................................................................................................................. 49
Package Information......................................................................................................... 49
Specification Revision History
iv •
Doc. Version
Revision Description
Date
1.0
Initial version
06/01/2004
Product Specification (V1.0) 06.01.2004
EM78P451S
8-Bit Microcontroller with OTP ROM
1
GENERAL DESCRIPTION
The EM78P451S is an 8-bit microprocessor designed and developed with low-power,
high speed CMOS technology. Its operational kernel is implemented with RISC-like
architecture and is available in the mask ROM version. The one time programmable
(OTP) version is flexible, both in mass production or engineering test stages. OTP
provide users with unlimited volume with favorable price opportunities. This device is
equipped with the Serial Peripheral Interface (SPI) function. The EM78P451S is very
suitable for wired communication. Only 58 easy-to-learn instructions are needed and
user’s program can be emulated with EMC In-Circuit Emulator (ICE).
2
FEATURES
Operating voltage range: 2.3V~5.5V.
Operating temperature range: 0°C~70°C.
Operating frequency range (base on 2 clocks ):
•
•
Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
Low power consumption:
•
•
Less then 3 mA at 5V/4MHz
Typically 10 µA during sleep mode
Serial Peripheral Interface (SPI) available.
4K × 13 bits on chip ROM (EM78P451S).
11 special function registers.
140× 8 bits on chip general-purposed registers.
5 bi-directional I/O ports (35 I/O pins).
3 LED direct sinking pins with internal serial resistors.
Built-in RC oscillator with external serial resistor, ±10% variation.
Built-in power-on reset.
5 stacks for subroutine nesting.
8-bit real time clock/counter (TCC) with overflow interrupt.
Two machine clocks or four machine clocks per instruction cycle.
Power down mode.
Programmable wake up from sleep circuit on I/O ports.
Programmable free running on-chip watchdog timer.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
•1
EM78P451S
8-Bit Microcontroller with OTP ROM
12 wake-up pins.
2 open-drain pins.
2 R-option pins.
32 programmable pull-high input pins.
Packages:
•
•
•
40 pin DIP 600mil : EM78P451SP .
40 pin SOP 450mil: EM78P451SWM
44 pin QFP : EM78P451SAQ.
Four types of interrupts.
•
•
•
•
SPI transmission completed interrupt.
TCC overflow interrupt.
Timer1 comparator match interrupt.
PIN ASSIGNMENT
Vss
1
40
/INT
2
39
R-OSCI
DATA
3
38
VDD
CLK
4
37
P70//RESET
P90
5
36
P71
P91
6
35
P72
P70//RESET
34
P67
NC
33
P66
NC
32
P65
31
P64
7
8
P94/SCK
9
P95//SS
10
P50
11
30
P63
P51
12
29
P62
P52
13
28
P61
EM78P451SP
P92/SDI
P93/SDO
P71
P72
P67
P66
P65
P64
P63
P62
P61
P60
P87
OSCO
33
34
32
31
30
29
28
27
26
25
24
23
22
P86
35
21
P85
36
20
P84
NC
37
19
P83
VDD
38
18
P82
R-OSCI
39
17
NC
OSCO
40
16
P81
Vss
41
15
P80
EM78P451AQ
14
P57
25
P86
13
P56
P56
17
24
P85
CLK
44
12
P55
P57
18
23
P84
P80
19
22
P83
P81
20
21
P82
1
2
3
4
5
6
7
8
9
10
11
P54
42
43
P53
/INT
DATA
P52
P87
P51
26
16
P50
15
P55
P95//SS
P54
P94/SCK
P60
P92/SDI
27
P93/SDO
14
P91
P53
P90
3
External interrupt (/INT).
Fig. 1 Pin Assignment
2•
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Table 1 Pin description
Symbol
Pin No.
Type
Function Description
R-OSCI
39
I
In XTAL mode: Crystal input; In internal C, external R mode: 56Kohm±5% pull
high for 1.8432MHz.
OSCO
40
O
In XTAL mode: Crystal output; In RC mode: Instruction clock output.
P90~P95
5~10
I/O
P80~P87
19~26
I/O
P70~P72
37~35
I/O
P70/
RESET
37
I/O
CLK
4
I/O
DATA
3
I/O
P60~P67
27~34
I/O
P50~P57
11~18
I/O
VDD
38
-
Power supply pin.
VSS
1
-
Ground pin.
/INT
2
I
An interrupt schmitt-triggered pin.
The function of interrupt triggers at the falling edge.
Users can enable it by software.
SDI
7
I/O
Serial data in for SPI
SDO
8
I/O
Serial data out for SPI.
SCK
9
I/O
Serial clock for SPI.
/SS
10
I/O
/Slave select for SPI.
General bi-directional I/O port. All of its pins can be pulled-high by software.
P90 and P91 are pin-change wake up pins.
General bi-directional I/O port. All of its pins can be pulled-high by software.
P80 and P81 are also used as the R-option pins.
LED direct-driving pin with internal serial resistor used as output and is
software defined.
LED direct-driving pin with internal serial resistor used as output and is
software defined.
Code option bit 3 (REN): reset enable
REN=0 => for reset pin
REN=1 => for general purpose I/O (P70)
Internal pull high resistor 220Kohm
By connecting P74 and P76 together.
P74 can be pulled-high by software and it is also a pin-change wake up pin.
P76 can be defined as an open-drain output.
By connecting P75 and P77 together.
P75 can be pulled-high by software and it is also a pin-change wake up pin.
P77 can be defined as an open-drain output.
General bi-directional port. All of its pins can be pulled-high by software, and
pin-change wake up pins.
General bi-directional I/O port. All of its pins can be pulled-high individually by
software.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
•3
EM78P451S
8-Bit Microcontroller with OTP ROM
4
FUNCTION DESCRIPTION
WDT Timer
WDT
Time-out
STACK 1
PC
STACK 2
Prescaler
STACK 3
Oscillator/
Timming
Control
/ INT
STACK 4
ROM
STACK 5
Interrupt
Control
R1(TCC)
Sleep
&
Wake Up
Control
Instruction
Register
ALU
Instruction
Decoder
RAM
R3
ACC
TMR1
R4
DATA & CONTROL BUS
IOC5
R5
IOC6
R6
IOC7
R7
PPPPPPPP
55555555
01234567
PPPPPPPP
66666666
01234567
P
7
0
P
7
1
IOC9
R9
IOC8
R8
P
7
2
P PPP
9 9 9 9
0 1 2 3
/ /
SS
DD
I O
PPPPPPPP
88888888
01234567
P
9
4
/
S
C
K
SPI
ENGIN
P
5
5
/
/
S
S
Fig. 2 Functional Block Diagram
4.1 Operational Registers
4.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing
pointer. Any instruction using R0 as register actually accesses data pointed by the
RAM Select Register (R4).
4.1.2 R1 (TCC)
Increased by the instruction cycle clock.
Written and read by program as any other register.
4.1.3 R2 (Program Counter) & Stack
R2 and the hardware stacks are 12 bits wide.
The structure is depicted in Fig. 3.
Generates 4K × 13 on-chip ROM addresses to the relative programming instruction
codes. One program page is 1024 words long.
All the R2 bits are set to "1"s as a RESET condition occurs.
4•
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows jump to any location on one page.
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
at the top of stack.
"MOV R2, A" allows the loading of an address from the "A" register to the lower 8
bits of PC, and the ninth and tenth bits (A8~A9) of PC are cleared.
"ADD R2, A" allows a relative address be added to the current PC, and the ninth
and tenth bits of PC are cleared.
Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅)
(except "TBL") will cause the ninth and tenth bits (A8~A9) of PC to be cleared.
Thus, the computed jump is limited to the first 256 locations of any program page.
"TBL" allows a relative address be added to the current PC (R2+A→R2), and
contents of the ninth and tenth bits (A8~A9) of PC are not changed. Thus, the
computed jump can be on the second (or third, 4th) 256 locations on one program
page.
In case of EM78P451S, the most significant bits (A10~A11) will be loaded with the
contents of bits PS0~PS1 in the status register (R3) upon the execution of a "JMP",
"CALL", or any other instructions which writes to R2.
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents R2. Such instruction will need one more
instruction cycle.
R3
A11 A10 A9 A8
A7
~
A0
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
11 PAGE3 0C00~0FFF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
000H
001H
002H
User Memory
Space
CALL
RET
RETL
RETI
Hardware Vector
Software Vector
On-chip Program
Memory
Reset Vector
FFFH
Fig. 3 Program Counter Organization
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
•5
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.4 R3 (Status Register)
7
6
5
4
3
2
1
0
GP
PS1
PS0
T
P
Z
DC
C
Bit7 (GP) General read/write bit.
Bit6 (PS1) ~ 5 (PS0) Page select bits. PS0~PS1 are used to pre-select a program
memory page. When executing a "JMP", "CALL", or other instructions which
causes the program counter to be changed (e.g. MOV R2, A), PS0~PS1 are
loaded into the 11th and 12th bits of the program counter where it selects
selecting one of the available program memory pages. Note that RET (RETL,
RETI) instruction does not change the PS0~PS1 bits. That is, the return will
always be to the page from where the subroutine was called, regardless of
the current setting of PS0~PS1 bits. PS1 bit is not used (read as "0") and
cannot be modified in EM78P451S.
PS1
PS0
Program memory page [Address]
0
0
Page 0 [000-3FF]
0
1
Page 1 [400-7FF]
1
0
Page 2 [800-BFF]
1
1
Page 3 [C00-FFF]
Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during
power up and reset to 0 with WDT timeout.
Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and
reset to 0 by a "SLEP" command.
Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 1 (DC) Auxiliary carry flag
Bit 0 (C) Carry flag
4.1.5 R4 (RAM Select Register)
Bits 7~6 determine which bank is activated among the 4 banks.
Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing
mode.
If no indirect addressing is used, the RSR is used as an 8-bit general-purposed
read/writer register.
See the configuration of the data memory in Fig. 4.
6•
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.6 R5~R8 (Port 5 ~ Port8)
Four general 8 bits I/O registers
Both P74 and P76 read or write data from the DATA pin, while both P75 and P77
read or write data from the CLK pin.
4.1.7 R9 (Port9)
A general 6-bit I/O register. The values of the two most significant bits are read as
"0".
Aaddress
R PAGE registers
IOC PAGE registers
00
R0
(Indirect Addressing Register)
01
R1
(Time Clock Counter)
02
R2
(Program Counter)
Reserve
03
R3
(Status Register)
Reserve
04
R4
(RAM Select Register)
Reserve
05
R5
(Port5)
IOC5
(I/O Port Control Register)
06
R6
(Port6)
IOC6
(I/O Port Control Register)
07
R7
(Port7)
IOC7
(I/O Port Control Register)
08
R8
(Port8)
IOC8
(I/O Port Control Register)
09
R9
(Port9)
IOC9
(I/O Port Control Register)
0A
RA
(SPI read buffer)
Reserve
0B
RB
(SPI write buffer)
Reserve
0C
RC
(SPI status buffer)
IOCC
0D
RD
(SPI control buffer)
IOCD (Pull_high Control Register)
0E
RE
(Timer1 register)
IOCE
(WDT Control Register)
0F
RF
(Pulse width preset register)
IOCF
(Interrupt Mask Register)
10
︰
1F
Reserve
CONT (Control Register)
(Timer1 Control Register)
General Registers
20
:
3E
Bank0
3F
R3F
Bank1
Bank2
Bank3
(Interrupt Status Register)
Fig. 4 Data memory configuration
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
•7
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.8 RA (SPIRB: SPI Read Buffer)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0X0A
SPIRB/RA
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB7~SRB0 are the 8-bit data when complete transmission by SPI.
4.1.9 RB (SPIWB: SPI Write Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIWB/RB SWB7
Name
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
Address
0x0B
SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
4.1.10 RC (SPIS: SPI Status Segister)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C
SPIS/RC
--
--
--
TM1IF
OD3
OD4
RBFIF
RBF
Bits 7 ~ 5
Not used.
Bit 4 (TM1IF):
0 = In timer1 mode, receiving not completed yet, and an interrupt does
not occur.
1 = In timer1 mode, receiving completed, and an interrupt occurs if
enabled.
Bit 3 (OD3): Open-Drain Control bit
0 = Open-drain disable for SDO.
1 = Open-drain enable for SDO,
Bit 2 (OD4): Open-Drain Control bit
0 = Open-drain disable for SCK.
1 = Open-drain enable for SCK,
Bit 1 (RBFIF):Read Buffer Full Interrupt Flag
0 = Receiving not completed yet; and SPIRB has not fully exchanged.
1 = Receiving completed, SPIRB is fully exchanged, and an interrupt
occurs if enabled.
Bit 0 (0RBF):Read Buffer Full flag
0 = Receiving not completed yet, and SPIRB has not fully exchanged.
1 = Receiving completed; SPIRB is fully exchanged.
8•
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.11 RD (SPIC: SPI Control Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0D
SPIC/RD
CES
SPIE
SRO
SSE
-
SBRS2
SBRS1
SBRS0
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on
hold during the low level.
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on
hold during the high level.
Bit 6 (SPIE): SPI Enable bit
0= Disable SPI mode
1= Enable SPI mode
Bit 5 (SRO): SPI Read Overflow bit
0 = No overflow
1 = A new data is received while the previous data is still being held in the
SPIB register. In this situation, the data in SPIS register will be destroyed.
To avoid setting this bit, users had better read SPIRB register even if only
the transmission is implemented.
NOTE
This can only occur in slave mode.
Bit 4 (SSE): SPI Shift Enable bit
0 = Reset as soon as the shifting is complete, and the next byte is ready
to shift.
1 = Start to shift, and keep on 1 while the current byte is still being
transmitted.
NOTE
This bit will reset to 0 at every one-byte transmission by the hardware
Bit 2~Bit 0 (SBRS): SPI Baud Rate Select bits
SPI baud rate table is illustrated in SPI section in later pages.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
•9
EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.12 RE (TMR1: Timer1 register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0X0E
TMR1/RE
TMR17
TMR16
TMR15
TMR14
TMR13
TMR12
Bit 1
Bit 0
TMR11 TMR10
TMR17~TMR10 is bit set of timer1 register and it increases until the value matches
PWP and then, it resets to 0.
4.1.13 RF (PWP: Pulse width preset register)
Address Name
0x0F
PWP/RF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWP7
PWP6
PWP5
PWP4
PWP3
PWP2
PWP1
PWP0
PWP7~PWP0 is bit set of pulse width preset in advance for the desired width of baud
clock.
4.1.14 R20~R3E (General Purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
4.1.15 R3F (Interrupt Status Register)
Address Name
0x3F
Bits 7~4
ISR/R3F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
TM1IF
SPIIF
EXIF
TCIF
are not used and read as “0”.
Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag
cleared by software.
Bit 2 (SPIIF) SPI interrupt flag. Set by data transmission complete, flag cleared by
software.
Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by
software
Bit 0 (TCIF) the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared
by software.
"1" means interrupt request, "0" means non-interrupt.
R3F can be cleared by instruction, but cannot be set by instruction.
IOCF is the interrupt mask register.
Note that to read R3F will result to "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
4.2.1
A (Accumulator)
Internal data transfer, or instruction operand holding.
A non-addressable register.
10 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.2.2
CONT (Control Register)
7
6
5
4
3
2
1
0
/PHEN
/INT
-
-
PAB
PSR2
PSR1
PSR0
Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled.
1: The pull-high function is disabled.
Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction.
0: interrupt masked by the DISI instruction.
1: interrupt enabled by the ENI or RETI instruction.
Bit5, 4
Not used, and to be read as “0”.
Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
Bit 2 (PSR2) ~ Bit 0 (PSR0) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bits 0~3, and 7 of the CONT register are readable and writable.
4.2.3
IOC5 ~ IOC9 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as
output.
Both P74 and P76 should not be defined as output pins at the same time. This also
applies to both P75 and P77.
Only the lower 6 bits of the IOC9 register are used.
4.2.4
IOCC (T1CON: Timer1 control register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0C
T1CON/IOCC
0
0
0
0
0
TM1E
TM1P1
TM1P0
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 11
EM78P451S
8-Bit Microcontroller with OTP ROM
Bit2 (TM1E): Timer1 Function Enable bit
0 = Disable timer1 function as default.
1 = Enable timer1 function.
Bit1~Bit0 (TM1P): Timer1 Prescaler bit
Timer1 prescaler table for FOSC will be illustrated in the Section on
Timer1 in later pages.
4.2.5
IOCD (Pull-high Control Register)
7
6
5
4
3
2
1
0
S7
-
-
-
/PU9
/PU8
/PU6
/PU5
The default values of /PU5, /PU6, /PU8, and /PU9 are one, which means the
pull-high function is disabled.
/PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written as
“0” pull high is enabled.
S7 defines the driving ability of the P70-P72.
0: Normal output.
1: Enhance the driving ability of LED.
4.2.6
IOCE (WDT Control Register)
7
6
5
4
3
2
1
0
-
ODE
WDTE
SLPC
ROC
-
-
/WUE
Bits 7, and1~2 Not used.
Bit 6 (ODE) Open-drain control bit.
0: Both P76 and P77 are normally I/O pins.
1: Both P76 and P77 pins have the open-drain function inside.
The ODE bit can be read and written.
Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If
the ENWDT bit is "1", then WDT can be disabled/enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0".
That is, if the ENWDT bit is "0", WDT is always disabled no matter what the
WDTE bit is.
The WDTE bit can be read and written.
12 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is
cleared in software. SLPC is used to control the oscillator operation. The
oscillator is disabled (oscillator is stopped, and the controller enters the
SLEEP2 mode) on the high-to-low transition and is enabled (the controller
is awakened from SLEEP2 mode) on low-to-high transition. In order to
ensure the stable output of the oscillator, once the oscillator is enabled
again, there is a delay for approximately 18 ms (oscillator start-up timer
(OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option bit
ENWDT is "0" or not. After waking up, the WDT is enabled if Code Option
ENWDT is "1". The block diagram of SLEEP2 mode and wake-up caused
by input triggered is depicted in Fig. 5. The SLPC bit can be read and
written.
Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of
R-option pins (P80, P81) to be read by the controller. Clearing ROC will
disable the R-option function. Otherwise, the R-option function is
introduced. Users must connect the P81 pin or/and P80 pin to VSS by a
560KΩ external resistor (Rex). If Rex is connected/disconnected with
VDD, the status of P80 (P81) will be read as "0"/"1" (refer to Fig. 7(b)). The
ROC bit can be read and written.
Bit 0 (/WUE) Control bit used to enable the wake-up function of P60~P67, P74~P75,
and P90~P91.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
4.2.7
IOCF (Interrupt Mask Register)
7
6
5
4
3
2
1
0
-
-
-
-
TM1IE
SPIIE
EXIE
TCIE
Bits 4~7 Not used.
Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
The IOCF Register could be read and written.
Bit 3 (TM1IE) TM1IE interrupt enable bit.
0: disable TM1IE interrupt
1: enable TM1IE interrupt
Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
1: enable SPI interrupt
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 13
EM78P451S
8-Bit Microcontroller with OTP ROM
Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
/W U E
O scillator
E n ab le
D isab le
/W U E
R eset
Q
Q
C lear
P D
R
C LK
C
L
VCC
S et
8
/W U E
fro m S /W
P 60~P 67
VCC
/W U E
/P H E N
4
P 74~P 75, P 90~P 91
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
4.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is
available for either the TCC or WDT only at any given time, and the PAB bit of CONT
register is used to determine the prescaler assignment. The PSR0~PSR2 bits
determine the prescale ratio. The prescaler is cleared each time the instruction is
written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT
mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit
diagram of TCC/WDT.
R1(TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction
cycle (without prescaler).
14 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep
running even when the oscillator driver has been turned off (i.e. in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during the normal
mode by software programming (if Code Option bit ENWDT is "1"). Refer to
WDTEbit of IOCE register. Without presacler, the WDT time-out period is
approximately 18 ms1.
4.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67,
P74~P75, and P90~P91 provide internal pull-high. P60~P67, P74~P75, and P90~P95
provide programmable wake-up function through software. P76~P77 can have
open-drain output by software control. P80~P81 are the R-option pins which are
enabled by software. When the R-option function is used, it is recommended that P80
and P81 are used as output pins. During R-option enabled state, P80 and P81 must be
programmed as input pins. If an external resistor is connected to P80 (P81) for the
R-option function, the current consumption should be taken as an important factor in
the applications for low power consideration.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers
(IOC5~IOC9) under program control. The I/O registers and I/O control registers are
both readable and writable. The I/O interface circuit is shown in Fig. 7. Note that the
reading path source of input and output pins is different when reading the I/O port.
Data Bus
CLK(=Fosc/2)
1
M
U
X
SYNC
2 cycles
TCC(R1)
0
TCC overflow interrupt
PAB
0
WDT
1
M
U
X
8-bit Counter
PSR0~PSR2
8 - to -1 MUX
0
WDTE
(in IOCE)
1
MUX
PAB
WDT timeout
Fig. 6 Block Diagram of TCC WDT
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 18.0ms ± 30%
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 15
EM78P451S
8-Bit Microcontroller with OTP ROM
PCRD
P D
R
CLK
Q C
L
Q
PCWR
IOD
P
R D
C CLK
Q L
PORT
Q
0
1
PDWR
M
U
X
PDRD
Fig. 7 (a) The Circuit of I/O Port and I/O Control Register
PCRD
VCC
ROC
Q
Weakly
Pull-up
Q
PORT
0
Rex*
1
M
U
X
P
D
R
CLK
C
L
PCWR
IOD
Q
P
R
Q
C CLK
L
D
PDWR
PDRD
*The Rex is 560K ohm external resistor
Fig.7(b) The Circuit of I/O Port with R-option (P80, P81)
16 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5 SERIAL PERIPHERAL INTERFACE MODE
4.5.1 Overview & Features
Overview:
Figures 8, 9, and 10 show how EM78P451S communicates with other devices through
SPI module. If EM78P451S is a master controller, it sends clock through the SCK pin.
A couple of 8-bit data are transmitted and received at the same time. However, if
EM78P451S is defined as a slave, its SCK pin could be programmed as an input pin.
Data will continue to be shifted based on both the clock rate and the selected edge.
Features:
Operation in either Master mode or Slave mode,
Three-wire or four-wire synchronous communication; that is, full duplex
Programmable baud rates of communication,
Programming clock polarity, (RD bit7)
Interrupt flag available for the read buffer full,
Up to 8 MHz ( maximum ) bit frequency,
SDO
SPIR Reg
SPIW
SPIW Reg
Reg
/SS
SPIS Reg
SDI
SPI Module
Bit 7
Master Device
SCK
Slave Device
Fig. 8 SPI Master/Slave Communication
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 17
EM78P451S
8-Bit Microcontroller with OTP ROM
SDI
SDO
SCK
/SS
Vdd
Master
P50
P51
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave Device 1
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 9 The SPI Configuration of Single-Master and Multi-Slave
SDI
SDO
SCK
/SS
SDI
SDO
SCK
/SS
Master1
or
P50
Slave1 P51
Master2
or
P50
P51 Slave6
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave 2 for master 1
P52
P53
Slave 3 for Master 1/2 Slave 4 for Master1/2
Slave 5 for Master 2
Fig. 10 The SPI Configuration of Single-Master and Multi-Slave
18 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5.2 SPI Function Description
Read
RBF
RBFI
W rite
S P IR
SE
re g
S P IW
re g
S e t to 1
B u ffe r F u ll D e te c to r
S P IS
P 9 2 /S D I
s h ift rig h t
re g
b it 0
b it 7
S P IC re g
P 9 3 /S D O
Edge
S e le c t
SB R 0 ~SB R2
P 9 5 / /S S
SBR 2~SB R 0
8
/ SS
P re sc aler
4 , 8 , 1 6, 32 , 6 4
T sco
N o is e
F ilte r
C lo c k S e le c t
2
Edge
S e le c t
P 9 4 /S C K
T M R 1 /2
S P IC b it6
Fig. 11 SPI Block Diagram
SPI
SPI Read Register
(0X0A)
7~0
SPIWB
/SS
SPI Write Register
(0X0B)
8-1 MUX
SPI Mode Select
Register
2 1 0
SPIC
SDO
SDI
Shift Clock
SPI Shift Buffer
FOSC
1 0
7 6 4 1 0
T1CON
SPIC
SPIS
2
4
INTC
SPIC
7~0
SPIRB
DATA BUS
Fig. 12 The Function Block Diagram of SPI Transmission
The following describes the function of each block and explains how to carry out the
SPI communication with the signals depicted in Fig.11 and Fig.12:
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 19
EM78P451S
8-Bit Microcontroller with OTP ROM
P92/SDI:Serial Data In.
P93/SDO:Serial Data Out.
P94/SCK: Serial Clock.
P95//SS:/Slave Select (Option). This pin (/SS) may be required during a slave
mode.
RBF: Set by Buffer Full Detector, and reset in software.
RBIF: Set by Buffer Full Detector, and reset in software.
Buffer Full Detector: Sets to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.:Shifting byte in and out. The MSB is shifted first. Both the SPIS register
and the SPIW register are loaded at the same time. Once data are written, SPIS
starts transmission / reception. The received data will be moved to the SPIR
register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full)
flag and the RBFI(Read Buffer Full Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.:Write buffer. The buffer will deny any attempt to write until the 8-bit
shifting is completed.
The SSE bit will be kept in 1 if the communication is still undergoing. This flag must be
cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0:Programming the clock frequency/rates and sources.
Clock Select:Selecting either the internal or external clock as the shifting clock.
Edge Select:Selecting the appropriate clock edges by programming the CES bit
4.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in
Fig. 9, are as follows:
SDI/P92 (Pin 7):
Serial Data In,
Receive serially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last,
Defined as high-impedance, if not selected,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
20 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
The received byte will update the transmitted byte,
Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI
operation is completed.
Timing is shown in Fig.13 and14.
SDO/P93 (Pin 8):
Serial Data Out,
Transmit serially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
The received byte will update the transmitted byte,
The CES (located in Register 0x0D) bit will be reset, as the SPI operation is
completed.
Timing is shown in Fig.13 and 14.
SCK/P94 (Pin 9):
Serial Clock
Generated by a master device
Synchronize the data communication on both the SDI and SDO pins
The CES (located in Register 0x0D) is used to select the edge to communicate.
The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
The CES, SBR0, SBR1, and SBR2 bits have no effect in the slave mode
Timing is show in Fig.13 and 14
/SS/P95 (Pin 10):
Slave Select; negative logic,
Generated by a master device to signify the slave(s) to receive data,
Goes low before the first cycle of SCK appears, and remains low until the last
(eighth) cycle is completed,
Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is
no longer driven.
Timing is shown in Fig.13 and Fig. 14.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 21
EM78P451S
8-Bit Microcontroller with OTP ROM
4.5.4 Programmed the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2
and Table 3.
Table 2 Related Control Registers of the SPI Mode
Address
0x0D
0x0F
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*SPIC/RD CES
INTC/IOCF
--
SPIE
--
SRO
--
SSE
--
-TM1IE
SBR2
SPIIE
SBR1
EXIE
SBR0
TCIE
SPIC: SPI Control Register.
Bit 7 (CES): Clock Edge Select bit
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold
during the low level.
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold
during the high level.
Bit 6 (SPIE):SPI Enable bit
0 = Disable SPI mode
1 = Enable SPI mode
Bit 5 (SRO):SPI Read Overflow bit
0 = No overflow.
1 = A new data is received while the previous data is still being on hold in the
SPIB register. Under this condition, the data in SPIS register will be destroyed.
To avoid setting this bit, users should read the SPIRB register even if the
transmission is implemented only.
NOTE
This can only occur under slave mode.
Bit 4 (SSE):SPI Shift Enable bit
0 = Reset as soon as the shifting is completed and the next byte is ready to shift.
1 = Start to shift, and stays on 1 while the current byte continues to transmit.
NOTE
This bit can be reset by hardware only.
22 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Bit 2~0 (S BRS): SPI Baud Rate Select Bits
SBRS2 (Bit 2)
SBRS1 (Bit 1)
SBRS0 (Bit 0)
Mode
Baud Rate
0
0
0
Master
Fsco/2
0
0
1
Master
Fsco/4
0
1
0
Master
Fsco/8
0
1
1
Master
Fsco/16
1
0
0
Master
Fsco/32
1
0
1
Slave
/SS enable
1
1
1
1
0
1
Slave
Master
/SS disable
TMR1/2
NOTE
In master mode, /SS is disable.
INTC: Interrupt control register
Bit 3 (TM1IE) TM1IE interrupt enable bit.
0: disable TM1IE interrupt
1: enable TM1IE interrupt
Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
1: enable SPI interrupt
Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
Table 3 Related Status/Data Registers of the SPI Mode
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0X0A
SPIRB/RA
SRB7
SRB6
SRB5
SRB4
SRB3
SRB2
SRB1
SRB0
0x0B
SPIWB/RB
SWB7
SWB6
SWB5
SWB4
SWB3
SWB2
SWB1
SWB0
0x0C
SPIS/RC
0
0
0
TM1IF
OD3
OD4
RBFIF
RBF
SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to
SPIRB from SPISR. The RBF bit and the RBFIF bit in the SPIS register will be
set also.
SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by
and start to shift the data when sensing SCK edge with SSE set to “1”.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 23
EM78P451S
8-Bit Microcontroller with OTP ROM
SPIS: SPI Status register
Bit 4 (TM1IF):Timer1 interrupt flag.
Bit 3 (OD3)Open-Drain Control bit (P93)
0 = Open-drain disable for SDO.
1 = Open-drain enable for SDO,
Bit 2 (OD4):Open Drain-Control bit (P94)
0 = Open-drain disable for SCK.
1 = Open-drain enable for SCK
Bit 1 (RBFIF):Read Buffer Full Interrupt flag
1 = Receive is completed, SPIB is full, and an interrupt occurs if enabled.
0 = Receive is ongoing, SPIB is empty.
Bit 0 (RBF):Read Buffer Full flag
0 = Receive is ongoingt, SPIB is empty.
1 = Receive is completed, SPIB is full.
4.5.5 SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13
is applicable regardless of whether the EM78P451S is under master or slave mode
with /SS disabled. However, The waveform in Fig. 14 can only be implemented in slave
mode with /SS enabled.
Fig. 13 SPI Mode with /SS Disable
24 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Fig. 14 SPI Mode with /SS Enable
4.5.6 Software Application of SPI
Example for SPI:
For Master
ORG 0X0
SETTING:
CLRA
IOW 0X05
;Set Port5 output
IOW 0X06
;Set Port6 output
MOV 0X05,A
MOV A,@0B11001111
;Set prescaler for WDT
CONTW
MOV A,@0B00010001
;Disable wakeup function
IOW 0X0E
MOV A,@0B00000000
;Disable interrupt
IOW 0X0F
MOV A,@0x07
;SDI input and SDO, SCK output
IOW 0x09
MOV A,@0B10000000
;Clear RBF and RBFIF flag
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 25
EM78P451S
8-Bit Microcontroller with OTP ROM
MOV 0x0C,A
MOV A,@0B11100000
;Select clock edge and enable SPI
MOV 0X0D,A
START:
WDTC
BC 0X0C,1
;Clear RBFIF flag
MOV A,@0XFF
MOV 0X05,A
;Show a signal at Port5
MOV 0X0A,A
;Move FF at read buffer
MOV A,@0XAA
;Move AA at write buffer
MOV 0X0B,A
BS 0X0D,4
;Start to shift SPI data
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BC 0X03,2
CALL DELAY
;To catch the data from slaver
MOV A,0X0A
XOR A,@0X5A
;Compare the data from slaver
JBS 0X03,2
JMP START
FLAG:
MOV A,@0X55
;Show the signal when receiving correct data from slaver
MOV 0X05,A
CALL DELAY
JMP START
DELAY:
; (user’s program)
EOP
ORG 0XFFF
JMP SETTING
26 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
For Slaver
ORG 0X0
INITI:
JMP INIT
ORG 0X2
INTERRUPT:
;Interrupt address
MOV A,@0X55
MOV 0X06,A
;Show a signal at Port 6 when entering interrupt
MOV A,@0B11100110
;Enable SPI, /SS disabled
MOV 0X0D,A
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
MOV A,@0X00
as 00
;Move 00 to write buffer in order to keep master’s read buffer
MOV 0X0B,A
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BS 0X0D,4
;Keep SSE at 1 to wait for SCK signal in order to shift data
BC 0X03,2
MOV A,0X0A
MOV 0X06,A
;Read master’s data from read buffer
XOR A,@0XAA
;Check pass signal from read buffer
JBS 0X03,2
JMP $-6
JMP SPI
ORG 0X30
INIT:
CLRA
IOW 0X05
IOW 0X06
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 27
EM78P451S
8-Bit Microcontroller with OTP ROM
MOV 0x05,A
MOV 0X06,A
MOV A,@0XFF
IOW 0X08
MOV A,@0B11001111
;Set prescaler for WDT
CONTW
MOV A,@0B00010001
;Disable wakeup function
IOW 0X0E
MOV A,@0B00000010
;Enable external interrupt
IOW 0XF
ENI
MOV A,@0B00110111
IOW 0x09
BC 0X3F,1
;Clear RBFIF flag
NOP
JBS 0X3F,1
;Polling loop for checking interrupt occurence
JMP $-2
JMP INTERRUPT
SPI:
BS 0X0D,4
;Keep SSE enabled as long as possible
WDTC
MOV A,@0X0F
;Show a signal when entering SPI loop
MOV 0X06,A
JBC 0X08,1
;Choose P81 as a signal button
JMP SPI
MOV A,@0X5A
;Move 5A into write buffer when P81 button is pushed
MOV 0X0B,A
NOP
JBC 0X0D,4
;Polling loop for checking SPI transmission completed
JMP $-2
BS 0XD,4
28 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
NOP
NOP
MOV A,@0XF0
;Display at Port6 when P81 button is pushed
MOV 0X06,A
MOV A,@0X00
;Send a signal to master to prevent infinite loop
MOV 0X0B,A
NOP
JBC 0X0D,4
JMP $-2
BS 0X0D,4
BS 0x0C,7
BC 0x0C,1
NOP
JMP SPI
DELAY:
; (user’s program)
EOP
ORG 0XFFF
JMP INITI
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 29
EM78P451S
8-Bit Microcontroller with OTP ROM
4.6 Timer 1
Clock output
4.6.1 Overview
OSC/4
Sets TMR1IF
Timer1(TMR1) is an eight-bit clock counter with a programmable prescaler. It is
designed for the SPI module as a baud rate clock generator. TMR1 can be read and
Comarator
written and cleared on any reset
conditions. If employed, it can be turned down for
EQ
Prescaler
power saving by setting TMR1EN bit [T1CON<2>]
1:1toto0.1:16
increase
OSC/2
reset
4.6.2 PWP
FunctionTMR1
description
Fig. 15 shows TIMER1 block diagram. Each signal and block is described as follows:
Fig. 15 TIMER1 Block Diagram
OSC/4:Input clock.
Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P02
(T1CON<1, 0>). It is cleared when a value is written to TMR1 or T1CON, and
during any kind of reset as well.
PWP: Pulse width preset register. The desired width of baud clock is written in
advance.
TMR1: Timer 1 register. TMR1 increases until it matches with PWP, and then
resets to 0. If it is chosen optionally in the SPI mode, its output is fed as a shifting
clock.
Comparator: To change the output status while a match occurs. The TMR1IF flag
will be set at the same time.
4.6.3 Programmed the related registers
The related registers of the defining TMR1 operation are shown in Table 4 and Table 5
Table 4 Related Control Registers of the TMR1
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0x0C
SPIS/RC
0
0
0
TM1IF
0x0F
INTC/IOCF
0
0
0
0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
0X0E
TMR1/RE
TMR17
TMR16
TMR15
0x0F
PWP/RF
PWP7
PWP6
PWP5
0x0C
T1CON/IOCC
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
OD3
OD4
RBFIF
RBF
TM1IE
SPIIE
EXIE
TCIE
Bit 3
Bit 2
Bit 1
Bit 0
TMR14
TMR13
TMR12
TMR11
TMR10
PWP4
PWP3
PWP2
PWP1
PWP0
0
0
TM1E
TM1P1
TM1P0
Table 5 Related Status/Data Registers ofTMR1
30 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
TMR1: Timer1 Register
TMR17~TMR10 is bit set of Timer1 register and it increases until the value
matches PWP and then it reset to 0.
PWP: Pulse Width Preset Register
PWP7~PWP0 is bit set of pulse width preset for the desired width of baud clock in
advance.
T1CON: Timer1 Control Register
Bit 2 (TM1E): Timer1 enable bit
Bit 1 (TM1P1) and Bit 0 (TM1P): Timer1 prescaler for FSCO
TM1P1
TM1P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
4.7 RESET and Wake-up
A RESET is initiated by
(1) Power on reset, or
(2) /RESET pin input “low”, or
(3) WDT timeout. (if enabled)
VDD
D
Q
CLK
CLR
Oscillator
CLK
Poweron Reset
Voltage
Detector
WDTE
WDT timeout
WDT
Setup
Time
Reset
Fig. 16 Block Diagram of Reset
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 31
EM78P451S
8-Bit Microcontroller with OTP ROM
EM78P451S POR voltage range is 1.2V~2.0V. Under customer application, when
power is OFF, Vdd must drop to below 1.2V and remains OFF for 10us before power
can be switched ON again. This way, the EM78P451S will reset and work normally.
The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or
less). However, under most cases where critical applications are involved, extra
devices are required to assist in solving the power-up problem.
The device is kept in a RESET condition for a period of approx. 18ms2 (one oscillator
start-up timer period) after the reset is detected and Fig.16 is the block diagram of
reset. Once the RESET occurs, the following functions are performed.
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "1".
When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
All I/O port pins are configured as input mode (high-impedance state).
The Watchdog timer and prescaler are cleared.
The Watchdog timer is enabled if Code Option bit ENWDT is "1".
The CONT register is set to all "1" except bit 6 (INT flag).
Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to "1".
Bits 0 of R3F and bits 0 of IOCF registers are cleared.
The sleep mode (power down) is achieved by executing the SLEP instruction (named
as SLEEP1 MODE). While entering sleep mode, the WDT (if enabled) is cleared but
keeps on running. The controller is awakened by WDT timeout (if enabled), and it will
cause the controller to reset. The T and P flags of R3 are used to determine the source
of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78P451S has another sleep mode (caused
by clearing "SLPC" bit of IOCE register, designated as SLEEP2 MODE). In the
SLEEP2 MODE, the controller can be awakened by(a) Any one of the wake-up pins is set to “0.” (refer to Fig.17). Upon waking, the
controller will continue to execute the program in-line. In this case, before entering
SLEEP2 MODE, the wake-up function of the trigger sources (P60~P67, P74~P75,
and P90~P91)should be selected (e.g. input pin) and enabled (e.g. pull-high,
wake-up control). One caution should be noted is that after waking up, the WDT is
enabled if Code Option bit ENWDT is "1". The WDT operation (to be enabled or
disabled) should be appropriately controlled by software after waking up.
(b) WDT time-out (if enabled). or external reset input on /RESET pin will trigger a
controller reset..
2
NOTE: Vdd = 5V, set up time period = 16.20ms ± 30%
Vdd = 3V, set up time period = 18.0ms ±30%
32 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Table 6 Usage of Sleep and Sleep2 Mode
Usage of Sleep and Sleep2 Mode
SLEEP2
SLEEP
(a) Before SLEEP
(a) Before SLEEP
1. Set Port6 or P74 or P75 Input
2. Enable Pull-High and set WDT prescaler over
1:1 (Set CONT.7 and CONT.3 ~ CONT.0)
3. Enable Wake-up (Set IOCB or IOCE.0)
1. Execute SLEP instruction
4. Execute Seep2 (Set IOCE.4)
(b) After Wake-up
(b) After Wake-up
1. Next instruction
1. Reset
2. Disable Wake-up
3. Disable WDT (Set IOCE.5)
If Port6 Input Status Changed Wake-up is used to wake-up the EM78P451S (Case [a] above), the
following instructions must be executed before entering SLEEP2 mode:
MOV
IOW
MOV
CONTW
MOV
IOW
A, @11111111b
IOC6
A, @0xxx1010b
; Set Port6 input
; Set Port6 pull-high, WDT prescaler, prescaler must set over 1:1
A, @xx00xxx0b
IOCE
; Enable Port6 wake-up function, Enable SLEEP2
A, @ xx01xxx1b
IOCE
; Disable Port6 wake-up function; Disable WDT
After Wake-up
NOP
MOV
IOW
After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabled
operation after waking up from SLEEP2 mode should be appropriately defined in the software.
To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt enters into interrupt
vector or is used to wake-up the MCU, the WDT prescaler must be set above the 1:1 ratio.
Table 7 The Summary of the Initialized Values for Registers
Address
N/A
N/A
N/A
N/A
Name
IOC5
IOC6
IOC7
IOC8
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
C57
1
1
C56
1
1
C55
1
1
C54
1
1
C53
1
1
C52
1
1
C51
1
1
C50
1
1
P
P
P
P
P
P
P
P
C67
1
1
C66
1
1
C65
1
1
C64
1
1
C63
1
1
C62
1
1
C61
1
1
C60
1
1
P
P
P
P
P
P
P
P
C77
1
1
C76
1
1
C75
1
1
C74
1
1
C73
1
1
C72
1
1
C71
1
1
C70
1
1
P
P
P
P
P
P
P
P
C87
1
1
C86
1
1
C85
1
1
C84
1
1
C83
1
1
C82
1
1
C81
1
1
C80
1
1
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 33
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
N/A
Name
IOC9
Reset Type
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
N/A
0x00
0x01
0x02
0x03
CONT
R0(IAR)
R1(TCC)
R2(PC)
R3(SR)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0x04
0x05
0x06
0x07
0x08
34 •
R4(RSR)
R5(P5)
R6(P6)
R7(P7)
R8(P8)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P
P
P
P
P
P
P
P
C97
1
1
C96
1
1
C95
1
1
C94
1
1
C93
1
1
C92
1
1
C91
1
1
C90
1
1
P
P
P
P
P
P
P
P
/INT
-
-
PAB
0
P
1
1
1
1
1
1
PSR
2
1
1
PSR
1
1
1
PSR
0
1
1
P
P
P
P
P
P
P
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
**P
**P
**P
**P
**P
**P
**P
**P
GP
0
0
PS1
0
0
PS0
0
0
T
t
t
P
t
t
Z
U
P
DC
U
P
C
U
P
P
P
P
t
t
P
P
P
RSR.
1
0
0
RSR.
0
0
0
-
-
-
-
-
-
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
P57
U
P
P56
U
P
P55
U
P
P54
U
P
P53
U
P
P52
U
P
P51
U
P
P50
U
P
P
P
P
P
P
P
P
P
P67
U
P
P66
U
P
P65
U
P
P64
U
P
P63
U
P
P62
U
P
P61
U
P
P60
U
P
P
P
P
P
P
P
P
P
P77
U
P
P76
U
P
P75
U
P
P74
U
P
P73
U
P
P72
U
P
P71
U
P
P70
U
P
P
P
P
P
P
P
P
P
P87
U
P
P86
U
P
P85
U
P
P84
U
P
P83
U
P
P82
U
P
P81
U
P
P80
U
P
/PHE
N
1
1
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
0x09
Name
Reset Type
R9(P9)
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit 7
Bit Name
0x0A
RA(SPIRB)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0x0B
RB(SPIWB)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0x0C
RC(SPIS)
Power-On
/RESET and WDT
Wake-Up from Pin
Change
RD(SPIC)
RE(TMR1)
0x3F
0x0C
0x0D
RF(PWP)
R3F(ISR)
IOCC
IOCD
Bit 3
Bit 2
Bit 1
Bit 0
P
P
P
P
P
P
P
P
P97
U
P
P96
U
P
P95
U
P
P94
U
P
P93
U
P
P92
U
P
P91
U
P
P90
U
P
P
P
P
P
P
P
P
P
SRB
7
U
P
SRB
6
U
P
SRB
5
U
P
SRB
4
U
P
SRB
3
U
P
SRB
2
U
P
SRB
1
U
P
SRB
0
U
P
P
P
P
P
P
P
P
P
SWB
7
U
P
SWB
6
U
P
SWB
5
U
P
SWB
4
U
P
SWB
3
U
P
SWB
2
U
P
SWB
1
U
P
SWB
0
U
P
P
P
P
P
P
P
P
P
ENS
DO
0
0
OBD
C
0
0
IBDC
TIIF
OD3
OD4
0
0
0
0
0
0
0
0
RBFI
F
0
0
P
P
P
P
P
P
P
P
CES
SPIE
SRO
0
0
0
0
SBR
S1
0
0
SBR
S0
0
0
P
RBF
0
0
0
0
0
0
P
P
P
P
P
P
P
TMR
17
0
0
TMR
16
0
0
TMR
15
0
0
TMR
14
0
0
TMR
13
0
0
TMR
12
0
0
TMR
11
0
0
TMR
10
0
0
P
P
P
P
P
P
P
P
PWP
7
1
1
PWP
6
1
1
PWP
5
1
1
PWP
4
1
1
PWP
3
1
1
PWP
2
1
1
PWP
1
1
1
PWP
0
1
1
P
P
P
P
P
P
P
P
U
U
U
U
U
U
U
U
T1IF
0
0
SPIIF
0
0
EXIF
0
0
TCIF
0
0
U
U
U
U
P
P
P
P
Bit Name
-
-
-
-
-
T1E
T1P1
T1P0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit Name
S7
-
-
-
/PU9
/PU8
/PU6
/PU5
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0x0F
Bit 4
SBR
S2
0
0
Bit Name
0x0E
Bit 5
SPIS
E
0
0
Bit Name
0x0D
Bit 6
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
-
• 35
EM78P451S
8-Bit Microcontroller with OTP ROM
Address
0x0E
0x0F
0x10~0x3E
Name
IOCE
IOCF
GPR
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
Bit Name
-
ODE
WTE
SLP
C
ROC
-
-
/WU
E
Power-On
U
0
1
1
0
U
U
1
/RESET and WDT
Wake-Up from Pin
Change
U
0
1
1
0
U
U
1
U
P
1
1
P
U
U
P
Bit Name
-
-
-
-
T1IE
SPII
E
EXIE
TCIE
Power-On
U
U
U
U
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
U
U
U
U
0
0
0
0
U
U
U
U
P
P
P
P
Bit Name
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
** To execute the next instruction after the ”SLPC” bit status of IOCE register being on
high-to-low transition.
X: NOTE
used. U: Unknown or don’t care. -: Not defined P: Previous value before reset.
t: Check Table 7
The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition,
2. Watchdog timer time-out.
The values of T and P, listed in Table 7 are used to check how the processor wakes up.
Table 8 shows the events that may affect the status of T and P.
Table 8 The Values of RST, T and P After RESET
Reset Type
T
P
Power on
1
1
WDT during Operating mode
0
P
WDT wake-up during SLEEP1 mode
0
0
WDT wake-up during SLEEP2 mode
0
P
Wake-Up on pin change during SLEEP2 mode
P
P
* P: Previous value before reset
36 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Table 9 The Status of RST, T and P Being Affected by Events
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-Up on pin change during SLEEP2 mode
P
P
* P: Previous value before reset
4.8 Interrupt
The EM78P451S has the following interrupts.
1. /TCC overflow interrupt
2. External interrupt (/INT)
3. Serial Peripheral Interface (SPI) transmission completed interrupt.
4. Timer1 comparator completed interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF
is the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (if enabled) is generated, will
cause the next instruction to be fetched from address 001H. Once in the interrupt
service routine the source of the interrupt can be determined by polling the flag bits in
the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask
bit or the execution of ENI instruction. Note that reading R3F will obtain the output of
logic AND of R3F and IOCF (refer to Fig. 17). The RETI instruction exits interrupt
routine and enables the global interrupt (execution of ENI instruction).
When an interrupt is generated by INT instruction (if enabled), it causes the next
instruction to be fetched from address 002H.
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 37
EM78P451S
8-Bit Microcontroller with OTP ROM
IRQn
PQ
R
CLK C
L Q
R3F
D
/IRQn
interrupt
IRQm
RFRD
ENI/DISI
Q P D
R
C CLK
Q L
IOD
IOCFWR
IOCF
RESET
IOCFRD
RFWR
Fig. 17 Interrupt Input Circuit
4.9 Oscillator
4.9.1 Oscillator Modes
The EM78P451S can operate in four different oscillator modes. There are high XTAL
(HXT) oscillator mode, low XTAL (LXT) oscillator mode, External RC oscillator mode
(ERC), and Internal C、External R oscillator modes. User can select one of them by
programming MS, RCT, HLF and HLP in the Code Option Register. Table 9 depicts
how these three modes are defined.
Table 10 Oscillator Modes by MS, IRC, RCT.
Mode
MS
RCT
HLF
HLP
High XTAL Oscillator
1
X
1
X
Low XTAL Oscillator
External RC Oscillator
1
0
X
1
0
X
0
X
External R and Internal C Oscillator
0
0
X
X
<Note> X: Don’t care
4.9.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P451S can be driven by an external clock signal through the OSCI pin as shown
in Fig 18 below. In the most applications, pin OSCI and pin OSCO is connected with a
crystal or ceramic resonator to generate oscillation. Fig 19 depicts such circuit. Table
10 provides the recommended values of C1 and C2. Since each resonator has its own
attribute, user should refer to its specification for appropriate values of C1 and C2. RS,
a serial resistor may be necessary for AT strip cut crystal or low frequency mode.
38 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
OSCI
Ext. Clock
OSCO
EM78P451S
Fig. 18 Circuit for External Clock Input
C1
OSCI
EM 78P451S
XTAL
OSCO
RS
C2
Fig. 19 Circuit for Crystal/Resonator
Table 11 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators
Oscillator Type
Ceramic Resonator
Frequency Mode
Frequency
C1 (pF)
C2 (pF)
455 KHz
10~150
10~150
1.0 MHz
40~80
40~80
2.0 MHz
20~40
20~40
HXT
4.0 MHz
10~30
10~30
32.768 KHz
25
15
100 KHz
25
25
200 KHz
25
25
455 KHz
20~40
20~150
1.0 MHz
2.0 MHz
15~30
15
15~30
15
4.0 MHz
15
15
LXT
Crystal Oscillator
HXT
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 39
EM78P451S
8-Bit Microcontroller with OTP ROM
4.9.3 RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Fig 22 & Fig 23) offers a lot of cost savings. Nevertheless, it should be noted
that the frequency of the RC oscillator is influenced by the supply voltage, the values of
the resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the
manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 M ohm. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator becomes unstable
because the NMOS cannot discharge the current of the capacitance correctly.
Based on the reasons above, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is layout, will affect the system frequency.
Vcc
Rext
OSCI
Cext
EM 78P451S
Fig. 20 Circuit for External RC Oscillator Mode
Vcc
Rext
OSCI
EM 78P451S
Fig. 21 Circuit for External R, Internal C Oscillator Mode
40 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Calibrate frequency of External RC oscillator (For reference only)
C ext
R ext
Fosc @5.0V,25℃
20pF
3.3K
5.1K
10K
100K
3.4MHz
2.2MHz
1.3MHz
144KHz
3.3K
1.2MHz
5.1K
10K
100K
3.3K
5.1K
10K
100K
935KHz
420KHz
45KHz
550KHz
360KHz
190KHz
28KHz
100pF
300pF
Internal C, external R Table (For reference only)
External R (Ohm)
Fosc @5.0V, 25℃ (Hz)
10K
12M
15K
7.7M
20K
5.7M
30K
3.65M
51K
2.24M
100K
1.14M
150K
749K
200K
559K
510K
214K
2M
56K
3.3M
32.8K
4.10 Code Option Register
WORD 0
12
MS
11
10
ENWD
CLKS
T
9
8
7
6
5
4
3
2
1
0
PTB
HLF
RCT
HLP
DEL1
DEL0
REN
N/A
N/A
N/A
Bit 12 (MS): Oscillator type selection.
0: RC type
1: XTAL type
Bit 11 (ENWDT): Watchdog Timer enabled.
0: Enable
1: Disable
Bit 10 (CLKS): Clocks of each instruction cycle.
0: Two clocks
1: Four clocks
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 41
EM78P451S
8-Bit Microcontroller with OTP ROM
Bit 9 (PTB): Protect bit.
0: Protect enabled
1: Protect disabled
Bit 8 (HLF): XTAL frequency selection.
0: Low frequency (32.768KHz)
1: High frequency
This bit is useful only when Bit 12 (MS) is 1. When MS is 0, HLF must be 0.
Bit 7 (RCT): Resistor Capacitor.
0: internal RC
1: external RC
Bit 6 (HLP): Power consumption selection.
0: Low power
1: High power
Bit 5 ~ Bit 4: DEL1 and DEL0 (SDI) input delay time options.
DEL 1
DEL 0
Delay time
1
0
1
1
1
0
0 ns
50 ns
100 ns
Bit3~0 (REN): reset pin enable bit
0: enable, P70/reset=>reset pin
1: disable, P70/reset=> P70
WORD 1 ( user’s ID code)
12
11
10
9
8
7
6
5
4
3
2
1
0
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
4.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. All instructions are executed within one single instruction cycle
(consisting of 2 oscillator periods), unless the program counter is changed by(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions
that write to R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ⋅⋅⋅⋅).
(b) execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ,
DJZA) which were tested to be true.
Under these cases, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
42 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the
registers (including operational registers and general purpose registers) is to be utilized
by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b"
represents a bit field designator that selects the value for the bit located in the register
"R" and affects operation. "k" represents an 8 or 10-bit constant or literal value.
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0 0000 0000 0000
0000
NOP
No Operation
None
0 0000 0000 0001
0001
DAA
Decimal Adjust A
C
0 0000 0000 0010
0002
CONTW
A → CONT
None
0 0000 0000 0011
0003
SLEP
0 → WDT, Stop oscillator
T,P
0 0000 0000 0100
0004
WDTC
0 → WDT
T,P
0 0000 0000 rrrr
000r
IOW R
A → IOCR
None <Note1>
0 0000 0001 0000
0010
ENI
Enable Interrupt
None
0 0000 0001 0001
0011
DISI
Disable Interrupt
None
0 0000 0001 0010
0012
RET
None
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0014
CONTR
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
0 0000 0001 rrrr
001r
IOR R
None <Note1>
0 0000 0010 0000
0020
TBL
0 0000 01rr rrrr
00rr
MOV R,A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A→R
0 0000 1000 0000
0080
CLRA
0→A
Z
0 0000 11rr rrrr
00rr
CLR R
0→R
Z
0 0001 00rr rrrr
01rr
SUB A,R
R-A → A
Z,C,DC
0 0001 01rr rrrr
01rr
SUB R,A
R-A → R
Z,C,DC
0 0001 10rr rrrr
01rr
DECA R
R-1 → A
Z
0 0001 11rr rrrr
01rr
DEC R
R-1 → R
Z
0 0010 00rr rrrr
02rr
OR A,R
A ∨ VR → A
Z
0 0010 01rr rrrr
02rr
OR R,A
A ∨ VR → R
Z
0 0010 10rr rrrr
02rr
AND A,R
A&R→A
Z
0 0010 11rr rrrr
02rr
AND R,A
A&R→R
Z
0 0011 00rr rrrr
03rr
XOR A,R
A⊕R→A
Z
0 0011 01rr rrrr
03rr
XOR R,A
A⊕R→R
Z
0 0011 10rr rrrr
03rr
ADD A,R
A+R→A
Z,C,DC
0 0011 11rr rrrr
03rr
ADD R,A
A+R→R
Z,C,DC
0 0100 00rr rrrr
04rr
MOV A,R
R→A
Z
0 0100 01rr rrrr
04rr
MOV R,R
R→R
Z
0 0100 10rr rrrr
04rr
COMA R
/R → A
Z
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
None
None
Z,C,DC
None
• 43
EM78P451S
8-Bit Microcontroller with OTP ROM
INSTRUCTION BINARY
HEX
MNEMONIC
OPERATION
STATUS AFFECTED
0 0100 11rr rrrr
04rr
COM R
/R → R
Z
0 0101 00rr rrrr
05rr
INCA R
R+1 → A
Z
0 0101 01rr rrrr
05rr
INC R
R+1 → R
Z
0 0101 10rr rrrr
05rr
DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr
05rr
DJZ R
None
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0 0111 01rr rrrr
07rr
SWAP R
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
0 0111 10rr rrrr
07rr
JZA R
R+1 → A, skip if zero
None
0 0111 11rr rrrr
07rr
JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr
0xxx
BC R,b
0 → R(b)
None <Note2>
0 101b bbrr rrrr
0xxx
BS R,b
1 → R(b)
None <Note3>
0 110b bbrr rrrr
0xxx
JBC R,b
if R(b)=0, skip
None
0 111b bbrr rrrr
0xxx
JBS R,b
if R(b)=1, skip
None
1 00kk kkkk kkkk
1kkk
CALL k
C
C
C
C
None
None
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
None
k→A
None
None
1 01kk kkkk kkkk
1kkk
JMP k
1 1000 kkkk kkkk
18kk
MOV A,k
1 1001 kkkk kkkk
19kk
OR A,k
A∨k→A
Z
1 1010 kkkk kkkk
1Akk
AND A,k
A&k→A
Z
1 1011 kkkk kkkk
1Bkk
XOR A,k
A⊕k→A
Z
1 1100 kkkk kkkk
1Ckk
RETL k
k → A, [Top of Stack] → PC
None
1 1101 kkkk kkkk
1Dkk
SUB A,k
k-A → A
Z,C,DC
1 1110 0000 0010
1E02
INT
PC+1 → [SP], 002H → PC
None
1 1111 kkkk kkkk
1Fkk
ADD A,k
k+A → A
Z,C,DC
NOTE
This instruction is applicable to IOC5 ~ IOC9, IOCD~IOCF only.
This instruction is not recommended for RF operation.
This instruction cannot operate on R3F.
44 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
4.12 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 45
EM78P451S
8-Bit Microcontroller with OTP ROM
5
ABSOLUTE MAXIMUM RATING
Items
Rating
Temperature under bias
0°C
to
70°C
Storage temperature
-65°C
to
150°C
Input voltage
-0.3V
to
+6.0V
Output voltage
-0.3V
to
+6.0V
DC
to
20MHz
Operating Frequency (2clk)
6
ELECTRICAL CHARACTERISTICS
6.1 DC Characteristic
(Ta=25°C, VDD=5V±5%, VSS=0V)
Symbol
FXT
FRC
IIL
VIH1
VIL1
VIHX1
VILX1
VIHT1
VILT1
VIH2
VIL2
VIHX2
VILX2
VOH1
VOH2
46 •
Parameter
XTAL VDD to 2.3V
XTAL VDD to 3V
XTAL VDD to 5V
RC VDD to 2.3V
RC VDD to 3V
RC VDD to 5V
Input Leakage Current
Input High Voltage
VDD=5V)
Input Low Voltage
(VDD=5V)
Clock Input High Voltage
(VDD=5V)
Clock Input Low Voltage
(VDD=5V)
Input high threshold voltage
(Schmitt trigger)
Input low threshold voltage
(Schmitt trigger)
Input High
Voltage(VDD=3V)
Input Low Voltage
(VDD=3V)
Clock Input High Voltage
(VDD=3V)
Clock Input Low Voltage
(VDD=3V)
Output High Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97,)
Output High Voltage
(P70~P72)
Condition
Min
Two clocks
Two clocks
Typ
Max
Unit
DC
DC
4
8
MHz
DC
DC
DC
DC
20
4
4
4
±1
VIN = VDD, VSS
2.0
2.5
1.0
2.0
0.8
1.5
1.5
0.6
2.4
2
V
V
OSCI
S7=1(IOCD Register bit7),
IOH = -9.0mA
S7=0(IOCD Register bit7),
IOH = -12.0mA
V
V
0.4
IOH = -12.0mA
V
V
P70/RESET pin
OSCI
V
V
OSCI
P70/RESET pin
µA
V
0.8
OSCI
MHz
V
V
2.4
V
2.4
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
Symbol
VOH3
VOL1
VOL2
VOL3
VOL4
IPH
IPH2
IPH3
Parameter
Output High Voltage
(P93/SDO,P94/SCK)
Output Low Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97))
Output Low Voltage
(P70~P72)
Output Low Voltage
(P93/SDO, P94/SCK)
Output Low Voltage
(P74~P77)
Pull-high current
Pull-high current
(P74,P75)
Pull high current
(P70/RESET)
ISB
Power down current
ICC
Operating supply current
Condition
Min
IOH = -12.0mA
Typ
Max
2.4
V
IOL =12.0mA
0.4
S7=1(IOCD Register bit7),
IOH = 9.0mA
S7=0(IOCD Register bit7),
IOH = 12.0mA
0.4
V
0.4
0.4
IOL = 15.0mA
0.4
-50
Pull-high active, input pin at VSS
Pull-high active, input pin at VSS
V
0.8
IOL = 12.0mA
Pull-high active, input pin at VSS
Unit
-100
-240
1
-16
V
µA
mA
-22
All input and I/O pin at VDD,
output pin floating, WDT enabled
/RESET="High",
Fosc=1.84324MHz (CK2="0"),
output pin floating
-29
µA
10
µA
3
mA
6.2 AC Characteristic
(Ta=0°C~70°C, VDD=5V±5%, VSS=0V)
Symbol
Dclk
Tins
Parameter
Conditions
Input CLK duty cycle
Instruction cycle time
(CK2="0")
RC Type
Min
Typ
Max
Unit
45
50
55
%
DC
ns
500
Ttcc
TCC input period
(Tins+20)/N*
ns
Twdt
Watchdog timer period
Ta=25°C
18
ms
Tdrh
Device reset hold period
Ta=25°C
183
ms
N= selected prescaler ratio.
3
NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%
Vdd = 3V, set up time period = 18.0ms ± 30%
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 47
EM78P451S
8-Bit Microcontroller with OTP ROM
7
Application Circuit
EM78P451S
48 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
EM78P451S
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Types
OTP MCU
Package Type
Pin Count
Package Size
EM78P451SP
DIP
40
600 mil
EM78P451SWM
SOP
40
450 mil
EM78P451SAQ
QFP
44
B Package Information
40-Lead Plastic Dual in line (PDIP) — 600 mil
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
• 49
EM78P451S
8-Bit Microcontroller with OTP ROM
44--Lead Quad flat package (QFP)
50 •
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
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