Cypress CY2DL1510AZIT 1:10 differential lvds fanout buffer Datasheet

CY2DL1510
1:10 Differential LVDS Fanout Buffer
Features
Functional Description
■
Low-voltage differential signal (LVDS) input with on-chip 100-Ω
input termination resistor
■
Ten differential LVDS outputs
■
40-ps maximum output-to-output skew
■
600-ps maximum propagation delay
■
0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
The CY2DL1510 is an ultra-low noise, low-skew,
low-propagation delay 1:10 differential LVDS fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The on-chip 100-Ω input termination
resistor reduces board component count, while the synchronous
clock enable function ensures glitch-free output transitions
during enable and disable periods. The device has a fully
differential internal architecture that is optimized to achieve
low-additive jitter and low-skew at operating frequencies of up to
1.5 GHz.
■
Up to 1.5-GHz operation
■
Synchronous clock enable function
■
32-pin thin quad flat pack (TQFP) package
■
2.5-V or 3.3-V operating voltage[1]
■
Commercial and industrial operating temperature range
Logic Block Diagram
Q0
Q0#
Q1
Q1#
VDD
Q2
Q2#
VSS
Q3
Q3#
IN
IN#
Q4
Q4#
100
Q5
Q5#
VDD
Q
100k
CLK_EN
Q6
Q6#
D
Q7
Q7#
VBB
Q8
Q8#
Q9
Q9#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-54863 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 25, 2011
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CY2DL1510
Contents
Pinouts .............................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions....................................................... 4
DC Electrical Specifications ............................................ 5
AC Electrical Specifications ............................................ 6
Ordering Information...................................................... 10
Ordering Code Definition........................................... 10
Package Dimension........................................................ 11
Document Number: 001-54863 Rev. *H
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY2DL1510
Pinouts
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Figure 1. Pin Diagram - CY2DL1510
24
23
22
21
20
19
18
17
VDD
25
16
VDD
Q2#
26
15
Q7
Q2
27
14
Q7#
Q1#
28
13
Q8
Q1
29
12
Q8#
Q0#
30
11
Q9
Q0
31
10
Q9#
VDD
32
9
VDD
4
5
6
7
8
VBB
IN
IN#
VSS
CLK_EN
3
NC
2
NC
1
VDD
CY2DL1510
Table 1. Pin Definitions
Pin No.
Pin Name
Pin Type
Description
1, 9, 16, 25, 32
VDD
Power
Power supply
2
CLK_EN
Input
Synchronous clock enable. Low-voltage complementary metal oxide
semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When CLK_EN = Low, Q(0:9) outputs are held low and Q(0:9)# outputs are
held high
Output
LVDS reference voltage output
3, 4
NC
5
VBB
No connection
6
IN
Input
LVDS input clock
7
IN#
Input
LVDS complementary input clock
8
VSS
Power
Ground
10,12,14,17,19,21, Q(0:9)#
23,26,28,30
Output
LVDS complementary output clocks
11,13,15,18,20,22, Q(0:9)
24,27,29,31
Output
LVDS output clocks
Document Number: 001-54863 Rev. *H
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CY2DL1510
Absolute Maximum Ratings
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
Nonfunctional
Condition
–0.5
4.6
V
VIN[2]
Input voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
VOUT[2]
DC output or I/O Voltage, relative to VSS
Nonfunctional
–0.5
lesser of 4.0
or VDD + 0.4
V
TS
Storage temperature
Nonfunctional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD) protection
(Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
Meets or exceeds JEDEC Spec
JESD78B IC latch up test
At 1/8 in.
V–0
3
Operating Conditions
Parameter
Description
VDD
Supply voltage
TA
Ambient operating temperature
tPU
Power ramp time
Min
Max
Unit
2.5-V supply
Condition
2.375
2.625
V
3.3-V supply
3.135
3.465
V
Commercial
0
70
°C
Industrial
–40
85
°C
Power-up time for VDD to reach
minimum specified voltage (power
ramp must be monotonic.)
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-54863 Rev. *H
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CY2DL1510
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
All LVDS outputs terminated with 100 Ω
load[3, 4]
Min
Max
Unit
–
125
mA
IDD
Operating supply current
VIH1
Input high Voltage, LVDS input clocks,
IN and IN#
–
VDD + 0.3
V
VIL1
Input low voltage, LVDS input clocks,
IN and IN#
–0.3
–
V
VIH2
Input high voltage, CLK_EN
VDD = 3.3 V
2.0
VDD + 0.3
V
VIL2
Input low voltage, CLK_EN
VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage, CLK_EN
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage, CLK_EN
VDD = 2.5 V
–0.3
0.7
V
VID[5]
Input differential amplitude
See Figure 3 on page 7
0.4
0.8
V
VICM
Input common mode voltage
See Figure 3 on page 7
0.5
VDD – 0.2
V
IIH
Input high current, All inputs
Input = VDD[6]
–
150
μA
IIL
Input low current, All inputs
Input = VSS[6]
–150
–
μA
VPP
LVDS differential output voltage peak to
peak, single-ended
VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs[3, 7]
250
470
mV
ΔVOCM
Change in VOCM between complementary VDD = 3.3 V or 2.5 V,
output states
RTERM = 100 Ω between Q and Q# pairs[3, 7]
–
50
mV
VBB
Output reference voltage
1.125
1.375
V
RTERM
On-chip differential input termination
resistor
80
120
Ω
RP
Internal pull-up resistance,
LVCMOS logic input
CLK_EN pin
60
140
kΩ
CIN
Input capacitance
Measured at 10 MHz per pin
–
3
pF
0 to 150 μA output current
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
Document Number: 001-54863 Rev. *H
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CY2DL1510
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Typ
Max
Unit
DC
–
1.5
GHz
–
1.5
GHz
–
600
ps
–
52
%
–
–
40
ps
–
–
150
ps
FIN
Input frequency
FOUT
Output frequency
FOUT = FIN
DC
tPD[10]
Propagation delay input pair to output
pair
Input rise/fall time < 1.5 ns
(20% to 80%)
–
tODC[11]
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48
tSK1[12]
Output-to-output skew
Any output to any output, with
same load conditions at DUT
tSK1 D[12]
Device-to-device output skew
Any output to any output between
two or more devices. Devices
must have the same input and
have the same output load.
PNADD
Additive RMS phase noise
156.25-MHz input
Rise/fall time < 150 ps (20% to 80%)
VID > 400 mV
Offset = 1 kHz
–
–
–120
dBc/Hz
Offset = 10 kHz
–
–
–135
dBc/Hz
Offset = 100 kHz
–
–
–135
dBc/Hz
Offset = 1 MHz
–
–
–150
dBc/Hz
Offset = 10 MHz
–
–
–154
dBc/Hz
Offset = 20 MHz
–
–
–155
dBc/Hz
tJIT[13]
Additive RMS phase jitter (Random)
156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
–
–
0.11
ps
tR,tF[14]
Output rise/fall time, single-ended
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz
–
–
300
ps
tSOD
Time from clock edge to outputs
disabled
Synchronous clock enable
(CLK_EN) switched low
–
–
700
ps
tSOE
Time from clock edge to outputs
enabled
Synchronous clock enable
(CLK_EN) switched high
–
–
700
ps
Notes
8. Refer to Figure 2 on page 7.
9. Refer to Figure 4 on page 7.
10. Refer to Figure 5 on page 7.
11. Refer to Figure 6 on page 7.
12. Refer to Figure 7 on page 8.
13. Refer to Figure 8 on page 8.
14. Refer to Figure 9 on page 8.
Document Number: 001-54863 Rev. *H
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CY2DL1510
Figure 2. LVDS Output Termination
Z = 50
BUF
Q
100
Z = 50
Q#
Figure 3. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 4. Output Differential and Common Mode Voltages
Q
VA
VOCM = (VA + VB)/2
VB
ΔVOCM = | VOCM1 – VOCM2 |
VPP
Q#
Figure 5. Input to Any Output Pair Propagation Delay
IN
IN #
QX
Q X#
t PD
Figure 6. Output Duty Cycle
QX
Q X#
tPW
tPERIOD
tODC =
Document Number: 001-54863 Rev. *H
tPW
tPERIOD
Page 7 of 15
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CY2DL1510
Figure 7. Output-to-output and Device-to-device Skew
QX
Q X#
Device 1
QY
Q Y#
tSK1
QZ
Device 2
Q Z#
tSK1 D
Figure 8. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter ∝
Area Under the Masked Phase Noise Plot
Figure 9. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
Document Number: 001-54863 Rev. *H
tF
Page 8 of 15
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CY2DL1510
Figure 10. Synchronous Clock Enable Timing
CLK_EN
IN
IN#
tSOD
tPD
tSOE
QX
QX#
Document Number: 001-54863 Rev. *H
Page 9 of 15
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CY2DL1510
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DL1510AZC
32-Pin TQFP
Commercial, 0 °C to 70 °C
CY2DL1510AZCT
32-Pin TQFP tape and reel
Commercial, 0 °C to 70 °C
CY2DL1510AZI
32-Pin TQFP
Industrial, –40 °C to 85 °C
CY2DL1510AZIT
32-Pin TQFP tape and reel
Industrial, –40 °C to 85 °C
Ordering Code Definition
CY 2DL15 10 AZ C/I T
Tape and reel
Temperature range
C = Commercial
I = Industrial
Pb-free TQFP package
Number of differential output pairs
Base part number
Company ID: CY = Cypress
Document Number: 001-54863 Rev. *H
Page 10 of 15
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CY2DL1510
Package Dimension
Figure 11. 32-Pin Thin Plastic Quad Flat Pack 7 x 7 x 1.0 mm
9.00±0.25 SQ
7.00±0.10 SQ
32
25
DIMENSIONS ARE IN MILLIMETERS
0.37±0.05
24
1
0° MIN.
R. 0.08 MIN.
0.20 MAX.
STAND-OFF
0.05 MIN.
0.15 MAX.
8
17
9
16
SEATING PLANE
0.80
B.S.C.
0.25
GAUGE PLANE
R. 0.08 MIN.
0.20 MAX.
0-7°
0.20 MIN.
12°±1°
(8X)
1.20 MAX.
1.00±0.05
0.60±0.15
1.00 REF.
DETAIL
A
0.08
0.20 MAX.
SEE DETAIL
Document Number: 001-54863 Rev. *H
A
51-85063 *C
Page 11 of 15
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CY2DL1510
Acronyms
Document Conventions
Table 2. Acronyms Used in this Document
Table 3. Units of Measure
Acronym
Description
Symbol
Unit of Measure
ESD
electrostatic discharge
°C
degree Celsius
HBM
human body model
dBc
decibels relative to the carrier
JEDEC
Joint electron devices engineering council
GHz
giga hertz
LVDS
low-voltage differential signal
Hz
hertz
LVCMOS
low-voltage complementary metal oxide
semiconductor
kΩ
kilo ohm
µA
microamperes
LVTTL
low-voltage transistor-transistor logic
µF
micro Farad
OE
Output enable
RMS
root mean square
TQFP
thin quad flat pack
Document Number: 001-54863 Rev. *H
µs
micro second
mA
milliamperes
ms
millisecond
mV
millivolt
MHz
megahertz
ns
nanosecond
Ω
ohm
pF
pico Farad
ps
pico second
V
volts
W
watts
Page 12 of 15
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CY2DL1510
Document History Page
Document Title: CY2DL1510 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision
ECN
Orig. of Change
Submission
Date
Description of Change
**
2744225
CXQ/PYRS
08/19/09
New datasheet.
*A
2782891
CXQ
10/09/09
Updated format of Logic Block Diagram on page 1.
Added TSOD and TSOE specs (700 ps max) to AC Specs table.
Added TSETUP and THOLD specs (300 ps min) to AC Specs table.
Changed equation for RMS jitter in Figure 8 to proportionality.
Changed package drawing from 1.4 mm thickness 51-85088 spec to
1.0 mm thickness 51-850063 spec.
Added “Synchronous Clock Enable Function” to Features on page 1.
*B
2838916
CXQ
01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features”
on page 1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Removed VOD and ΔVOD specs from the DC Electrical Specs table on
page 4.
Added VPP and ΔVPP specs to the AC Electrical Specs table on page 5.
VPP min = 250 mV and max = 470 mV; ΔVPP max = 50 mV.
Added internal pullup resistance spec for CLK_EN in the DC Electrical
Specs table on page 4. Min = 60 kΩ, Max = 140 kΩ.
Added a measurement definition for CIN in the DC Electrical Specs table
on page 4.
Changed letter case and some names of all the timing parameters in the
AC Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on
page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in
Figures 5, 6, 7, and 9, to be consistent with EROS. Updated Figure 4
with definitions for VPP and ΔVPP.
*C
2885033
CXQ
02/26/2010 Updated 32-Pin TQFP package diagram.
*D
3011766
CXQ
08/20/2010 Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features”
on page 1 and in tJIT in the AC Electrical Specs table on page 5.
Changed max tPD spec from 480 ps to 600 ps.
Added note 5 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for differential inputs from 100 kΩ to 150 kΩ in the Logic
Block Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ
max in the DC Electrical Specs table.
Added VID max spec of 0.8V in the DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset
to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC
Electrical Specs table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Added Acronyms and Ordering Code Definition.
*E
3017258
CXQ
08/27/2010 Corrected Output Rise/Fall time diagram.
Document Number: 001-54863 Rev. *H
Page 13 of 15
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CY2DL1510
Document Title: CY2DL1510 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision
ECN
Orig. of Change
Submission
Date
*F
3100234
CXQ
11/18/2010
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC
Spec JESD78B IC Latchup Test”
Moved VPP from AC spec table to DC spec table, removed ΔVPP.
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets.
Added “Measured at 1 GHz” to tR, tF spec condition.
Removed tS and tH specs from AC specs table.
Changed to CY2DL1510AZ package code in Ordering Information.
Added to Z package code in Ordering Code Definition.
*G
3135201
CXQ
01/12/2011
Removed “Preliminary” status heading.
Fixed typo and removed resistors from IN/IN# in Logic Block Diagram.
Added Figure 10 to describe TSOE and TSOD.
*H
3090938
CXQ
02/25/2011
Post to external web.
Document Number: 001-54863 Rev. *H
Description of Change
Page 14 of 15
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CY2DL1510
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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cypress.com/go/powerpsoc
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54863 Rev. *H
Revised February 25, 2011
Page 15 of 15
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