MICRF501 Micrel MICRF501 300MHz to 600MHz RadioWire™ RF Transceiver Final General Description The MICRF501 is a single chip tranceiver intended for ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands from 300MHz to 600MHz with FSK data rates up to 128k baud. The transmitter consists of a PLL frequency synthesizer and a power amplifier. The frequency synthesizer consists of a voltage-controlled oscillator (VCO), a crystal oscillator, dualmodulus prescaler, programmable frequency dividers and a phase-detector. The loop filter is external for flexibility and can be a simple passive circuit. The VCO is a Colpitts oscillator which requires an external resonator and varactor. FSK modulation can be applied externally to the VCO or the crystal oscillator. The synthesizer has two different N, M and A frequency dividers. FSK modulation can also be implemented by switching between these dividers (max. 2400bps). The lengths of the N and M and A registers are 12, 10 and 6 bits respectively. For all types of FSK modulation, data is entered at the DATAIXO pin (see application circuit). The output power of the power amplifier can be programmed to eight levels. A lock-detect circuit detects when the PLL is in lock. In receive mode the PLL synthesizer generates the local oscillator (LO) signal. The N, M and A values that give the LO frequency are stored in the N0, M0 and A0 registers. The receiver is a zero intermediate frequency (IF) type in order to make channel filtering possible with low-power integrated low-pass filters. The receiver consists of a low noise amplifier (LNA) that drives a quadrature mixer pair. The mixer outputs feed two identical signal channels in phase quadrature. Each channel includes a preamplifier, a third order Sallen-Key RC low pass filter that protects the following gyrator filter from strong adjacent channel signals and finally, a limiter. The main channel filter is a gyrator capacitor implementation of a seven-pole elliptic low pass filter. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. The cut-off frequency of the Sallen-Key RC filter can be programmed to four different frequencies: 10kHz, 30kHz, 60kHz and 200kHz. An external resistor adjusts the cut-off frequency of the gyrator filter. The demodulator demodulates the I and Q channel outputs and produces a digital data output. It detects the relative phase of the I and the Q channel signal. If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data ‘1’). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data ‘0’). The output of the receiver is available on the DATAIXO pin. A RSSI (Receive Signal Strength Indicator) circuit indicates the received signal level. RadioWire™ A two pin serial interface is used to program the circuit. External components are necessary for RF input and output impedance matching and decoupling of power. Other external components are the VCO resonator circuit with varactor, crystal, feedback capacitors and components for FSK modulation with the VCO, loop filter, bias resistors for the power amplifier and gyrator filters. A T/R switch can be implemented with 2-pin diodes. This gives maximum input sensitivity and transmit output power. Features • • • • • Frequency range: 300MHz to 600MHz Modulation: FSK RF output power: 12dBm Sensitivity (19.2k bauds, BER=10-3): –105dBm Maximum data rate: 128k bauds Applications • • • • • • • Telemetry Remote metering Wireless controller Wireless data repeaters Remote control systems Wireless modem Wireless security system Ordering Information Part Number MICRF501BLQ Ambient Temp. Range Package –40°C to +85°C 44-Lead LQFP RadioWire is a trademark of Micrel, Inc. Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com March 2003 1 MICRF501 MICRF501 Micrel VB_IP QCHC ICHC IFQINN IFQINP MIXQOUTN MIXQOUTP IFIINN IFIINP MIXIOUTN MIXIOUTP Pin Configuration 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 MIXERVDD MIXERGND LNA_C RFGND2 RFIN RFVDD RFGND RFOUT PABIAS PA_C DIGGND XOSCIN XOSCOUT LD_C LOCKDET RSSI PDEXT DATAC DATAIXO CLKIN REGIN DIGVDD IFGND IFVDD ICHOUT QCHOUT OSCVDD OSCIN OSCGND GND CMPOUT CMPR MOD 44-Pin LQFP (BLQ) Pin Description Pin Number Pin Name 1 IFGND Pin Function IF Ground 2 IFVDD 3 ICHOUT I-Channel Output 4 QCHOUT Q-Channel Output 5 OSCVDD Colpitts Oscillator Power 6 OSCIN 7 OSCGND 8 GND 9 CMPOUT 10 CMPR Charge Pump Resistor Input 11 MOD Output for VCO Modulation 12 XOSCIN 13 XOSCOUT 14 LD_C 15 LOCKDET 16 RSSI 17 PDEXT Power Down Input (0=Power Down) 18 DATAC Data Filter Capacitor 19 DATAIXO 20 CLKIN Clock Input for Programming 21 REGIN Data Input for Programming 22 DIGVDD Digital Circuitry Power 23 DIGGND Digital Circuitry Ground MICRF501 IF Power Colpitts Oscillator Input Colpitts Oscillator and Substrate Ground Substrate Ground Charge Cump Output Crystal Oscillator Input Crystal Oscillator Output External Capacitor for Lock Detector Lock Detector Output Received Signal Strength Indicator Output Data Input/Output 2 March 2003 MICRF501 Micrel Pin Description, cont’d Pin Number Pin Name 24 PA_C Capacitor for Slow Ramp Up/Down of PA 25 PABIAS External Bias Resistor for Power Amplifier 26 RFOUT Power Amplifier Output 27 RFGND LNA, PA and Substrate Ground 28 RFVDD LNA and PA Power 29 RFIN 30 RFGND2 31 LNA_C 32 MIXERGND Mixer Ground 33 MIXERVDD Mixer Power 34 MIXIOUTP I-Channel Mixer Positive Output 35 MIXIOUTN I-Channel Mixer Negative Output 36 IFIINP I-Channel IF Amplifier Positive Input 37 IFIIN I-Channel IF Amplifier Negative Input 38 MIXQOUTP Q-Channel Mixer Positive Output 39 MIXQOUTN Q-Channel Mixer Negative Output 40 IFQINP Q-Channel IF Amplifier Positive Input 41 IFQINN Q-Channel IF Amplifier Negative Input 42 ICHC I-Channel Amplifier Capacitor 43 QCHC Q-channel Amplifier Capacitor 44 VB_IP Gyrator Filter Resistor March 2003 Pin Function Low Noise RF Amplifier (LNA) Input LNA First Stage Ground External LNA Stabilizing Capacitor 3 MICRF501 MICRF501 Micrel Absolute Maximum Ratings (Note 1) Operating Ratings (Note 2) Maximum Supply Voltage (VDD) ................................... +7V Maximum NPN Reverse Base-emitter Voltage .......... +2.5V Storage Temperature Range (TS) ............ –55°C to +150°C ESD Rating, Note 3 ................................................. 500mV Supply Voltage (VIN) ................................... +2.5V to +3.4V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance TQFP(θJA)-Multilayer Board ............................. 46.3°C/W Electrical Characteristics FREF = 850MHz, VDD = 2.5 to 3.4V, TA = 25°C, unless otherwise specified. Parameter Condition Min Typ Max Units 300 434 600 MHz <1 2 µA Overall Operating Frequency Power Down Current Logic High Input, VIH 70% VDD Logic Low Input, VIL 30% DATAIXO, Logic High Output (VOH) IOH = –500µA DATAIXO, Logic Low Output (VOL) IOL = 500µA LockDet, Logic High Output (VOH) IOH = –100µA LockDet, Logic Low Output (VOL) IOL = 100µA VDD-0.3 V 0.3 VDD-0.25 25 Data Setup to Clock (rising edge) 25 V V Clock/Data Frequency Clock/Data Duty-Cycle VDD 0.25 V 10 MHz 75 % ns VCO and PLL Section Prescaler Divide Ratio 32/33 Reference Frequency 40 MHz PLL Lock Time (int. modulation) 4kHz loop filter bandwidth 1 ms PLL Lock Time (ext. modulation) 1kHz loop filter bandwidth 4 ms Rx – (Tx with PA on) Switch Time 1kHz loop filter bandwidth 2 ms ±95/±380 ±125/±500 ±155/±620 µA 12 dBm Charge Pump Current Transmit Section fOUT = 434MHz Output Power RLOAD = 50Ω, VDD = 3.0V Transmit Data Rate (ext. modulation) Note 4 128 kbauds Transmit Data Rate (int. modulation) Note 5 2.4 kbauds Frequency Deviation to Modulation Rate Ratio unfiltered FSK Current Consumption Transmit Mode 10 dBm, RLOAD = 50Ω MICRF501 1.0 1.5 45 4 mA March 2003 MICRF501 Micrel Parameter Condition Receive Section fIN = 434MHz Receiver Sensitivity (Note 6) BER=10-3 Min Typ Max Units –1056 dBm Input 1dB Compression Level –41 dBm Input IP3 –31 dBm 26-j77 Ω 60 dB 0.7 2.1 V V 25kHz channel spacing 100kHz channel spacing 200kHz channel spacing 700kHz channel spacing 27 33 45 TBD dB dB dB dB RC filter: RC filter: RC filter: RC filter: 63 57 57 TBD dB Input Impedance RSSI Dynamic Range RSSI Output Voltage Adjacent Channel Rejection: fC = 10kHz fC = 30kHz fC = 60kHz fC = 200kHz Blocking Immunity (1MHz) PIN = –100dBm PIN = –30dBm fC = 10kHz fC = 30kHz fC = 60kHz fC = 200kHz Maximum Receiver Bandwidth 175 Receiver Settling Time Current Consumption Receive Mode dB dB 1 gyrator filter fC = 60kHz 8 Current Consumption XCO 300 kHz ms 11 mA µA Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. Note 4. Modulation is applied to the VCO and therefore the modulation cannot have any DC component. Some kind of coding is needed to ensure that the modulation is DC free, e.g., Manchester code or block code. With Manchester code the bitrate is half the baudrate, but with 3B4B block code the bitrate is _ of the baudrate. Note 5: Bitrate is the same as the baudrate. Note 6: Measured at 19.2k bauds and frequency deviation ±25kHz (external modulation), jitter of received data: < 45%. Output Power vs. Current @ 25°C 15 10 dBm 5 0 -5 -10 -15 -20 0 March 2003 5 10 15 20 25 30 35 40 45 ITOT (mA) 5 MICRF501 MICRF501 Micrel Functional Diagram 33 32 31 30 34 29 28 27 26 25 24 23 22 LNA PA C o n t r Logic o l 35 90° Prescaler 32/33 36 37 Control A1/A0 38 A-counter N1/N0 39 19 18 17 16 Gyrator Filters 41 20 N-counter R S S I RC Filters 40 I n t e r f a c e 21 M-counter 15 M1/M0 42 LD 14 Phase Detector 43 13 VCO Charge Pump Demod XCO 44 12 1 2 3 4 5 6 7 8 9 10 11 Figure 1. Transceiver Internal Blocks MICRF501 6 March 2003 MICRF501 Micrel Typical Application Figure 3 shows an example of a transceiver with modulation applied to the VCO. The inductors and trimming capacitors must have a good high frequency performance. The varactor MA4ST-350-1141 is a single variable capacitance diode manufactured by MACOM. The pin diode MA-4P789-1141 is manufactured by MACOM. C7 4.7n 44 R10 8.2k R8 47k RFOUT CMPOUT PABIAS C26 10n C28 6.8p L2 15n C29 18p C34 47p C25 470p D3 MA4P789-1141 L4 68n 21 C31 15p L5 10n 22 R3 10Ω REGIN CLKIN DATAIX0 VDD C24 1n 23 DIGVDD 20 REGIN 19 CLKIN 18 DATAIX0 Lock Det C20 2p-6p 17 DATAC C22 47p 16 PDEXT C23 1n 15 PDEXT 14 ANT DIGGND RSSI 13 LD_C 12 L3 47n C4 100p R14 1k 26 25 ant-switch D2 MA4P-789-1141 C27 22p 24 C21 5.6p 10MHz 27 C5 100p PA_C MOD C17 470p R16 1k 28 GND XOSCIN R12 3.3k 29 RFVDD CMPR C36 1n 31 RFIN 10 R11 150k C18 100n 32 30 9 11 C19 470p MIXER GND RFGND LOCKDET R9 8.2k 33 OSCGND R4 10Ω C30 47p MIXER VDD RFGND2 MICRF501 44-pin LQFP OSCIN VDD R5 10Ω LNA_C XOSCOUT R13 C15 270k 6.8n 34 MIXIOUTP D1 MA4ST350 35 MIXIOUTN C35 2.2p IFIINP OSCVDD 8 36 IFIINN 5 C16 100n 37 MIXQOUTP QCHOUT 7 MIXQOUTN 4 47n 38 ICHOUT QchOut 6 39 VDD IFVDD 3 C13 15p L1 40 IFGND IchOut R7 3.6k C2 100p C11 1n IFQINP R2 10Ω IFQINN 2 41 ICHC C1 1n 42 QCHC 1 VDD 43 VB_IP VDD C12 1n C10 1n C9 1n R6 8.2k R1 10Ω C8 4.7n C3 1n C32 2.2p C33 5.6p R15 3.6k VDD C6 100p VDD RSSI Figure 3. Application Circuit March 2003 7 MICRF501 MICRF501 Micrel List of components Component Values Component Values Component Values R1 10Ω C6 100pF C28 6.8pF R2 10Ω C8 4.7nF C29 18pF R3 10Ω C9 1nF C30 47pF R4 10Ω C10 1nF C31 15pF R5 10Ω C11 1nF C32 2.2pF R6 8.2kΩ C12 1nF C33 5.6pF R7 3.6kΩ C13 15pF C34 47pF R8 47kΩ C15 6.8nF C35 2.2pF R9 8.2kΩ C16 100nF C36 1nF R10 8.2kΩ C17 470pF L1 47nH R11 150kΩ C18 100nF L2 15nH R12 3.3kΩ C19 470pF L3 47nH R13 270kΩ C20 2pF-6pF L4 47nH R14 1kΩ C21 5.6pF L5 10nH R15 3.6kΩ C22 47pF D1 MA4ST-350-1141 R16 1kΩ C23 1nF D2 MA4P-789 C1 1nF C24 1nF D3 MA4P-789 C2 100pF C25 470pF crystal 10MHz C4 100pF C26 10nF C5 100pF C27 22pF MICRF501 8 March 2003 MICRF501 Micrel Applications Information DIFVDD VCO and PLL Section The frequency synthesizer consists of a VCO, crystal oscillator, dual-modulus prescaler, programmable frequency dividers, phase-detector, charge pump, lock detector and an external loop filter. The dual-modulus prescaler divides the VCO-frequency by 32/33. This mode is controlled by the Adivider. There are two sets of M, N and A-frequency dividers. Using both sets in transmit mode, FSK can be implemented by switching between those two sets. The phase-detector is a frequency/phase detector with back slash pulses to minimize phase noise. The VCO, crystal oscillator, charge pump, lock detector and the loop filter will be described in detail below. Voltage Controlled Oscillator (VCO) C36 1n C20 2-6p 10MHz R8 47k D1 MA4ST350 L1 The crystal oscillator is tuned by varying the trimming capacitor C20. The drift of the RF frequency is the same as the drift of crystal frequency when measured in ppm. The total difference in ppm, ∆f(ppm), between the tuned RF frequency and the drifted frequency is given by: ∆f(ppm) = ST × ∆T + n × ∆t where: • ST is the total temperature coefficient of the oscillator frequency (due to crystal and components) in ppm°C. • ∆T is the change in temperature from room temperature, at which the crystal was tuned. • n is the ageing in ppm/year. • ∆t is the time (in years) elapsed since the transceiver was last tuned. The demodulator will not be able to decode data when ∆f(Hz) = ∆f(ppm) × fRF is larger than the FSK frequency deviation. For small frequency deviations, the crystal should be pre-aged, and should have a small temperature coefficient. The circuit has been tested with a 10MHz crystal, but other crystal frequencies can be used as well. The circuit has been tested with a 10MHz crystal, but other crystal frequencies can be used as well. Pin 6 47nH OSCOUT Pin 7 Figure 3. VCO The circuit schematic of the VCO with external components is shown in Figure 3. The VCO is basically a Colpitts oscillator. The oscillator has an external resonator and varactor. The resonator consists of inductor L1 and the series connection of capacitor C13, the internal capacitance, the capacitance of the varactor and C35 in parallel with D1. The capacitance of the varactor (D1) decreases as the input voltage increases. The VCO frequency will therefore increase as the input voltage increases. The VCO has a positive gain (MHz/Volt). C35 is added, if necessary, to bring VCO tuning voltage to its middle range or VCC/2, which is measured at Pin 9 - CMPOUT. If the value of capacitor C13 and C14 become too small the amplitude of the VCO signal decreases, which leads to lower output power. The layout of the VCO is very critical. The external components should be placed as close to the input pin (Pin 6) as possible. The anode of the varactor D1 must be placed next to pins 7 and 8. Ground vias should be next to component pads. Crystal Oscillator The crystal oscillator is the reference for the RF output frequency as well as for the LO frequency in the receiver. The crystal oscillator is a very critical block since very good phase and frequency stability is required. The schematic of the crystal oscillator with external components for 10MHz is shown in Figure 4. These components are optimized for a crystal with 15pF load capacitance. March 2003 XOSCOUT Figure 4. Crystal Oscillator R7 3.6k C35 2.2p Pin 13 DIGGND Pin 5 loopfilter_output C22 5.6p C21 47p VDD C13 15p Pin 12 Prestart of XCO The start-up time of a crystal oscillator is typically some milliseconds. Therefore, to save current consumption, the MICRF501 circuit has been designed so that the XCO is turned on before any other circuit block. During start-up the XCO amplitude will eventually reach a sufficient level to trigger the M-counter. After counting two M-counter output pulses the rest of the circuit will be turned on. The current consumption during the prestart period is approximately 300µA. Lock Detector The MICRF501 circuit has a lock detector feature that indicates whether the PLL is in lock or not. A logic high on Pin 15 (LOCKDET) means that the PLL is in lock. The phase detector output is converted into a voltage that is filtered by the external capacitor C23, connected to Pin 14, LDC. The resulting DC voltage is compared to a reference window set by bits Ref0 – Ref5. The reference window can be stepped up/down linearly between 0V, Ref0 – Ref5 =1, and Ref0 – Ref5 = 0, which gives the highest value (DC voltage) of the reference window. The size of the window can either be 9 MICRF501 MICRF501 Micrel equal to two (Ref6 = 1) reference steps or four reference steps (Ref6 = 0). The bit setting that corresponds to lock can vary, depending on temperature, loop filter and type of varactor. Therefore, the lock detect circuit needs to be calibrated regularly by a software routine that finds the correct bit setting, by running through all combinations of bits Ref0 – Ref5. Depending on the size of the reference window, there will be several bit combinations that show lock. For instance, with a large reference window, as much as five bit combinations can make the lock detector show lock. To have the maximum robustness to noise, the third of the bit settings should be chosen. Charge Pump The charge pump can be programmed to four different modes with two currents, ±125µA and ±500µA. Bits 70 and 71 in the control word (cpmp1 and cpmp0) controls the operation. The four modes are: 1. cpmp1 = 0 Current is constant ±125µA. Used in cpmp0 = 0 applications where short PLL lock time is not important. very close to the desired frequency. Because of the small tuning range the VCO will not go out of lock when tuning the crystal oscillator. FSK Modulation The circuit has two sets of frequency dividers A0, N0, M0 and A1, N1, M1. The frequency dividers are programmed via the control word. A0, N0, M0 are to be programmed with the receive frequency and are used in receive mode. There are three ways of implementing FSK: • FSK modulation can be applied to the VCO. This way of implementing FSK modulation is explained more in detail in the next section. The values corresponding to the transmit frequency should be programmed in dividers A1, N1 and M1. Pin DATAIXO must be kept in tri-state from the time Tx-mode is entered until one starts sending data. • FSK modulation can be applied to the crystal oscillator. A, N and M values corresponding to the receive frequency and the low transmit frequency have to be found. The values corresponding to the low transmit frequency should be programmed in dividers A1, N1 and M1. In transmit mode, set DataIXO=‘1’ and tune the trimming capacitor until the output frequency that corresponds to data ‘1’ is reached. Check that the output frequency equals the low FSK frequency when DataIXO=‘0’. • FSK modulation by switching between the two sets of A, N and M dividers. A, N and M values corresponding to the receive frequency and both transmit frequencies have to be found. In transmit the values corresponding to data ‘0’ should be programmed in dividers A0, N0 and M0, and the values corresponding to data ‘1’ should be programmed in dividers A1, N1 and M1. • FSK modulation by adding/subtracting 1 to divider A1. The frequency deviation will be equal to the comparison frequency. The values corresponding to the transmit frequency should be programmed in dividers A1, N1 and M1. For all types of FSK modulation, data is entered at the DATAIXO pin. Loop Filter The design of the loop filter is of great importance for optimizing parameters like modulation rate, PLL lock time, bandwidth and phase noise. Low bitrates will allow modulation inside the PLL, which means the loop will lock on different frequency for 1s and 0s. This can be implemented by switching the internal dividers (M, N and A), or by pulling the reference frequency (XCO–modulation). Higher modulation rates (above 2400bps) imply implementation of modulation outside the PLL. This can be implemented by applying the modulation directly to the VCO. Loop filter values can be found using an appropriate software program. 2. cpmp1 = 0 Current is constant ±500µA. Used in cpmp0 = 1 applications where a short PLL lock time is important, e.g., internal modulation. See “Modulation Inside PLL” section. 3. cpmp1 = 1 Current is ±500µA when PLL is out of cpmp0 = 0 lock and ±125µA when it is in lock. Controlled by LOCKDET (Pin 15). Lock time is halved. See “Modulation Outside PLL” section. 4. cpmp1 = 1 Same as above in Tx. In Rx the current cpmp0 = 1 is ±500µA. Used when using dual-loop filters. See “Modulation Outside PLL Dual-Loop Filters” section. Tuning of VCO and XCO There are two circuit blocks that may need tuning, the VCO and the crystal oscillator. VCO Tuning When the tuning voltage is not at its mid-point measured at Pin 9, a capacitor value for C35 is chosen. This is particularly important when using VCO modulation. The gain curve of the VCO (MHz/Volt) is not linear and the gain will therefore vary with loop voltage. This means that the FSK frequency deviation also varies with loop voltage. It is therefore important to trim the loop voltage to the same value from circuit to circuit. When using internal modulation, tuning the VCO can be omitted as long as the VCO gain is large enough to allow the PLL to handle variations in process parameters and temperature without going out of lock. XCO Tuning Tune the trimming capacitor in the crystal oscillator to the precise desired transmit frequency. It is not possible to tune the crystal oscillator over a large frequency range. N, M and A values must therefore be chosen to give a RF frequency MICRF501 10 March 2003 MICRF501 Micrel Modulation Inside PLL Data rates above approximately 19200baud (including Manchester encoding) can be used with this loop filter without significant tracking of the modulating signal. PLL lock time will be approximately 4ms. If a faster PLL lock time is wanted, the charge pump can be made to deliver a current of 500µA per unit phase error, while an open drain NMOS on chip (Pin 10, CmpR) switches in a second damping resistor (R10) to ground as shown in Figure 6. Once locked on the correct frequency, the PLL automatically returns to standard low noise operation (charge pump current: 125µA/rad). If correct settings have been made in the control word (cpmp1 = 1, cpmp0 = 0), the fast locking feature is activated and will reduce PLL lock time by a factor of two without affecting the phase margin in the loop. Components C17, C18 C19, R11, R12, R13 and R16 (see application circuit) are necessary if FSK modulation is applied to the VCO. Data entered at the DATAIXO-pin will then be fed through the Mod-pin (Pin 11) which is a current output. The pin sources a current of 50µA when Logic 1 is entered at the DATAIXO and drains the current for Logic 0. The capacitance of C17 will set the order of filtering of the baseband signal. A large capacitance will give a slow ramp-up and therefore a high order of filtering of the baseband signal, while a small capacitance gives a fast ramp-up, which in turn also gives a broader frequency spectrum. Resistors R11 and R12 set the frequency deviation. If C18 is large compared to C17, the frequency deviation will be large. R13 should be large to avoid influencing the loop filter. Pin DATAIXO must be kept in tri-state from the time Tx-mode is entered until one starts sending data. A fast PLL requires a loop filter with relatively high bandwidth. If a second order loop filter is chosen, it may not give adequate attenuation of the comparison frequency. Therefore in the following example a third order loop filter is chosen. Example 1: Radio frequency fRF 434MHz 100kHz Comparison frequency fC Loop bandwidth BW 4.3kHz VCO gain Ko 28MHz/V Phase comparator gain Kd 500µA/rad Phase margin j 62° Breakthrough suppression A 20dB The component values will be: R101 IN 22k OUT C116 33n C115 1.5n C103 150p R109 6.2k Figure 5. Third Order Loop Filter With this loop filter, internal modulation up to 2400bps is possible. The PLL lock time from power-down to Rx will be approximately 1ms. Modulation Outside PLL (Closed Loop) When modulation is applied outside the PLL, it means that the PLL should not track the changes in the loop due to the modulation signal. A loop filter with relatively low bandwidth is therefore necessary. The exact bandwidth will depend on the actual modulation rate. Because the loop bandwidth will be significantly lower than the comparison frequency, a second order loop filter will normally give adequate attenuation of the comparison frequency. If not, a third order loop filter may give the extra attenuation needed. Example 2: Radio frequency fRF 434MHz Comparison frequency fC 140kHz Loop bandwidth BW 1.03kHz VCO gain Ko 28MHz/V Phase comparator gain Kd Phase margin j The component values will be: IN Modulation Outside PLL, Dual-Loop Filters Modulation outside the PLL requires a loop filter with a relatively low bandwidth compared to the modulation rate. This results in a relatively long loop lock time. In applications where modulation is applied to the VCO, but at the same time a short start-up time from power down to receive mode is needed, dual-loop filters can be implemented. Figure 7 shows how to implement dual-loop filters. CMPOUT Pin10 C15 C116 C115 C103 100n 6.8n 33n 1.5n 150p R9 6.2k R8 47k towards_VCO R109 6.2k Pin4 DFC OUT Figure 7. Dual-Loop Filters C16 100n C15 6.8n The loop filter used in transmit mode is made up of C15, C16, R9 and R10. The fast lock feature is also included (internal NMOS controlled by FLC, Fast Lock Control). This filter is automatically switched in/out by an internal NMOS at Pin 4, QchOut, which is controlled by DFC (Dual Filter Control). Bits OutS2, OutS1, OutS0 must be set to 110. When QchOut is used to switch the Tx loop filter to ground, neither QchOut nor IchOut can be used as test pins to look at the different receiver CmpR R9 8.2k R10 8.2k Figure 6. Second Order Loop Filter March 2003 C16 R10 6.2k FLC 125µA/rad 62° R102 22k Pin9 11 MICRF501 MICRF501 Micrel signals. The receive mode loop filter comprises C115, C116, R109, R101 and C101. stabilizes the overall dc feedback loop, which has a large low frequency loop gain. Figure 8 shows the input impedance of the LNA. Modulation Outside PLL (Open Loop) In this mode the charge pump output is tri-stated. The loop is open and will therefore not track the modulation. This means that the loop filter can have a relatively high bandwidth, which give short switching times. However, the loop voltage will decrease with time due to current leakage. The transmit time will therefore be limited and is dependent on the bandwidth of the loop filter. High bandwidth gives low capacitor values and the loop voltage will decrease faster, which gives a shorter transmit time. The loop is closed until the PLL is locked on the desired frequency and the power amplifier is turned on. The loop immediately opens when the modulation starts. The loop will not track the modulation, but the modulation still needs to be DC free due to the AC coupling in the modulation network. Transmit Power Amplifier (PA) The power amplifier is biased in class AB. The last stage has an open collector, and an external load inductor (L5) is therefore necessary. The DC current in the amplifier is adjusted with an external bias resistor (R14). A good starting point when designing the PA is a 1.5kΩ bias resistor which gives a bias current of approximately 50µA. This will give a bias current in the last stage of about 15mA. R14 is optimized to 1kΩ, as shown in the application circuit. The impedance matching circuit will depend on the type of antenna used, but should be designed for maximum output power. For maximum output power the load seen by the PA must be resistive and should be about 100Ω. The output power is programmable in eight steps, with approximately 3dB between each step. This is controlled by bits Pa2 - Pa0. To prevent spurious components from being transmitted the PA should be switched on/off slowly, by allowing the bias current to ramp up/down at a rate determined by the external capacitor C25 connected to Pin 24. The ramp up/down current is typically 1.1µA, which makes the on/off rate for a 2.8V power supply 2.6µs/pF. Turning the PA on/off affects the PLL. Therefore the on/off rate must be adjusted to the PLL bandwidth. PA Buffer A buffer amplifier is connected between the VCO and the PA to ensure that the input signal of the PA has sufficient amplitude to achieve the desired output power. This buffer can be bypassed by setting the bit Gc to 0. Figure 8. Input Impedance Input matching is very important to get high receive sensitivity. The LNA can be bypassed by setting bit LNA to ‘1’. This is useful for very strong signal levels. The RSSI signal can be used to drive a microcontroller to create a subroutine when a strong income signal is present to bypass the LNA. This will increase the dynamic range by approximately 25dB. The mixers have a gain of about 15dB at 434MHz. The differential outputs of the mixers are available at Pins 34, 35 and at Pins 38, 39. The output impedance of each mixer is about 30kΩ. Sallen-Key Filter and Preamplifier Each channel includes a preamplifier and a prefilter, which is a three-pole elliptic Sallen-Key lowpass filter with 20dB stopband attenuation. It protects the following gyrator filter from strong adjacent channel signals. The preamplifier has a gain of 35dB and output voltage swing is about 200mVPP. The third order Sallen-Key lowpass filter is programmable to four different cut-off frequencies according to the table below: Fc0 Cut-Off Frequency (kHz) Recommended Channel Spacing 0 0 10 ±2.5 25kHz 0 1 30 ±7.5 100kHz 1 0 60 ±15 200kHz 1 1 200 ±50 700kHz For the 10kHz cut-off frequency the first pole must be generated externally by connecting a 330pF capacitor between the outputs of each mixer. As the cut-off frequency of the gyrator filter can be set by varying an external resistor, the optimum channel spacing will depend on the cut-off frequencies of the Sallen-Key filter. The table above shows the recommended channel spacing depending on the different bit settings. Receive Front End (LNA and Mixers) A low noise amplifier in the RF receiver is used to boost the incoming signal prior to the frequency conversion process. This is important in order to prevent mixer noise from dominating the overall front end noise performance. The LNA is a two stage amplifier and has a nominal gain of 25dB at 434MHz. The LNA has a dc feedback loop, which provides bias for the LNA. The external capacitor C26 decouples and MICRF501 Fc1 12 March 2003 MICRF501 Micrel Gyrator Filter The main channel filter is a gyrator capacitor implementation of a seven-pole elliptic lowpass filter. The elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. An external resistor can adjust the cutoff frequency of the gyrator filter. The table below shows how the cut-off frequency varies with bias resistor: 14 47 8 The gyrator filter cut-off frequency should be chosen to be approximately the same as the cut-off frequency of the Sallen-Key filter. Cut-Off Frequency Setting The cut-off frequency must be high enough to pass the received signal (frequency deviation + modulation). The minimum cut-off frequency is given by: fC(min) = fDEV + Baudrate/2 For a frequency deviation of fDEV = 30kHz and a baudrate of 20k baud, the minimum cut-off frequency is 40kHz. Bit setting Fc1 = 1 and Fc0 = 0, which gives a cut-off of (60 ±15) kHz, would be the best choice. The gyrator filter bias resistor should therefore be 7.5kΩ or 8.2 kΩ, to set the gyrator filter cut-off frequency to approximately 60kHz. The crystal tolerance must also be taken into account when selecting the receiver bandwidth. If the crystal has a temperature tolerance of say ±10ppm over the total temperature range, the incoming RF signal and the LO signal can theoretically be 20ppm away from each other. The frequency deviation must always be larger than the maximum frequency drift for the demodulator to be able to demodulate the signal. The minimum frequency deviation (fDEVmin) is equal to the baudrate, according to the electrical characteristic's. This means that the frequency deviation has to be at least equal to the baudrate plus the maximum frequency drift. The frequency deviation may therefore vary from the minimum frequency deviation to the minimum frequency deviation plus two times the maximum frequency drift. The minimum cut-off frequency when crystal tolerances are considered is therefore given by: fCmin = ∆f × 2 fDEVmin + Baudrate/2 where ∆f is the maximum frequency drift between the LO signal and the incoming RF signal due to crystal tolerances. A frequency drift of 20ppm is 8680Hz at 434MHz. The frequency deviation must be higher than 28.68kHz for a baudrate of 20k baud. The frequency deviation may then vary from 20kHz, when the RF signal is 20ppm lower than the LO signal; to 37.36kHz when the RF signal is 20ppm higher than the LO signal. The minimum cut-off frequency is therefore 47.36kHz. March 2003 2.2 2 VOUT (V) 1.8 1.6 1.4 1.2 1 0.8 -110 0.6 -20 30 -30 30 -40 15 -50 55 -60 8.2 -70 70 -80 6.8 -90 Cut-Off Frequency (kHz) -100 Bias Resistor (kΩ) Limiter The limiter serves as a zero crossing detector, thus removing amplitude variations in the IF signal, while retaining only the phase variations. The limiter outputs are ideally suited to measure the I-Q phase difference, since its outputs are square waves with sharp edges. Demodulator The demodulator demodulates the I and Q channel outputs and produces a digital data output. It detects the relative phase difference between the I and the Q channel signals. For every edge (positive and negative) of the I channel limiter output, the amplitude of the Q channel limiter output is sampled, and vice versa. The output of the demodulator is available on the DATAIXO pin. The data output is therefore updated 4 times per cycle of the IF signal. This also means that the maximum jitter of the data output is 1/(4×∆f) (valid only for zero frequency offsets). If the I channel signal lags the Q channel, the FSK tone frequency lies above the LO frequency (data ‘1’). If the I channel leads the Q channel, the FSK tone lies below the LO frequency (data ‘0’). The inputs and the output of the demodulator are filtered by first order RC lowpass filters and then amplified by Schmitt triggers to produce clean square waves. It is recommended for low bitrates (<10kbps) that an additional capacitor is connected to Pin 18 (DataC) to decrease the bandwidth of the Rx data signal filter. The bandwidth of the filter must be adjusted for the bitrate. This functionality is controlled by bit RxFilt. Received Signal Strength Indicator (RSSI) The RSSI provides a DC output voltage proportional to the strength of the RF input signal. A graph of a typical RSSI response is shown in Figure 9 (fDEV = 30kHz, Gc = 1). PIN (dBm) Figure 9. Typical RSSI Characteristics This graph shows a range of 0.7V to 2.05V over a RF input range of 70dB. The RSSI can be used as a signal presence indicator. When a RF signal is received, the RSSI output increases. This could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life. Another application for which the RSSI could be used is to determine if transmit power can be reduced in a system. If the RSSI detects a strong signal, it could tell the transmitter to reduce the transmit power to reduce current consumption. 13 MICRF501 MICRF501 Micrel Programming A two-line bus is used to program the circuit; the two lines being CLKIN and REGIN. The 2-line serial bus interface allows control over the frequency dividers and the selective powering up of Tx, Rx and Synthesizer circuit blocks. The interface consists of an 80-bit programming register. Data is entered on the REGIN line with the most significant bit first. The first bit entered is called p1, the last one p80. The bits in the programming register are arranged as shown in Table 1. p1 – p6 p7 - p12 p13 – p24 p25 – p36 p37 – p46 p47 – p56 p57 p58 A1 A0 N1 N0 M1 M0 RxFilt Pa2 p59 p60 p61 p62 p63 p64 p65 p66 Pa1 Pa0 Gc ByLNA Ref6 Ref5 Ref4 Ref3 p67 p68 p69 p70 p71 p72 p73 p74 Ref2 Ref1 Ref0 Cpmp1 Cpmp0 Fc1 Fc0 OutS2 p75 p76 p77 p78 p79 p80 — — OutS1 OutS0 Mod1 Mod0 RT Pu — — Table 1. Bit Allocation MICRF501 14 March 2003 MICRF501 Micrel Name Description A1 frequency divider A1, 6 bits A0 frequency divider A0, 6 bits N1 frequency divider N1, 12 bits N0 frequency divider N0, 12 bits M1 frequency divider M1, 10 bits M0 frequency divider M0, 10 bits RxFilt 1=external capacitor for filtering of Rx data signal Pa2 gain setting in power amplifier Pa1 pa2, pa1, pa0 = 0 : lowest output power Pa0 pa2, pa1, pa0 = 1 : highest output power Gc gain control in power amplifier buffer: 1=high gain gain control in preamplifier in receiver: 1=high gain ByLNA 1 = the LNA is bypassed Ref6 Ref5 reference settings in lock detector Ref4 Ref3 all 0’s: highest reference Ref2 all 1’s: lowest reference Ref1 Ref0 Cpmp1 charge pump setting: Cpmp1=0, Cpmp0=1 : ±500µA Cpmp1=1, Cpmp0=0 : controlled by LockDet (LD) LD=0: ±500µA, LD=1: ±125µA Cpmp1=1, Cpmp0=1 : same as previous in Tx. In Rx the current is ±500µA. Cpmp0 Fc1 Cpmp1=0, Cpmp0=0 : ±125µA Active RC-filter settings Fc0 Fc1=0, Fc0=0 : 10kHz Fc1=1, Fc0=0 : 60kHz Fc1=0, Fc0=1 : 30kHz Fc1=1, Fc0=1 : 200kHz OutS2 I- and Q-channel OutS2 OutS1 OutS0 IchOut QchOut OutS2 OutS1 OutS0 IchOut QchOut OutS1 output select 0 0 high Z 1 0 0 lim_qch gm_qch OutS0 0 0 1 sk_ich sk_qch 1 0 1 gm_ich 0 1 0 gm_ich gm_qch 1 1 0 high Z 0 1 1 lim_ich lim_qch 1 1 1 N_div sk:_*:Sallen-Key-filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output (for testing). 110 is for dual-loop filter applications, see Modulation Outside PLL, Dual-Loop Filters. lim_ich Dual LF M_div Mod1 Mod1 = 0, Mod0 = 0: FSK modulation can be applied to the VCO Mod0 Mod1 = 0, Mod0 = 1: FSK modulation can be applied to the VCO: crystal modulation Mod1 = 1, Mod0 = 0: FSK modulation by switching between the two sets of dividers Mod1 = 1, Mod0 = 1: FSK modulation by adding/subtracting 1 to divider A1: fdeviation = fcomparison RT 0 = receive mode 1 = transmit mode Pu 1 = power up, 0 = power down (When Pu=1, power down is controlled by PuExt) 0 high Z Table 2. Bit Description March 2003 15 MICRF501 MICRF501 Micrel 6. A new control word is entered into the first register. A transition on the REGIN signal when CLKIN is high will now turn the power amplifier off. 7. When the power amplifier is turned off an internal load pulse is generated. The new control word is loaded into the parallel register and the circuit enters a new mode (in this case power down mode). CLKIN must go low after the internal load pulse is generated. As long as transitions on REGIN are avoided when CLKIN is high, a new control word can be clocked into the first register any time without affecting the operation of the transceiver. Example 1. f RF = 434.245MHz, frequency deviation: ≈ ±10kHz, fXCO = 10.00MHz. FSK modulation is implemented by switching between dividers. When FSK modulation is applied to the VCO the PLL is using the dividers A1, N1 and M1. When Mod1 = 1 and Mod0 = 0 it is possible to switch between the different dividers in the PLL. DATAIXO controls the switching. When DATAIXO = 0 the PLL uses dividers A0, N0 and M0. When DATAIXO = 1 the PLL uses dividers A1, N1 and M1. Switching between the different dividers can be used to implement FSK modulation. The N, M and A values can be calculated from the formula: f fRF fC = XCO = M 32 × N + A where fC is the comparison frequency. The 8bit control word is first read into a shift-register, and is then loaded into a parallel register by a transition of the REGIN signal (positive or negative) when the CLKIN signal is high. The circuit then goes directly into the specified mode (receive, transmit, etc.). 1 23 4 5 6 7 CLKIN REGIN LOAD_INT A1 A0 N1 N0 M1 M0 Tx 18 11 127 115 94 85 Rx 27 27 143 143 106 106 RxFilt Pa2 Pa1 Pa0 Gc ByLNA Tx 0 1 1 1 1 0 Rx 0 1 1 1 1 0 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Tx 0 0 0 0 0 0 Rx 0 0 0 0 0 0 Fc1 Fc0 OutS2 PA_C Ref0 LOCKDET Tx 0 1 0 0 1 0 Rx 0 1 0 0 1 0 OutS1 OutS0 Mod1 Mod0 RT Pu Tx 0 0 1 0 1 1 Rx 0 0 1 0 0 1 Figure 10. Timing of CLKIN, REGIN and the Internal LOAD_INT and PA_C Signals 1. The second last bit is clocked into the first shift register (‘1’). 2. The last bit is clocked into the first shift register (‘1’). 3. A transition on the REGIN signal generates an internal load pulse that loads the control word into the parallel register. The circuit enters the new mode (in this case Tx-mode). The circuit stabilizes in the new mode. 4. When the clock signal goes low, the power amplifier (PA) is turned on slowly in order to minimize spurious components on the RF output signal. To be sure the PLL is in lock before the PA is turned on, the PA should be turned on after LOCKDET has been set. The negative transition on the clock signal should come a minimum time of one period of the comparison frequency after the internal load pulse is generated. 5. The power amplifier is fully turned on. MICRF501 Cpmp1 Cpmp0 Binary form: (MSB to the left): Tx: 010010 001011 000001111111 000001110011 0001011110 0001010101 011110000000010010001011 Rx: 011011 011011 000010001111 000010001111 0001101010 0001101010 011110000000010010001001 When FSK modulation is implemented by switching between the different dividers A, N and M values corresponding to the receive frequency and both transmit frequencies have to be found. 16 March 2003 MICRF501 Micrel Example 2. fRF = 434.245MHz, fRF = 10.00MHz. FSK modulation is applied to the VCO. A1 A0 N1 N0 M1 M0 Tx 27 27 143 143 106 106 Rx 27 27 143 143 106 106 RxFilt Pa2 Pa1 Pa0 Gc ByLNA Tx 0 1 1 1 1 0 Rx 0 1 1 1 1 0 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Tx 0 0 0 0 0 0 Rx 0 0 0 0 0 0 Fc1 Fc0 OutS2 Ref0 Cpmp1 Cpmp0 Tx 0 0 1 1 0 0 Rx 0 0 1 1 0 0 OutS1 OutS0 Mod1 Mod0 RT Pu Tx 0 0 0 0 1 1 Rx 0 0 0 0 0 1 March 2003 Binary form: (MSB to the left): Tx: 011011 011011 000010001111 000010001111 0001101010 0001101010 011110000000001100000011 Rx: 011011 011011 000010001111 000010001111 0001101010 0001101010 011110000000001100000001 With modulation applied to the VCO, A, N and M values corresponding to the receive frequency have to be found. The same set of A, N and M values are used in all modes. Programming After Battery Reset In order to ensure a successful programming after VDD has been zero volts, the PDEXT needs to be kept low during the first programming sequence. This can be done by a seperate I/O-line from a microcontroller, or a RC circuit on the PDEXT pin to the VDD (a capacitor between PDEXT and ground and a resistor between PDEXT and VDD). Using the latter method, R and C values need to be chosen so that the voltage on the PDEXT pin is lower then VDD/2 when the control word is loaded into the parallel register. (See Figure 10.) 17 MICRF501 MICRF501 Micrel Package Information 0.551±0.012 (14.0±0.3) 0.394±0.012 (10.0±0.3) 0.315±0.012 (8.0±0.3) 44 34 1 33 11 23 0.031 (0.8) 12 22 0.039 (1.0) 0.085±0.004 (2.15±0.1) 0.016 (0.4) 0.002 (0.05) 0.047 (1.2) 44-Pin LQFP (BLQ) MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. MICRF501 18 March 2003