8-BIT RIPPLE COUNTER DESCRIPTION FEATURES ■ 1.8GHz min. count frequency ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E137 are very high speed binary ripple counters. The two least significant bits were designed with very fast edge rates, while the more significant bits maintain standard ECLinPS output edge rates. This allows the counters to operate at very high frequencies, while maintaining a moderate power dissipation level. The devices are ideally suited for multiple frequency clock generation, as well as for counters in highperformance ATE time measurement boards. Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted, enables the counter while overriding any synchronous enable signals. The E137 features XOR'ed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted, the counter becomes disabled on the next CLK transition. All outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted in order to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. EN1 (or EN2) and CLK edges are coincident. Sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip-flop set-up time) to ensure that the synchronous enable signal is clocked correctly; hence, the counter is disabled. The E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal. If a single-ended signal is to be used, the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. VBB can only source/sink 0.5mA; therefore, it should be used as a switching reference for the E137 only. All input pins left open will be pulled LOW via an input pull-down resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device. The asynchronous Master Reset resets the counter to an all zero state upon assertion. Synchronous and asynchronous enable pins Differential clock input and data output pins VBB output for single-ended use Asynchronous Master Reset Internal 75KΩ input pull-down resistors Available in 28-pin PLCC packge Q5 Q5 Q6 25 24 23 22 VCCO Q6 Q7 Q7 PIN CONFIGURATION 21 20 19 A_Start 26 18 Q4 EN1 EN2 27 17 Q4 16 VCC VEE CLK CLK 1 2 VBB 4 28 PLCC TOP VIEW J28-1 7 8 Q0 Q0 Q1 9 Q3 14 Q3 13 Q2 12 Q2 10 11 Q1 6 15 VCCO 5 MR 3 VCCO ■ ■ ■ ■ ■ ■ PIN NAMES Pin SY10E137 SY100E137 Function CLK, CLK Differential Clock Inputs Q0–Q7, Q0–Q7 Differential Q Outputs A_Start Asynchronous Enable Input EN1, EN2 Synchronous Enable Inputs MR Asynchronous Master Reset VBB Switching Reference Output VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E137 SY100E137 Micrel BLOCK DIAGRAM A_Start EN1 D R Q Q0 Q0 EN2 Q1 Q1 Q6 Q6 Q7 Q7 Q CLK CLK CLK CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK Q CLK D D D R D R D R R MR VBB SEQUENTIAL TRUTH TABLE(1) Function EN1 EN2 A_Start MR CLK Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Reset X X X H X L L L L L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L L L L L L L H H H L H Stop H H L L L L L L Z Z L L L L L L L L L L L L H H H H Async. Start H H L L L L H H H L L L Z Z Z L L L L L L L L L L L L L L L H H H L L H L H L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L L H H H L L H L L H L H Stop L L H H L L L L Z Z L L L L L L L L H H L L L L H H Sync. Start H H H H H H L L L L L L Z Z Z L L L L L L L L L L L L H H H L L H H H L L H L Stop H H L L L L L L Z Z L L L L L L L L H H H H L L L L Count L L L L L L L L L L L L Z Z Z L L L L L L L L L L L L H H H H H H L H H H L H Reset X X X H X L L L L L L L L NOTE: 1. Z = LOW-to-HIGH transition 2 SY10E137 SY100E137 Micrel DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter Output Reference Voltage VBB 10E 100E IIH Input HIGH Current IEE Power Supply Current TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. –1.38 –1.38 — — –1.25 –1.31 –1.26 –1.38 — — –1.19 –1.26 — — 150 — — 150 — — 150 — — 121 121 145 145 — — 121 121 145 145 — — 121 139 145 167 10E 100E –1.27 –1.35 –1.26 –1.38 — — Unit Condition V — µA — mA — Max. Unit Condition — MHz — ps — AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. — 1800 2200 TA = +85°C Max. Min. Typ. fCOUNT Max. Count Frequency 1800 2200 — 1800 2200 tPLH tPHL Propagation Delay to Output CLK to Q0 CLK to Q1 CLK to Q2 CLK to Q3 CLK to Q4 CLK to Q5 CLK to Q6 CLK to Q7 A_Start to Q0 MR to Q0 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2025 2425 2750 3125 3450 3775 4075 1325 1000 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1300 1600 1950 2275 2625 2950 3250 3575 950 700 1700 2050 2450 2775 3150 3475 3800 4125 1325 1000 2150 2500 2925 3350 3750 4150 4450 4800 1700 1300 1350 1650 2025 2350 2700 3050 3375 3700 950 700 1750 2100 2500 2850 3225 3550 3925 4250 1325 1000 2200 2550 3000 3425 3625 4250 4600 4950 1700 1300 tS Set-up Time (EN1, EN2) 0 –150 — 0 –150 — 0 –150 — ps — tH Hold Time (EN1, EN2) 300 150 — 300 150 — 300 150 — ps — tRR Reset Recovery Time MR, A_Start 400 200 — 400 200 — 400 200 — ps — tPW Minimum Pulse Width CLK, MR, A_Start 400 — — 400 — — 400 — — ps — VPP Minimum Input Swing (CLK) 0.25 — 1.0 0.25 — 1.0 0.25 — 1.0 V 1 VCMR Com. Mode Range (CLK) –0.4 — –2.0 –0.4 — –2.0 –0.4 — –2.0 V — tr tf Rise/Fall Time, 20% to 80% Q0, Q1 Q2–Q7 ps — 150 275 — — 400 600 150 275 — — 400 600 150 275 — — 400 600 NOTE: 1. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50mV input swings. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E137JC J28-1 Commercial SY10E137JCTR J28-1 Commercial SY100E137JC J28-1 Commercial SY100E137JCTR J28-1 Commercial 3 SY10E137 SY100E137 Micrel 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4