Lattice ISPLSI2064V-100LJ84I 3.3v high density programmable logic Datasheet

®
ispLSI 2064V
3.3V High Density Programmable Logic
Features
Functional Block Diagram
• HIGH DENSITY PROGRAMMABLE LOGIC
GLB
D Q
D Q
S
B1
D Q
EW
A3
A5
A4
A6
Input Bus
Logic
Array
B2
D
A2
D Q
B3
Output Routing Pool (ORP)
A1
B4
ES
IG
N
Global Routing Pool
(GRP)
A0
Input Bus
B5
B0
A7
Output Routing Pool (ORP)
N
Input Bus
0139A/2064V
Description
FO
•
B6
B7
Output Routing Pool (ORP)
•
Input Bus
Output Routing Pool (ORP)
R
•
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
3.3V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 5V TTL Devices
— The 64 I/O Pin Version is Fuse Map Compatible with
5V ispLSI 2064
HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 100MHz Maximum Operating Frequency
— tpd = 7.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 3.3V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
VE
64
SI
20
•
The ispLSI 2064V is a High Density Programmable Logic
Device available in 64 and 32 I/O-pin versions. The
device contains 64 Registers, four Dedicated Input pins,
three Dedicated Clock Input pins, two dedicated Global
OE input pins and a Global Routing Pool (GRP). The
GRP provides complete interconnectivity between all of
these elements. The ispLSI 2064V features in-system
programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2064V offers non-volatile
reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
pL
The basic unit of logic on the ispLSI 2064V device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1…B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064V device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
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• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
2064v_10
1
September 2000
Specifications ispLSI 2064V
Functional Block Diagram
Generic Logic
Blocks (GLBs)
0139B/2064V
S
Input Bus
Output Routing Pool (ORP)
D
A5
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
B0
GOE0/IN 3
A6
A7
Output Routing Pool (ORP)
Input Bus
TMS/IN 2
CLK 0
CLK 1
CLK 2
ispEN
A4
I/O 23
0139B/2064V.32IO
FO
Y0
Y1
Y2
I/O 28
I/O 29
I/O 30
I/O 31
I/O 20
I/O 21
I/O 22
I/O 23
I/O 18
I/O 19
I/O 16
I/O 17
Input Bus
B1
GOE1/Y0
RESET/Y1
TCK/Y2
CLK 0
CLK 1
CLK 2
ispEN
TDI/IN 0
TDO/IN 1
TDO/IN 2
Output Routing Pool (ORP)
RESET
Input Bus
TCK/IN 3
A7
EW
A6
A2
N
A5
B4
B2
A3
R
A4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 35
I/O 34
I/O 33
I/O 32
Global Routing Pool
(GRP)
A1
I/O 9
I/O 10
I/O 11
B0
I/O 39
I/O 38
I/O 37
I/O 36
B5
B3
I/O 8
A3
I/O 43
I/O 42
I/O 41
I/O 40
B6
A0
Output Routing Pool (ORP)
B1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 46
I/O 45
I/O 44
Input Bus
B2
A2
TDI/IN 0
TMS/IN 1
Output Routing Pool (ORP)
Global Routing Pool
(GRP)
I/O 24
I/O 25
I/O 26
I/O 27
Output Routing Pool (ORP)
I/O 12
I/O 13
I/O 14
I/O 15
B7
B3
A1
Output Routing Pool (ORP)
Megablock
B4
A0
Input Bus
I/O 8
I/O 9
I/O 10
I/O 11
B5
I/O 47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
B6
ES
IG
N
Output Routing Pool (ORP)
B7
Generic Logic
Blocks (GLBs)
Input Bus
I/O 12
I/O 13
I/O 14
I/O 15
Input Bus
Megablock
I/O 27
I/O 26
I/O 25
I/O 24
I/O 31
I/O 30
I/O 29
I/O 28
I/O 51
I/O 50
I/O 49
I/O 48
I/O 55
I/O 54
I/O 53
I/O 52
I/O 56
I/O 58
I/O 57
I/O 59
I/O 63
I/O 62
I/O 61
I/O 60
GOE 1
GOE 0
Figure 1. ispLSI 2064V Functional Block Diagram (64-I/O and 32-I/O Versions)
The 64-I/O 2064V contains 64 I/O cells, while the 32-I/O
version contains 32 I/O cells. Each I/O cell is directly
connected to an I/O pin and can be individually programmed to be a combinatorial input, output or
bi-directional I/O pin with 3-state control. The signal
levels are TTL compatible voltages and the output drivers
can source 4 mA or sink 8 mA. Each output can be
programmed independently for fast or slow output slew
rate to minimize overall output switching noise. Device
pins can be safely driven to 5-Volt signal levels to support
mixed-voltage systems.
VE
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
64
Programmable Open-Drain Outputs
SI
20
In addition to the standard output configuration, the
outputs of the ispLSI 2064V are individually programmable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC “1”),
the output is configured as a totem-pole output. When
this fuse is programmed (JEDEC “0”), the output is
configured as an open-drain. The default configuration
when the device is in bulk erased state is totem-pole
configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
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Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and
two or one ORPs are connected together to make a
Megablock (see Figure 1). The outputs of the eight GLBs
are connected to a set of 32 or 16 universal I/O cells by
two or one ORPs. Each ispLSI 2064V device contains
two Megablocks.
U
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064V device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
2
Specifications ispLSI 2064V
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +5.6V
Input Voltage Applied ..................................... -0.5 to +5.6V
Off-State Output Voltage Applied .................. -0.5 to +5.6V
ES
IG
N
S
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
D
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
SYMBOL
EW
DC Recommended Operating Condition
PARAMETER
VIL
VIH
Input Low Voltage
UNITS
TA = 0°C to + 70°C
3.0
3.6
V
Industrial
TA = -40°C to + 85°C
3.0
3.6
V
0.8
V
VSS – 0.5
2.0
FO
Input High Voltage
MAX.
Commercial
N
Supply Voltage
R
VCC
MIN.
5.25
V
Table 2-0005/2064V
VE
Capacitance (TA=25°C, f=1.0 MHz)
TYPICAL
UNITS
Dedicated Input Capacitance
10
pf
VCC = 3.3V, VIN = 2.0V
I/O Capacitance
10
pf
VCC = 3.3V, VI/O = 2.0V
13
pf
VCC = 3.3V, VY = 2.0V
C1
C2
C3
64
PARAMETER
20
SYMBOL
Clock and Global Output Enable Capacitance
TEST CONDITIONS
SI
Table 2-0006/2064V
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Data Retention Specifications
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PARAMETER
MINIMUM
MAXIMUM
UNITS
20
–
Years
10000
–
Cycles
Data Retention
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ispLSI Erase/Reprogram Cycles
U
Table 2-0008/2064V
3
Specifications ispLSI 2064V
Switching Test Conditions
Input Pulse Levels
Figure 2. Test Load
GND to 3.0V
Input Rise and Fall Time
10% to 90%
+ 3.3V
≤ 1.5 ns
Output Timing Reference Levels
1.5V
Output Load
R1
Device
Output
See Figure 2
Table 2-0003/2064V
3-state levels are measured 0.5V from
steady-state active level.
S
1.5V
ES
IG
N
Input Timing Reference Levels
CL
35pF
Active High
∞
348Ω
35pF
Active Low
C
316Ω
348Ω
35pF
Active High to Z
at VOH -0.5V
∞
348Ω
5pF
Active Low to Z
at VOL +0.5V
316Ω
348Ω
5pF
0213A/2064V
N
B
*CL includes Test Fixture and Probe Capacitance.
D
R2
348Ω
EW
R1
316Ω
R
TEST CONDITION
A
C L*
R2
Output Load Conditions (see Figure 2)
Test
Point
FO
Table 2-0004/2064V
DC Electrical Characteristics
PARAMETER
SYMBOL
CONDITION
IOL= 8 mA
64
Output Low Voltage
IOH = -4 mA
Output High Voltage
Input or I/O Low Leakage Current
20
VOL
VOH
IIL
VE
Over Recommended Operating Conditions
3
MIN.
TYP.
MAX. UNITS
–
–
0.4
V
2.4
–
–
V
0V ≤ VIN ≤ VIL (Max.)
–
–
-10
µA
(VCC – 0.2)V ≤ VIN ≤ VCC
–
–
10
µA
VCC ≤ VIN ≤ 5.25V
–
–
50
mA
µA
Input or I/O High Leakage Current
IIL-isp
IIL-PU
IOS1
ispEN Input Low Leakage Current
0V ≤ VIN ≤ VIL
–
–
-150
I/O Active Pull-Up Current
0V ≤ VIN ≤ VIL
–
–
-150
µA
Output Short Circuit Current
VCC = 3.3V, VOUT = 0.5V
–
–
-100
mA
ICC2, 4
Operating Power Supply Current
VIL = 0.0V, VIH = 3.0V
–
82
–
mA
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SI
IIH
fCLOCK = 1 MHz
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Table 2-0007/2064V
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test
problems by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at VCC = 3.3V and TA= 25°C.
4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum ICC .
4
Specifications ispLSI 2064V
External Timing Parameters
Over Recommended Operating Conditions
4
-80
-100
1
-60
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
–
15.0
ns
A
2
Data Propagation Delay
–
12.0
–
15.0
–
20.0
ns
3
3
Clock Frequency with Internal Feedback
102
–
80.0
–
4
Clock Frequency with External Feedback ( tsu2 + tco1)
83.3
–
64.5
–
51.3
61.7
–
–
MHz
–
5
Clock Frequency, Max. Toggle
125
–
100
–
71.4
–
MHz
–
6
GLB Reg. Setup Time before Clock, 4 PT Bypass
5.5
–
7.0
–
9.0
–
ns
A
7
GLB Reg. Clock to Output Delay, ORP Bypass
–
5.0
–
6.5
–
8.5
ns
–
8
GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0
–
0.0
–
0.0
–
ns
–
9
GLB Reg. Setup Time before Clock
7.0
–
9.0
–
11.0
–
ns
–
10 GLB Reg. Clock to Output Delay
–
6.3
–
11 GLB Reg. Hold Time after Clock
A
12 Ext. Reset Pin to Output Delay
D
ES
IG
N
A
MHz
–
7.5
–
9.5
ns
0.0
–
0.0
–
0.0
–
ns
–
12.0
–
14.0
–
16.0
ns
EW
1
–
S
A
–
7.0
–
8.0
–
ns
–
13.0
–
15.0
–
18.0
ns
–
13.0
–
15.0
–
18.0
ns
–
7.5
–
10.0
–
12.0
ns
–
7.5
–
10.0
–
12.0
ns
18 External Synchronous Clock Pulse Duration, High
4.0
–
5.0
–
7.0
–
ns
19 External Synchronous Clock Pulse Duration, Low
4.0
–
5.0
–
7.0
–
ns
C
15 Input to Output Disable
B
16 Global OE Output Enable
C
17 Global OE Output Disable
–
–
5.0
N
13 Ext. Reset Pulse Duration
14 Input to Output Enable
R
–
B
64
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
Refer to Timing Model in this data sheet for further details.
Standard 16-bit counter using GRP feedback.
Reference Switching Test Conditions section.
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SI
20
1.
2.
3.
4.
DESCRIPTION
VE
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
twl
TEST
2
#
COND.
FO
PARAMETER
5
Table 2-0030/2064V
Specifications ispLSI 2064V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
2
#
-100
DESCRIPTION
-60
-80
MIN. MAX. MIN. MAX. MIN. MAX.
UNITS
–
0.2
–
0.4
–
0.6
ns
21 Dedicated Input Delay
–
0.6
–
1.3
–
1.4
ns
22 GRP Delay
–
0.7
–
1.2
–
2.1
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
–
4.6
–
5.8
–
9.6
ns
24 4 Product Term Bypass Path Delay (Registered)
–
6.0
–
7.5
–
10.3
ns
25 1 Product Term/XOR Path Delay
–
6.7
–
9.2
–
12.3
ns
26 20 Product Term/XOR Path Delay
–
7.5
–
9.5
–
12.3
ns
–
8.5
–
11.3
–
14.4
ns
–
0.3
–
0.3
–
1.3
ns
0.1
–
0.2
–
0.2
–
ns
3.8
–
5.4
–
8.0
–
ns
–
1.5
–
1.6
–
1.6
ns
–
2.2
–
2.5
–
2.8
ns
33 GLB Product Term Reset to Register Delay
–
3.8
–
5.6
–
9.3
ns
34 GLB Product Term Output Enable to I/O Cell Delay
–
7.2
–
8.5
–
10.4
ns
3.0
4.4
3.8
5.6
6.5
9.3
ns
–
1.4
–
1.4
–
1.5
ns
–
0.1
–
0.4
–
0.5
ns
38 Output Buffer Delay
–
1.9
–
2.2
–
2.2
ns
39 Output Slew Limited Delay Adder
–
11.9
–
12.2
–
12.2
ns
40 I/O Cell OE to Output Enabled
–
4.9
–
4.9
–
4.9
ns
41 I/O Cell OE to Output Disabled
–
4.9
–
4.9
–
4.9
ns
42 Global Output Enable
–
2.6
–
5.1
–
7.1
ns
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
1.5
1.5
2.3
2.3
4.2
4.2
ns
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
1.5
1.5
2.3
2.3
4.2
4.2
ns
–
6.5
–
7.9
–
9.5
ns
GRP
tgrp
27 XOR Adjacent Path Delay
N
29 GLB Register Setup Time befor Clock
R
30 GLB Register Hold Time after Clock
VE
32 GLB Register Reset to Output Delay
FO
31 GLB Register Clock to Output Delay
35 GLB Product Term Clock Delay
36 ORP Delay
37 ORP Bypass Delay
20
Outputs
64
torp
torpbp
SE
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SI
tob
tsl
toen
todis
tgoe
tgy0
tgy1/2
3
28 GLB Register Bypass Delay
ORP
Clocks
EW
GLB
t4ptbpc
t4ptbpr
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
S
20 Input Buffer Delay
ES
IG
N
tio
tdin
D
Inputs
Global Reset
U
tgr
45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
6
Table 2-0036/2064V
Specifications ispLSI 2064V
ispLSI 2064V Timing Model
I/O Cell
GRP
GLB
ORP
I/O Cell
Feedback
I/O Delay
GRP
Reg 4 PT Bypass
GLB Reg Bypass
ORP Bypass
#20
#22
#24
#28
#37
20 PT
XOR Delays
GLB Reg
Delay
D
#25, 26, 27
ORP
Delay
Q
#36
RST
#45
#29, 30,
31, 32
D
Reset
EW
Control RE
PTs
OE
#33, 34, CK
35
#43, 44
Y0,1,2
#42
R
N
GOE 0,1
tco
10.1 ns
Clock (max) + Reg h - Logic
(tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 0.7 + 4.4) + (3.8) - (0.2 + 0.7 + 7.5)
=
=
=
=
Clock (max) + Reg co + Output
(tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 0.7 + 4.4) + (1.5) + (1.4 + 1.9)
VE
=
=
=
=
64
0.7 ns
Logic + Reg su - Clock (min)
(tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 0.7 + 7.5) + (0.1) - (0.2 + 0.7 + 3.0)
20
th
=
=
=
=
SI
4.6 ns
1
FO
Derivations of tsu, th and tco from the Product Term Clock
tsu
pL
Note: Calculations are based on timing specifications for the ispLSI 2064V-100L.
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Table 2-0042/2064V
7
#38,
39
ES
IG
N
I/O Pin
(Input)
Comb 4 PT Bypass #23
#21
S
Ded. In
#40, 41
0491/2064
I/O Pin
(Output)
Specifications ispLSI 2064V
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 2064V device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used.
S
Figure 3. Typical Device Power Consumption vs fmax
ES
IG
N
120
ispLSI 2064V
100
D
90
80
0
25
50
75
fmax (MHz)
N
70
EW
ICC (mA)
110
100
FO
R
Notes: Configuration of Four 16-bit Counters
Typical Current at 3.3V, 25° C
ICC can be estimated for the ispLSI 2064V using the following equation:
VE
ICC(mA) = 10 + (# of PTs * 0.556) + (# of nets * Max freq * 0.0053)
64
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
20
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
SI
0127/2064
pL
Power-up Considerations
When Lattice 3.3-Volt 2000V devices are used in mixed
5V/3.3V applications, some consideration needs to be
given to the power-up sequence. When the I/O pins on
the 3.3V ispLSI devices are driven directly by 5V devices,
a low impedance path can exist on the 3.3V device
between its I/O and Vcc pins when the 3.3V supply is not
present. This low impedance path can cause current to
flow from the 5V device into the 3.3V ispLSI device. The
maximum current occurs when the signals on the I/O pins
are driven high by the 5V devices. If a large enough
current flows through the 3.3V I/O pins, latch-up can
occur and permanent device damage may result.
SE
is
This latch-up condition occurs only during the power-up
sequence when the 5V supply comes up before the 3.3V
supply. The Lattice 3.3V ispLSI devices are guaranteed
to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V.
U
The recommended power-up options are as follows:
Option 1: Ensure that the 3.3V supply is powered-up and
stable before the 5V supply is powered up.
Option 2: Ensure that the 5V device outputs are driven to
a high impedance or logic low state during power-up.
8
Specifications ispLSI 2064V
Pin Description
84-PIN PLCC
PIN NUMBERS
NAME
100-PIN TQFP
PIN NUMBERS
DESCRIPTION
20, Input/Output Pins — These are the general purpose I/O pins
26, used by the logic array.
30,
35,
43,
48,
53,
58,
70,
76,
80,
85,
93,
98,
3
8
26,
30,
34,
38,
45,
49,
53,
57,
68,
72,
76,
80,
3,
7,
11,
15
27,
31,
35,
39,
46,
50,
54,
58,
69,
73,
77,
81,
4
8,
12,
16,
GOE 0, GOE 1
64,
22
Y0, Y1, Y2
19,
67,
RESET
20
11
Active Low (0) Reset pin which resets all registers in the device.
ispEN
24
15
Input — Dedicated in-system programming enable input pin.
This pin is brought low to enable the programming mode. The
TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
25
16
TMS/IN 1
43
37
TDO/IN 2
1
TCK/IN 3
61
GND
23,
13
10,
65,
ES
IG
N
62,
19,
24,
29,
34,
42,
47,
52,
57,
69,
74,
79,
84,
92,
97,
2,
7,
D
18,
23,
28,
33,
41,
46,
51,
56,
68,
73,
78,
83,
91,
96,
1,
6,
Global Output Enable Input Pins
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all the GLBs in the device.
60
is
SE
NC1
66
VE
Input — This pin performs two functions. When ispEN is logic
low, it functions as an input pin to load programming data into the
device. TDI/IN 0 also is used as one of the two control pins for the
ISP state machine. When ispEN is high, it functions as a
dedicated input pin.
64
Input — This pin performs two functions. When ispEN is logic low,
it functions as a pin to control the operation of the ISP state
machine. When ispEN is high, it functions as a dedicated input
pin.
Output/Input — This pin performs two functions. When ispEN is
logic low, it functions as an output pin to read serial shift register
data. When ispEN is high, it functions as a dedicated input pin.
20
87
Input — This pin performs two functions. When ispEN is logic
low, it functions as a clock pin for the Serial Shift Register. When
ispEN is high, it functions as a dedicated input pin.
SI
59
44,
63,
84
14,
39,
61,
86
Ground (GND)
21,
42,
65
12,
36,
63,
89
Vcc
4,
31,
54,
75,
100
9,
38,
64,
81
21,
44,
66,
88,
25, No Connect.
50,
71,
94,
pL
2,
VCC
FO
R
62
17,
22,
27,
32,
40,
45,
49,
55,
67,
72,
77,
82,
90,
95,
99,
5,
EW
29,
33,
37,
41,
48,
52,
56,
60,
71,
75,
79,
83,
6,
10,
14,
18
N
28,
32,
36,
40,
47,
51,
55,
59,
70,
74,
78,
82,
5,
9,
13,
17,
S
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
U
1. NC pins are not to be connected to any active signals, VCC or GND.
9
Table 2-0002A/2064V
Specifications ispLSI 2064V
Pin Description
44-PIN TQFP
PIN NUMBERS
44-PIN PLCC
PIN NUMBERS
NAME
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
GOE 0/IN 3
2
40
This pin performs one of two functions. It can be programmed to
function as a Global Output Enable pin or a Dedicted Input pin.
GOE 1/Y0
11
5
This pin performs one of two functions. It can be programmed
to function as a Global Output Enable or a Dedicated Clock
input. This clock input is connected to one of the clock inputs of
all the GLBs on the device.
RESET/Y1
35
29
This pin performs one of two functions. It can be programmed
to function as a Dedicated Clock Input that is brought into the
Clock Distribution Network and can optionally be routed to any
GLB and/or I/O cell on the device, or as an Active Low (0)
Reset pin which resets all of the GLB and I/O registers in the
device.
ispEN
13
7
Input — Dedicated in-system programming enable input pin.
This pin is brought low to enable the programming mode. The
TMS, TDI, TDO and TCK controls become active.
TDI/IN 0
14
8
TMS/IN 2
36
30
TDO/IN 1
24
TCK/Y2
33
S
9,
13,
19,
23,
31,
35,
41,
1,
ES
IG
N
18,
22,
28,
32,
40,
44,
6,
10
D
17,
21,
27,
31,
39,
43,
5,
9,
DESCRIPTION
15,
19,
25,
29,
37,
41,
3,
7,
R
N
EW
16,
20,
26,
30,
38,
42,
4,
8,
Input/Output Pins — These are the general purpose I/O pins
used by the logic array.
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
VE
FO
Input — This pin performs two functions. When ispEN is logic
low, it functions as an input pin to load programming data into
the device. TDI/IN 0 also is used as one of the two control pins
for the ISP state machine. When ispEN is high, it functions as a
dedicated input pin.
64
Input — This pin performs two functions. When ispEN is logic
low, it functions as a pin to control the operation of the ISP
state machine. When ispEN is high, it functions as a dedicated
input pin.
Output/Input — This pin performs two functions. When ispEN is
logic low, it functions as an output pin to read serial shift register
data. When ispEN is high, it functions as a dedicated input pin.
20
18
Input — This pin performs two functions. When ispEN is logic
low, it functions as a clock pin for the Serial Shift Register.
When ispEN is high, it functions as a dedicated clock input. This
clock input is brought into the Clock Distribution Network, and
can optionally be routed to any GLB and/or I/O cell on the
device.
pL
SI
27
12,
23
17,
39
Ground (GND)
34
6,
28
Vcc
Table 2-0002B/2064V
U
SE
VCC
1,
is
GND
10
Specifications ispLSI 2064V
Pin Configuration
ES
IG
N
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
20
64
VE
FO
R
Top View
N
ispLSI 2064V
EW
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC1
I/O 38
I/O 37
I/O 36
NC1
I/O 35
I/O 34
I/O 33
I/O 32
NC1
Y1
NC1
VCC
GOE 0
GND
Y2
TCK/IN 3
I/O 31
I/O 30
I/O 29
I/O 28
NC1
I/O 27
I/O 26
I/O 25
pL
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
1NC
I/O 12
I/O 13
I/O 14
I/O 15
VCC
TMS/IN 1
1NC
GND
I/O 16
I/O 17
I/O 18
I/O 19
1NC
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1NC
SI
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O 57
I/O 58
I/O 59
1NC
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
RESET
VCC
GOE 1
GND
ispEN
TDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
1NC
I/O 4
I/O 5
I/O 6
1NC
S
NC1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
NC1
I/O 51
I/O 50
I/O 49
I/O 48
VCC
NC1
TDO/IN 2
GND
I/O 47
I/O 46
I/O 45
I/O 44
NC1
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
ispLSI 2064V 100-Pin TQFP Pinout Diagram
is
100 TQFP/2064V
U
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
11
Specifications ispLSI 2064V
Pin Configuration
12
I/O 58
I/O 59
13
I/O 60
15
I/O 61
16
I/O 62
I/O 63
17
Y0
19
RESET
20
VCC
GOE 1
21
GND
23
ispEN
24
TDI/IN 0
25
I/O 0
I/O 1
26
I/O 2
28
I/O 3
29
I/O 4
I/O 5
I/O 6
30
4
2
I/O 41
I/O 40
I/O 39
I/O 42
I/O 43
I/O 44
I/O 45
1 84 83 82 81 80 79 78 77 76 75
EW
D
14
72
I/O 37
I/O 36
71
I/O 35
70
I/O 34
69
I/O 33
68
I/O 32
Y1
64
NC1
VCC
GOE 0
63
GND
62
61
Y2
TCK/IN 3
60
I/O 31
59
I/O 30
58
I/O 29
57
I/O 28
56
I/O 27
55
I/O 26
I/O 25
R
FO
VE
64
20
SI
54
pL
32
73
65
Top View
31
I/O 38
66
ispLSI 2064V
27
74
67
N
18
22
S
5
I/O 46
3
6
I/O 47
7
GND
I/O 48
VCC
TDO/IN 2
8
ES
IG
N
I/O 57
I/O 52
I/O 51
I/O 50
I/O 49
11 10 9
I/O 53
I/O 55
I/O 54
I/O 56
ispLSI 2064V 84-Pin PLCC Pinout Diagram
U
1. NC pins are not to be connected to any active signal, VCC or GND.
12
I/O 24
I/O 23
I/O 21
I/O 22
I/O 19
I/O 20
I/O 17
I/O 18
I/O 16
GND
VCC
TMS/IN 1
I/O 15
I/O 12
I/O 13
I/O 14
I/O 11
I/O 9
I/O 7
I/O 8
I/O 10
SE
is
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
84 PLCC/2064V
Specifications ispLSI 2064V
I/O 21
I/O 20
I/O 19
I/O 22
I/O 23
GOE 0/IN 3
I/O 24
I/O 26
I/O 25
I/O 27
ispLSI 2064V 44-Pin PLCC Pinout Diagram
GND
Pin Configuration
I/O 18
38
I/O 17
I/O 30
9
37
I/O 16
I/O 31
10
11
36
TMS/IN 2
GOE1/Y0
VCC
ES
IG
N
7
8
39
I/O 29
I/O 28
S
6 5 4 3 2 1 44 43 42 41 40
12
ispLSI 2064V
35
34
RESET/Y1
VCC
Top View
13
33
TCK/Y2
14
32
I/O 15
I/O 0
15
31
I/O 1
I/O 2
16
17
I/O 14
I/O 13
EW
D
ispEN
TDI/IN 0
30
29
I/O 12
N
R
I/O 8
TDO/IN 1
I/O 9
I/O 10
I/O 11
44 PLCC/2064V
FO
GND
I/O 7
I/O 6
I/O 4
I/O 5
I/O 3
18 19 20 21 22 23 24 25 26 27 28
VE
Pin Configuration
SI
I/O 29
I/O 30
I/O 31
GOE1/Y0
VCC
I/O 21
I/O 20
I/O 19
I/O 22
GND
I/O 23
GOE 0/IN 3
I/O 24
I/O 26
I/O 25
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
ispLSI 2064V
6
Top View
33
I/O 18
32
31
I/O 17
I/O 16
30
TMS/IN 2
29
28
RESET/Y1
VCC
ispEN
7
27
TCK/Y2
TDI/IN 0
8
26
I/O 15
9
10
11
25
24
23
I/O 14
I/O 13
I/O 12
I/O 9
I/O 10
I/O 11
I/O 8
GND
TDO/IN 1
I/O 7
I/O 6
12 13 14 15 16 17 18 19 20 21 22
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
U
SE
is
pL
I/O 28
I/O 27
20
64
ispLSI 2064V 44-Pin TQFP Pinout Diagram
44 TQFP/2064V
13
Specifications ispLSI 2064V
Part Number Description
ispLSI
2064V – XXX X
XXX X
Device Family
Grade
Blank = Commercial
I = Industrial
S
Device Number
Package
T100 = 100-Pin TQFP
J84 = 84-Pin PLCC
J44 = 44-Pin PLCC
T44 = 44-Pin TQFP
Power
L = Low
D
ES
IG
N
Speed
100 = 100 MHz fmax
80 = 80 MHz fmax
60 = 60 MHz fmax
EW
ispLSI 2064V Ordering Information
COMMERCIAL
I/Os
ORDERING NUMBER
PACKAGE
7.5
64
ispLSI 2064V-100LJ84
84-Pin PLCC
100
7.5
64
ispLSI 2064V-100LT100
100-Pin TQFP
100
7.5
32
ispLSI 2064V-100LJ44
44-Pin PLCC
100
7.5
32
ispLSI 2064V-100LT44
44-Pin TQFP
80
10
64
ispLSI 2064V-80LJ84
84-Pin PLCC
80
10
64
ispLSI 2064V-80LT100
100-Pin TQFP
80
10
32
ispLSI 2064V-80LJ44
44-Pin PLCC
80
10
32
ispLSI 2064V-80LT44
44-Pin TQFP
60
15
64
ispLSI 2064V-60LJ84
84-Pin PLCC
60
15
64
ispLSI 2064V-60LT100
100-Pin TQFP
60
15
32
ispLSI 2064V-60LJ44
44-Pin PLCC
60
15
32
ispLSI 2064V-60LT44
44-Pin TQFP
pL
R
FO
VE
64
INDUSTRIAL
tpd (ns)
I/Os
ORDERING NUMBER
PACKAGE
60
15
64
ispLSI 2064V-60LT100I
100-Pin TQFP
60
15
32
ispLSI 2064V-60LT44I
44-Pin TQFP
Table 2-0041B/2064V
U
SE
ispLSI
Table 2-0041A/2064V
fmax (MHz)
is
FAMILY
N
tpd (ns)
100
SI
ispLSI
fmax (MHz)
20
FAMILY
0212/2064V
14
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