(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8) CLOCK GENERATION CHIP FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system. 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM Q0 1 Q0 16 VCC Q ÷1 or ÷2 2 R Q VCC 3 15 EN 14 F SEL D R Q1 4 13 CLK Q Q1 5 ÷2 or ÷4 12 CLK R VCC 6 Q2 11 VBB 7 10 MR 9 VEE Q Q2 8 ClockWorks™ SY100S834 SY100S834L ÷4 or ÷8 R SOIC TOP VIEW PIN NAMES TRUTH TABLE Pin CLK Function Differential Clock Inputs CLK EN MR Z L L Divide Function ZZ H L Hold Q0–2 X X H Reset Q0–2 FSEL Function Select EN Synchronous Enable MR Master Reset VBB Reference Output Q0 Differential ÷1 or ÷2 Outputs Q1 Differential ÷2 or ÷4 Outputs FSEL Q0 Outputs Q1 Outputs Q2 Outputs Q2 Differential ÷4 or ÷8 Outputs L Divide by 2 Divide by 4 Divide by 8 H Divide by 1 Divide by 2 Divide by 4 NOTES: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition Rev.: F 1 Amendment: /0 Issue Date: September, 1999 ClockWorks™ SY100S834 SY100S834L Micrel DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — — 49 — — 49 — — 49 — — 54 mA — -1.26 V — 150 µA IEE Power Supply Current VBB Output Reference Voltage -1.38 — -1.26 -1.38 — -1.26 -1.38 — IIH Input HIGH Current — 150 — — 150 — — — NOTE: 1. Parametric values specified at: TA = +85°C 5 volt Power Supply Range 3 volt Power Supply Range 100S834 Series: 100S834L Series -1.26 -1.38 150 — -4.2V to -5.5V. -3.0V to -3.8V. AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (Min.) to VEE (Max.); VCC = GND TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 960 650 1100 800 1200 1010 960 650 1100 1200 800 1010 960 650 1100 800 1200 1010 960 650 1100 800 1200 1010 ps — — 50 — — 50 — — 50 — — 50 ps 400 — — 400 — — 400 — — 400 — — ps tPLH tPHL Propagation Delay to Output tskew Within-Device Skew(2) tS Set-up Time EN tH Hold Time EN 200 — — 200 — — 200 — — 200 — — ps VPP Minimum Input Swing 250 — — 250 — — 250 — — 250 — — mV VCMR Common Mode Range(3) CLK –1.3 — –0.4 –1.4 — –0.4 –1.4 — –0.4 –1.4 — –0.4 V 275 400 525 275 400 525 275 400 525 275 400 525 ps tr tf CLK MR TA = 0°C Output Rise/Fall Times Q (20% – 80%) NOTES: 1. Parametric values specified at: 5 volt Power Supply Range 100S834 Series: -4.2V to -5.5V. 3 volt Power Supply Range 100S834L Series -3.0V to -3.8V. 2. Within-Device Skew is specified for identical transition. 3. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I. 2 ClockWorks™ SY100S834 SY100S834L Micrel TIMING DIAGRAM Internal Clock Disabled Internal Clock Enabled CLK FSEL = 0 Q0 Q1 Q2 FSEL = 1 Q0 Q1 Q2 EN The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. PRODUCT ORDERING CODE Package Type Operating Range VEE Range (V) Ordering Code SY100S834ZC Z16-2 Commercial -4.2 to -5.5 SY100S834ZCTR Z16-2 Commercial SY100S834LZC Z16-2 SY100S834LZCTR Z16-2 Ordering Code Package Type Operating Range VEE Range (V) SY100S834ZI Z16-2 Industrial -4.2 to -5.5 -4.2 to -5.5 SY100S834ZITR Z16-2 Industrial -4.2 to -5.5 Commercial -3.0 to -3.8 SY100S834LZI Z16-2 Industrial -3.0 to -3.8 Commercial -3.0 to -3.8 SY100S834LZITR Z16-2 Industrial -3.0 to -3.8 3 ClockWorks™ SY100S834 SY100S834L Micrel 16 LEAD SOIC .150" WIDE (Z16-2) Rev. 02 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4