Samsung K6R4016C1D-KI10 1mx4 bit high speed static ram(5.0v operating) Datasheet

PRELIMINARY
CMOS SRAM
K6R4004C1D
Document Title
1Mx4 Bit High Speed Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No.
History
Rev. 0.0
Initial release with Preliminary.
September. 7. 2001
Preliminary
Rev. 0.1
Change Icc. Isb and Isb1
November, 3. 2001
Preliminary
November, 3. 2001
Preliminary
Draft Data
Item
ICC(Commercial)
ICC(Industrial)
10ns
12ns
15ns
10ns
12ns
15ns
ISB
ISB1
Previous
90mA
80mA
70mA
115mA
100mA
85mA
30mA
10mA
Current
65mA
55mA
45mA
85mA
75mA
65mA
20mA
5mA
Rev. 0.2
1. Correct AC parameters : Read & Write Cycle mA
2. Delete Low Ver.
3. Delete Data Retention Characteristics
Rev. 0.3
1. Delete 15ns speed bin.
2. Change Icc for Industrial mode.
Item
10ns
ICC(Industrial)
12ns
Rev. 1.0
Rev. 2.0
Remark
Previous
85mA
75mA
Current
75mA
65mA
December, 18. 2001
Preliminary
1. Final datasheet release.
2. Delete 12ns speed bin.
3. Delete UB,LB releated AC characteristics and timing diagram.
4. Correct Read Cycle time waveform(2).
July, 09, 2002
Final
1. Add the Lead Free Package type.
July. 26, 2004
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
4Mb Async. Fast SRAM Ordering Information
Org.
Part Number
VDD(V)
Speed ( ns )
5
10
K6R4004V1D-J(K)C(I) 08/10
3.3
8/10
K6R4008C1D-J(K,T,U)C(I) 10
5
10
K6R4008V1D-J(K,T,U)C(I) 08/10
3.3
8/10
K6R4016C1D-J(K,T,U,E)C(I) 10
5
10
3.3
8/10
K6R4004C1D-J(K)C(I) 10
1M x4
512K x8
256K x16
K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10
-2-
PKG
Temp. & Power
J : 32-SOJ
K : 32-SOJ(LF)
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
J : 36-SOJ
K : 36-SOJ(LF)
,Normal Power Range
T : 44-TSOP2
L : Commercial Temperature
U : 44-TSOP2(LF)
,Low Power Range
P : Industrial Temperature
J : 44-SOJ
,Low Power Range
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
1M x 4 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating K6R4004C1D-10 : 65mA(Max.)
Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4004C1D-J : 32-SOJ-400
K6R4004C1D-K : 32-SOJ-400(Lead-Free)
• Operating in Commercial and Industrial Temperature range.
The K6R4004C1D is a 4,194,304-bit high-speed Static Random
Access Memory organized as 1,048,576 words by 4 bits. The
K6R4004C1D uses 4 common input and output lines and has an
output enable pin which operates faster than address access
time at read cycle. The device is fabricated using SAMSUNG′s
advanced CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in high-density
high-speed system applications. The K6R4004C1D is packaged
in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1~I/O4
Pre-Charge Circuit
Row Select
Clk Gen.
Memory Array
1024 Rows
1024 x 4 Columns
Data
Cont.
I/O Circuit
Column Select
A0
1
32
A19
A1
2
31
A18
A2
3
30
A17
A3
4
29
A16
A4
5
28
A15
CS
6
27
OE
I/O1
7
26 I/O4
Vcc
8
SOJ
Vss
24
Vcc
Vss
9
I/O2
10
23 I/O3
WE
11
22
A14
A5
12
21
A13
A6
13
20
A12
A7
14
19
A11
A8
15
18
A10
A9
16
17 N.C
PIN FUNCTION
Pin Name
CLK
Gen.
A0 - A19
A10
25
A12 A14 A16 A18
A11 A13 A15 A17 A19
Pin Function
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
CS
I/O1 ~ I/O4
WE
VCC
Power(+5.0V)
OE
VSS
Ground
N.C
No Connection
-3-
Data Inputs/Outputs
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Rating
Unit
VIN, VOUT
-0.5 to VCC+0.5
V
Voltage on VCC Supply Relative to VSS
VCC
-0.5 to 7.0
V
Power Dissipation
PD
1.0
W
Voltage on Any Pin Relative to VSS
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Industrial
TA
-40 to 85
°C
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Parameter
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC+0.5**
V
Input Low Voltage
VIL
-0.5*
-
0.8
V
* The above parameters are also guaranteed at industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Symbol
Test Conditions
Min
Max
Unit
ILI
VIN=VSS to VCC
-2
2
µA
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Com.
10ns
-
65
Ind.
10ns
-
75
Min. Cycle, CS=VIH
-
20
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
5
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
Operating Current
Standby Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
ISB
mA
mA
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Symbol
Test Conditions
TYP
Max
Unit
Input/Output Capacitance
Item
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
6
pF
* Capacitance is sampled and not 100% tested.
-4-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at industrial temperature range.
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
Output Loads(A)
+5.0V
RL = 50Ω
DOUT
480Ω
VL = 1.5V
DOUT
30pF*
ZO = 50Ω
255Ω
* Capacitive Load consists of all components of the
test environment.
5pF*
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Symbol
K6R4004C1D-10
Min
Max
Unit
Read Cycle Time
tRC
10
-
ns
Address Access Time
tAA
-
10
ns
Chip Select to Output
tCO
-
10
ns
Output Enable to Valid Output
tOE
-
5
ns
Chip Enable to Low-Z Output
tLZ
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
ns
tHZ
0
5
ns
Output Disable to High-Z Output
tOHZ
0
5
ns
Output Hold from Address Change
tOH
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
ns
Chip Disable to High-Z Output
* The above parameters are also guaranteed at industrial temperature range.
-5-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
WRITE CYCLE*
Parameter
K6R4004C1D-10
Symbol
K6R4004C1D-12
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
10
-
12
-
ns
Chip Select to End of Write
tCW
7
-
8
-
ns
Address Set-up Time
tAS
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
ns
Write Pulse Width(OE Low)
tWP1
10
-
12
-
ns
Write Recovery Time
tWR
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
5
0
6
ns
Data to Write Time Overlap
tDW
5
-
6
-
ns
Data Hold from Write Time
tDH
0
-
0
-
ns
End of Write to Output Low-Z
tOW
3
-
3
-
ns
* The above parameters are also guaranteed at industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tOHZ
tOE
OE
tOLZ
Data out
High-Z
VCC
ICC
Current
ISB
tDH
tLZ(4,5)
Valid Data
tPU
tPD
50%
50%
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-6-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tAW
CS
tWR(5)
tCW(3)
tAS(4)
tWP1(2)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
High-Z(8)
Data out
(10)
(9)
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
Valid Data
tLZ
Data out
tDH
High-Z
tWHZ(6)
High-Z(8)
High-Z
-7-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
H
X
X*
L
H
H
L
H
L
L
L
X
Mode
I/O Pin
Supply Current
Not Select
High-Z
ISB, ISB1
Output Disable
High-Z
ICC
Read
DOUT
ICC
Write
DIN
ICC
* X means Don′t Care.
-8-
Rev. 2.0
July 2004
PRELIMINARY
CMOS SRAM
K6R4004C1D
PACKAGE DIMENSIONS
Units:millimeters/Inches
32-SOJ-400
#32
10.16
0.400
#17
11.18 ±0.12
0.440 ±0.005
9.40 ±0.25
0.370 ±0.010
0.20
#1
0.69
0.027 MIN
21.36 MAX
0.841
20.95 ±0.12
0.825 ±0.005
( 1.30 )
0.051
( 1.30 )
0.051
( 0.95 )
0.0375
0.43
+0.10
-0.05
0.017 +0.004
-0.002
1.27
0.050
+0.10
-0.05
0.008 +0.004
-0.002
#16
0.71
3.76 MAX
0.148
0.10
MAX
0.004
+0.10
-0.05
0.028 +0.004
-0.002
-9-
Rev. 2.0
July 2004
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