NSC CLC109ALC Low-power, wideband, closed-loop buffer Datasheet

N
CLC109
Low-Power, Wideband, Closed-Loop Buffer
General Description
Features
The CLC109 is a high-performance, closed-loop monolithic buffer
intended for power sensitive applications. Requiring only 35mW of
quiescent power (±5V supplies), the CLC109 offers a high bandwidth
of 270MHz (0.5Vpp) and a slew rate of 350V/µs. Even with this
minimal dissipation, the CLC109 can easily drive a demanding
100Ω load. The buffer specifications are for a 100Ω load.
■
With its patented closed-loop topology, the CLC109 has significant
performance advantages over conventional open-loop designs.
Applications requiring low (2.8Ω) output impedance and nearly
ideal unity gain (0.997) through very high frequencies will benefit
from the CLC109's superior performance. Power sensitive
applications will benefit from the CLC109's excellent performance
on reduced or single supply voltages.
■
■
■
■
■
High small-signal bandwidth (270MHz)
Low supply current (3.5mA @ ±5V)
Low output impedance (2.8Ω)
350V/µs slew rate
Single supply operation (0 to 3V supply min.)
Evaluation boards and Spice models
Applications
■
■
■
■
■
■
Video switch buffers
Test point drivers
Low power active filters
DC clamping buffer
High-speed S & H circuits
Inverting op amp input buffer
Constructed using an advanced, complementary bipolar process
and Comlinear's proven high-performance architectures, the
CLC109 is available in several versions to meet a variety of
requirements.
CLC109AJP
CLC109AJE
CLC109ALC
CLC109AMC
CLC109
Low-Power, Wideband, Closed-Loop Buffer
June 1999
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
8-pin Plastic DIP
8-pin Plastic SOIC
dice
dice qualified to Method 5008,
MIL-STD-883, Level B
CLC109AJM5 -40°C to +85°C
5-pin SOT
Contact factory for other packages and DESC SMD number.
Vo
PINOUT
SOT23-5
VCC
PINOUT
VEE
Vnon-inv
DIP & SOIC
Vinv
Typical Application
CLC109
Single-Supply Circuit
 1999 National Semiconductor Corporation
Printed in the U.S.A.
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CLC109 Electrical Characteristics (±V = ± 5V, R = 100ΩΩ unless specified)
Ω)
±5V,, RL = 100
100Ω
CLC109 Electrical Characteristics (±Vcc = ±5V
CC
PARAMETER
Ambient Temperature
FREQUENCY RESPONSE
small signal bandwidth
gain flatness
flatness
peaking
rolloff
differential gain
differential phase
TIME DOMAIN RESPONSE
rise and fall time
settling time to ±0.05%
overshoot
slew rate
CONDITIONS
TYP
MIN/MAX RATINGS
UNITS
SYMBOL
150
70
MHz
MHz
SSBW
LSBW
±0.1
0.3
0.4
1.0
0.05
±0.1
0.3
0.6
1.0
0.1
dB
dB
dB
%
°
GFL
GFPH
GFRH
DG
DP
1.7
6
25
15
220
1.7
6
18
10
250
2.3
7
25
10
220
ns
ns
ns
%
V/µsec
TRS
TRL
TS
OS1
SR
-46
-55
-36
-50
-38
-50
-38
-45
dBc
dBc
HD2
HD3
3.3
1.3
4.1
3
4.1
2
4.5
2
nV/√Hz
pA/√Hz
VN
ICN
0.997
0.96
2.8
1
±10
±2
±30
-56
3.5
0.995
0.94
5.0
±8.2
±40
±8
±50
-48
4
0.995
0.95
4.0
±5
0.994
0.95
4.0
±6
±30
±4
±25
-46
4
V/V
V/V
Ω
mV
µV/°C
µA
nA/°C
dB
mA
GA1
GA2
RO
VIO
DVIO
IBN
DIBN
PSRR
ICC
0.5
1.5
2.5
1.25
4.0
+3.8,-2.5
1.0
0.7
0.3
1.0
3.5
3.5
2.0
2.0
3.6
3.8
+3.0,-1.2 +3.6,-2.0
+3.0,-1.6
+40,-12 +40,-20
+40,-16
0.6
2.0
3.5
2.0
3.8
+3.6,-2.5
%
MΩ
pF
pF
V
V
V
mA
mA
ILIN
RIN
CIN
CIN
VO
VOL
VOL
IO
IO
CLC109AJ
+25°C
-40°C
+25°C
+85°C
Vout < 0.5Vpp
Vout < 2.0Vpp
Vout < 0.5Vpp
DC-30MHz
DC-200MHz
DC-60MHz
4.43MHz, 150Ω load
4.43MHz, 150Ω load
270
120
200
90
200
90
0
0
0.1
0.7
0.03
±0.1
1.0
0.4
1.5
0.05
0.5V step
2.0V step
2.0V step
0.5V step
4V step
1.3
4.4
12
3
350
DISTORTION AND NOISE PERFORMANCE
2nd harmonic distortion
2Vpp, 20MHz
3rd harmonic distortion
2Vpp, 20MHz
equivalent output noise
voltage
current
STATIC DC PERFORMANCE
small signal gain
L
no load
100Ω load
DC
output resistance
*output offset voltage
average temperature coefficient
* input bias current
average temperature coefficient
power supply rejection ratio
* supply current
no load
MISCELLANEOUS PERFORMANCE
integral endpoint linearity
±1V, full scale
input resistance
input capacitance
CERDIP
Plastic DIP
output voltage range
no load
RL=100Ω
RL=100Ω, 0°C
output current
0°C
+60,-30
±4
-48
4
+40,-30
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
Vcc
Iout output is short circuit protected to
ground, but maximum reliability will be
maintained if Iout does not exceed...
input voltage
maximum junction temperature
operating temperature range
AJ
A8/AM/AL
storage temperature range
lead temperature (soldering 10 sec)
ESD rating
Miscellaneous Ratings
±7.0V
Notes:
*
30mA
±Vcc
+150°C
-40°C to +85°C
-55°C to +125°C
-65°C to +150°C
+300°C
1000V
AJ : 100% tested at +25°C.
Package Thermal Resistance
θJC
θJA
Plastic (AJP)
70°C/W
125°C/W
Surface Mount (AJE)
SOT
65°C/W
130°C/W
145°C/W
200°C/W
Package
Reliability Information
Transistor count
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17
Electrical Characteristics
PARAMETERS
(VCC=+3V or VCC=+5V, -Vee= 0V, TA=+25°C, RL = 100Ω
Ω , unless noted)
CONDITIONS
VCC = 3V
VCC = 5V
30
90
35
MHz
MHz
3
0
0.3
0
1.5
dB
dB
dB
13.9
4.7
13.5
0
200
ns
ns
%
V/µs
FREQUENCY DOMAIN RESPONSE
-3dB bandwidth
Vout < 0.5Vpp
Vout < 2.0Vpp
gain flatness
Vout < 0.5Vpp
flatness
DC to 30MHz
peaking
DC to 200MHz
rolloff
DC to 60MHz
TIME DOMAIN RESPONSE
rise and fall time
0.5V step
2.0V step
overshoot
0.5V step
slew rate
0.5V step
DISTORTION AND NOISE RESPONSE
0.5Vpp,20MHz
2nd harmonic distortion
1.0Vpp,20MHz
0.5Vpp,20MHz
3rd harmonic distortion
1.0Vpp,20MHz
STATIC DC PERFORMANCE
small-signal gain
supply current
AC-coupled
RL= ∞
MISCELLANEOUS PERFORMANCE
output voltage range
RL= ∞
RL=100Ω
0
35
-32
UNITS
-43
dBc
dBc
dBc
dBc
0.89
0.75
0.94
1.6
V/V
mA
1.5
1.1
2.8
2.6
Vpp
Vpp
-37
-29
Operation
The CLC109 is a low-power, high-speed unity-gain buffer.
It uses a closed-loop topology which allows for accuracy
not usually found in high-speed buffers. A closed-loop
design provides high accuracy and low output impedance
through a wide bandwidth.
+5V
C3
6.8µF
+
Vin
4
CLC109
Rin
Rin is chosen
for desired
input impedance.
Single Supply Operation
Although the CLC109 is specified to operate from split
±5V power supplies, there is no internal ground reference
that prevents operation from a single voltage power
supply. For single supply operation the input signal should
be biased at a DC value of ½V CC . This can be
accomplished by AC coupling and rebiasing as shown in
the "Typical Application" illustrations on the front page.
0.01µF
C1
1
2
3
8
6 7
Vout
Rout
5
C2
0.01µF
-5V
C4
6.8µF
+
Rout is chosen for
desired output impedance.
(CLC109 Ro= 2.8Ω )
Figure 1: Recommended circuit & evaluation
board schematic
This phase shift can decrease phase margin and increase
frequency response peaking. A small series resistor
inserted between pin 6 and the capacitance effectively
decouples this effect. The graphs on the following page
illustrate the required resistor value and the resulting
performance vs. capacitance.
The above electrical specifications provide typical
performance specifications for the CLC109 at 25°C while
operating from a single +3V or a single +5V power supply.
Printed Circuit Layout and Supply Bypassing
As with any high-frequency device, a good PCB layout is
required for optimum performance. This is especially
important for a device as fast as the CLC109.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products), which have low parasitic reactances,
were used to develop the data sheet specifications.
Precision carbon composition resistors or standard spirallytrimmed RN55D metal film resistors will work, though they
may cause a slight degradation of ac performance due to
their reactive nature at high frequencies.
To minimize capacitive feedthrough, pins 2, 3, 6, and 7
should be connected to the ground plane, as shown in
Figure 1. Input and output traces should be laid out as
transmission lines with the appropriate termination resistors
very near the CLC109. On a 0.065 inch epoxy PCB
material, a 50Ω transmission line (commonly called stripline)
can be constructed by using a trace width of 0.1" over a
complete ground plane.
Evaluation Boards
Evaluation boards are available from National as part
CLC730012 (DIP) and CLC730045 (SOIC). This board
was used in the characterization of the device and provides
optimal performance. Designers are encouraged to copy
these printed circuit board layouts for their applications.
Figure 1 shows recommended power supply bypassing.
Parasitic or load capacitance directly on the output of the
CLC109 will introduce additional phase shift in the device.
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CLC109
Low-Power, Wideband, Closed-Loop Buffer
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