÷2/4, ÷4/5/6 CLOCK ClockWorks™ SY100S839V FINAL GENERATION CHIP FEATURES ■ ■ ■ ■ ■ ■ DESCRIPTION The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device. If a singleended input is to be used, the VBB output should be connected to the /CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the S839V under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The common enable (/EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one S839V, the MR pin need not be exercised as the internal divider designs ensures synchronization between the ÷2/4, and the ÷4/5/6 outputs of a single device. 3.3V and 5V power supply option 50ps output-to-output skew 50% duty cycle outputs Synchronous enable/disable Master Reset for synchronization Internal 75KΩ input pull-down resistors ■ Available in 20-pin SOIC package VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE 20 19 18 17 16 15 14 13 12 11 9 10 DIVSELb1 DIVSELa PIN CONFIGURATION/BLOCK DIAGRAM 1 2 3 4 5 6 7 8 VCC EN DIVSELb0 TOP VIEW SOIC Z20-1 CLK CLK VBB MR VCC TRUTH TABLE CLK /EN MR Function Z L L Divide ZZ H L Hold Q0–3 X X H Reset Q0–3 NOTE: Z = LOW-to-HIGH transition ZZ = HIGH-to-LOW transition PIN NAMES DIVSELa Q0, Q1 OUTPUTS 0 Divide by 2 1 Divide by 4 Pin Function CLK Differential Clock Inputs /EN Synchronous Enable DIVSELb1 DIVSELb0 Q2, Q3 OUTPUTS MR Master Reset 0 0 Divide by 4 VBB Reference Output 0 1 Divide by 6 Q0, Q1 Differential ÷2/4 Outputs 1 0 Divide by 5 Q2, Q3 Differential ÷4/5/6 Outputs 1 1 Divide by 5 DIVSEL Frequency Select Input Rev.: A 1 Amendment: /0 Issue Date: May, 1999 ClockWorks™ SY100S839V Micrel DC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (min) to VEE (max); VCC = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — 50 95 — 50 95 — 50 95 — 54 95 mA –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26 –1.38 — –1.26 V — — IEE Power Supply Current VBB Output Reference Voltage IIH Input High Current VOH Output HIGH Voltage(2) –1085 –1005 VOL 150 — — 150 — — 150 — — 150 µA –880 –1025 –955 –880 –1025 –955 –880 –1025 –955 –880 mV Output LOW Voltage(2) –1830 –1695 –1555 –1810 –1705 –1620 –1810 –1705 –1620 –1810 –1705 –1620 mV VOHA Output HIGH Voltage(3) –1095 — — –1035 — — –1035 — — –1035 — — mV VOLA Output LOW Voltage(3) — — –1555 — — –1610 — — –1610 — — –1610 mV VIH Input HIGH Voltage –1165 — –880 –1165 — –880 –1165 — –880 –1165 — –880 mV VIL Input LOW Voltage –1810 — –1475 –1810 — –1475 –1810 — –1475 –1810 — –1475 mV 0.5 — — — µA IIL Input LOW Current(4) — 0.5 — NOTE: 1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V. 2. VIN = VIH(Max) or VIL(Min): Loading with 50Ω to –2.0V. 3. VIN = VIH(Min) or VIL(Max): Loading with 50Ω to –2.0V. 4. VIN = VIL(Min). 2 — 0.5 — — 0.5 ClockWorks™ SY100S839V Micrel AC ELECTRICAL CHARACTERISTICS(1) VEE = VEE (min) to VEE (max); VCC = GND TA = –40°C Symbol Parameter TA = 0°C TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit MHz fMAX Maximum Toggle Frequency 1000 — — 1000 — — 1000 — — 1000 — — tPLH tPHL Propagation Delay to Output CLK ➝ Output (Diff.) CLK ➝ Output (S.E.) MR ➝ Output 725 675 600 — — — 925 975 900 725 675 600 — — — 925 975 900 725 675 610 — — — 925 975 910 725 675 630 — — — 925 975 930 tskew Within-Device Skew(2) Q0 — Q3 — — 50 — — 50 — — 50 — — 50 Part-to-Part Q0 — Q3 (Diff.) — — 200 — — 200 — — 200 — — 200 tS Set-up Time /EN ➝ /CLK DIVSEL ➝ CLK 250 400 — — — — 250 400 — — — — 250 400 — — — — 250 400 — — — — ps tH Hold Time /CLK ➝ /EN CLK ➝ DIVSEL 100 150 — — — — 100 150 — — — — 100 150 — — — — 100 150 — — — — ps VPP Minimum Input Swing(3) 250 — — 250 — — 250 — — 250 — — mV -1.6 — -0.4 -1.7 — -0.4 -1.7 — -0.4 -1.7 — -0.4 V — — 100 — — 100 — — 100 — — 100 ps CLK MR 500 700 — — — — 500 700 — — — — 500 700 — — — — 500 700 — — — — ps Q 280 — 550 280 — 550 280 — 550 280 — 550 ps VCMR Common Mode tRR Reset Recovery Time tPW Minimum Pulse Width tr Output Rise/Fall Times (20% —80%) tf CLK Range(4), (5) ps ps NOTES: 1. Parametric values specified at: -3.0V to -3.8V or -4.2V to -5.5V. 2. Skew is measured between outputs under identical transitions. 3. Minimum input swing for which AC parameters are guaranteed. The device will function reliably with differential inputs down to 100mV. 4. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I. 5. Duty Cycle: (Min. 48%; Max. 52%) } over temp. 3 ClockWorks™ SY100S839V Micrel LOGIC DIAGRAM DIVSELa (÷ 2/4) Q0 Q0 CLK R CLK Q1 Q1 EN (÷4/5/6) VBB R Q2 Q2 Q3 MR Q3 DIVSELb0 DIVSELb1 TIMING DIAGRAMS CLK Q (÷ 2) Q (÷ 4) Q (÷ 5) Q (÷ 6) PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY100S839VZC Z20-1 Commercial SY100S839VZCTR Z20-1 Commercial 4 ClockWorks™ SY100S839V Micrel 20 LEAD SOIC .300" WIDE (Z20-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 5