Catalyst CAT524 Configured digitally programmable potentiometer (dppâ ¢): programmable voltage application Datasheet

CAT524
Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications
FEATURES
APPLICATIONS
■ Four 8-bit DPPs configured as programmable
■ Automated product calibration
voltage sources in DAC-like applications
■ Remote control adjustment of equipment
■ Common reference inputs
■ Offset, gain and zero adjustments in
■ Buffered wiper outputs
self-calibrating and adaptive control systems
■ Non-volatile NVRAM memory wiper storage
■ Tamper-proof calibrations
■ Output voltage range includes both supply rails
■ DAC (with memory) substitute
■ 4 independently addressable buffered
output wipers
■ 1 LSB accuracy, high resolution
■ Serial µP interface
■ Single supply operation: 2.7V-5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
the stored settings, and stored settings can be read back
without disturbing the DPP’s output.
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The CAT524 is controlled with a simple 3 wire serial
interface. A Chip Select pin allows several devices to
share a common serial interface. Communication back
to the host controller is via a single serial data line thanks
to the Tri-Stated CAT524 Data Output pin. A RDY/BSY
output working in concert with an internal low voltage
detector signals proper operation of the non-volatile
NVRAM memory Erase/Write cycle.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are not
lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can
be dithered to test new output values without effecting
The CAT524 is available in the 0 to 70° C commercial
and –40° C to 85° C industrial operating temperature
ranges. Both 14-pin plastic DIP and SOIC packages are
offered.
FUNCTIONAL DIAGRAM
RDY/BSY
3
V
DD
PIN CONFIGURATION
V
H
REF
1
14
DIP Package (P)
PROG
7
PROGRAM
CONTROL
+
13
–
DI
5
+
12
–
CLK
2
SERIAL
CONTROL
VOUT2
VDD
1
14
CLK
2
13
RDY/BSY
3
CS
NVRAM
+
CS
V
1
OUT
11
–
4
DI
DO
V
3
OUT
PROG
+
10
–
SERIAL
DATA
OUTPUT
REGISTER
12
CAT
4
11
524
5
10
6
9
7
8
SOIC Package (J)
VREFH
VOUT1
VDD
CLK
1
14
2
13
VREFH
VOUT1
VOUT2
RDY/BSY
3
VOUT3
VOUT 4
VREF L
CS
DI
DO
12
4 CAT 11
524
5
10
6
9
VOUT 2
VOUT 3
VOUT 4
VREF L
7
GND
GND
PROG
8
VOUT4
6
DO
CAT524
9
8
GND
V
L
REF
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25076-00 4/01 M-1
CAT524
ABSOLUTE MAXIMUM RATINGS*
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
Supply Voltage
VDD to GND ...................................... –0.5V to +7V
Inputs
CLK to GND ............................ –0.5V to VDD +0.5V
CS to GND .............................. –0.5V to VDD +0.5V
DI to GND ............................... –0.5V to VDD +0.5V
PROG to GND ........................ –0.5V to VDD +0.5V
VREFH to GND ........................ –0.5V to VDD +0.5V
VREFL to GND ......................... –0.5V to VDD +0.5V
Outputs
D0 to GND ............................... –0.5V to VDD +0.5V
VOUT 1– 4 to GND ................... –0.5V to VDD +0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix) ...................... – 40°C to +85°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
VZAP(1)
ILTH(1)(2)
ESD Susceptibility
Latch-Up
2000
100
Max
Units
Test Method
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
DC ELECTRICAL CHARACTERISTICS:
VDD = +2.7 to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Resolution
Min
Typ
Max
Units
8
—
—
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±1
±1
±2
±2
± 0.5
± 0.5
± 1.5
± 1.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
—
—
2
0
—
—
—
—
10
–10
VDD
0.8
µA
µA
V
V
2.7
GND
—
—
—
7
VDD
VDD -2.7
—
V
V
kΩ
VDD –0.3
—
—
—
—
0.4
V
V
—
—
0.4
V
Accuracy
INL
Integral Linearity Error
DNL
Differential Linearity Error
ILOAD = 10 µA
ILOAD = 10 µA
ILOAD = 40 µA
ILOAD = 40 µA
ILOAD = 10 µA
ILOAD = 10 µA
ILOAD = 40 µA
ILOAD = 40 µA
TR = C
TR = I
TR = C
TR = I
TR = C
TR = I
TR = C
TR = I
Logic Inputs
IIH
IIL
VIH
VIL
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
VIN = VDD
VIN = 0V
References
VRH
VRL
ZIN
VREFH Input Voltage Range
VREFL Input Voltage Range
VREFH–VREFL Resistance
Logic Outputs
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
IOH = – 40 µA
IOL = 1 mA, VDD = +5V
IOL = 0.4 mA, VDD = +3V
Doc. No. 25076-00 Rev. 4/01 M-1
2
CAT524
DC ELECTRICAL CHARACTERISTICS (Cont.):
VDD = +2.7V to +5.5V , VREFH = +VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.99 VR
—
—
—
—
—
0.995 VR
0.005 VR
—
—
—
—
—
0.01 VR
1
100
150
1
V
V
µA
kΩ
kΩ
LSB / V
VREFH = +5V, VREFL = 0V
—
—
200
µV/ °C
VDD = +5V, ILOAD = 250nA
VREFH to VREFL
—
700
—
—
—
—
2.7
400
1600
1000
—
600
2500
1600
5.5
µA
µA
µA
V
Min
Typ
Max
Units
150
100
0
50
50
—
—
—
—
—
700
150
500
300
DC
—
—
—
—
—
—
—
400
4
400
—
—
—
—
—
—
—
—
—
—
150
150
—
5
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
MHz
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
—
—
3
6
10
10
µs
µs
VIN = 0V, f = 1 MHz(2)
VOUT = 0V, f = 1 MHz(2)
—
—
8
6
—
—
pF
pF
Analog Output
FSO
ZSO
IL
ROUT
Full-Scale Output Voltage
Zero-Scale Output Voltage
DAC Output Load Current
DAC Output Impedance
PSSR
Power Supply Rejection
VR = VREFH–VREFL
VR = VREFH–VREFL
VDD = +5V
VDD = +3V
ILOAD = 250 nA
Temperature
TCO
VOUT Temperature Coefficient
TCREF
Temperature Coefficient of
VREF Resistance
ppm / °C
Power Supply
IDD1
IDD2
Supply Current (Read)
Supply Current (Write)
VDD
Operating Voltage Range
Normal Operating
VDD=5V
VDD=3V
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Digital
tCSMIN
tCSS
tCSH
tDIS
tDIH
tDO1
tDO0
tHZ
tBusy
tLZ
tPROG
tPS
tCLKH
tCLKL
fC
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Erase/Write Cycle Time
Output Delay to Low-Z
Erase/Write Pulse Width
PROG Setup Time
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
CL = 100 pF,
see note 1
Analog
tDS
DAC Settling Time to 1/2 LSB
Pin Capacitance
CIN
COUT
Input Capacitance
Output Capacitance
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 25076-00 Rev. 4/01
Doc. No. 25076-00 Rev. 4/01 M-1
4
RDY/BSY
PROG
DO
DI
CS
CLK
to
to
t LZ
t DIS
t CSS
1
1
t DO1
t DIH
2
2
t CLK H
3
t PROG
t PS
t CLK L
3
t DO0
4
t BUSY
t CSH
4
t HZ
t CSMIN
5
5
FROM
TIMING
TO
Rising CS edge to D0 becoming high
low impedance (active output)
t LZ
Rising PROG edge to next rising
CLK edge
Falling CS edge to D0 becoming high
impedance (Tri-State)
t BUSY Falling CLK edge after PROG=H to
rising RDY/BSY edge
t PROG Rising PROG edge to falling
PROG edge
t PS
t HZ
Rising CLK edge to D0 = high
Rising CLK edge to D0 = low
t DO0
t DO1
Rising CLK edge to end of data valid
t DIH
Max
Min
Min
(Max)
Max
(Max)
Max
Min
Min
Data valid to first rising CLK
edge after CS = high
t DIS
Min
Min
Rising CS edge to next rising CLK edge
t CSMIN Falling CS edge to rising CS edge
t CSS
Min
t CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
Min
Min
MIN/MAX
t CLK L Falling CLK edge to CLK rising edge
t CLK H Rising CLK edge to falling CLK edge
PARAM
NAME
CAT524
A. C. TIMING DIAGRAM
CAT524
PIN DESCRIPTION
Pin
Name
1
2
3
4
5
6
7
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
8
9
10
11
12
13
14
GND
VREFL
VOUT4
VOUT3
VOUT2
VOUT1
VREFH
DAC addressing is as follows:
Function
Power supply positive.
Clock input pin.Clock input pin.
Ready/Busy Output
Chip Select
Serial data input pin.
Serial data output pin.
EEPROM Programming Enable
Input
Power supply ground.
Minimum DAC output voltage.
DAC output channel 4.
DAC output channel 3.
DAC output channel 2.
DAC output channel 1.
Maximum DAC output voltage.
DEVICE OPERATION
DAC OUTPUT
A0
A1
VOUT1
0
0
VOUT2
1
0
VOUT3
0
1
VOUT4
1
1
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high impedance Tri-State mode.
The CAT524 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without changing the stored output setting, which is useful for testing
new output settings before storing them in memory.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT524’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
DIGITAL INTERFACE
The CAT524 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
No clock is necessary upon system power-up. The
CAT524’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
CHIP SELECT
Chip Select (CS) enables and disables the CAT524’s
read and write operations. When CS is high data may be
5
Doc. No. 25076-00 Rev. 4/01
CAT524
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
VREF
VREF, the voltage applied between pins VREFH andVREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span the
full power supply range or just a fraction of it. In typical
applications VREFH andVREFL are connected across the
power supply rails. When using less than the full supply
voltage VREFH is restricted to voltages between VDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
Programming is achieved by bringing PROG high for a
minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry
takes care of ramping the programming voltage for data
transfer to the EEPROM cells. The CAT524 EEPROM
memory cells will endure over 100,000 write cycles and
will retain data for a minimum of 20 years without being
refreshed.
/BUSY
READY/BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the EEPROM erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/
BSY goes low and remains low until the programming
cycle is complete. During this time the CAT524 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum
value required for EEPROM programming, RDY/BSY
will remain high following the program command indicating a failure to record the desired data in non-volatile
memory.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13th clock cycle completes. In doing so the EEPROM’s
setting is reloaded into the DAC control register. Since
DATA OUTPUT
Data is output serially by the CAT524, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 524s to share a
single serial data line and simplifies interfacing multiple
524s to a microprocessor.
WRITING TO MEMORY
Programming the CAT524’s EEPROM memory is acFigure 1. Writing to Memory
to
1
2
3
4
5
6
7
8
9
Figure 2. Reading from Memory
10
11
12
N N+1 N+2
to
CS
1
2
3
4
5
6
7
8
9
10
11
12
CS
NEW DAC DATA
DI
1
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D6
D7
DI
1
A0
A1
CURRENT DAC DATA
DO
D0
D1
D2
D3
D4
D5
CURRENT DAC DATA
DO
PROG
DAC
OUTPUT
D0
D1
D2
D3
D4
D5
PROG
CURRENT
DAC VALUE
NEW
DAC VALUE
NEW
DAC VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
Doc. No. 25076-00 Rev. 4/01 M-1
DAC
OUTPUT
6
CURRENT
DAC VALUE
NON-VOLATILE
D6
D7
CAT524
this feature, the new value must be reloaded into the
DAC control register prior to programming. This is because the CAT524’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
this value is the same as that which had been there
previously no change in the DAC’s output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then a change would occur
at the read cycle’s conclusion.
TEMPORARILY CHANGE OUTPUT
Figure 3. Temporary Change in Output
The CAT524 allows temporary changes in DAC’s output
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
to
1
2
3
4
5
6
7
8
9
10
11
12
N
N+1 N+2
CS
NEW DAC DATA
1
DI
Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporary setting(s) remain in effect long as CS remains
high. When CS returns low all four DACs will return to the
output values stored in EEPROM memory.
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D6
D7
CURRENT DAC DATA
D0
DO
D1
D2
D3
D4
D5
PROG
CURRENT
DAC VALUE
NON-VOLATILE
NEW
DAC VALUE
VOLATILE
CURRENT
DAC VALUE
NON-VOLATILE
DAC
OUTPUT
When it is desired to save a new setting acquired using
APPLICATION CIRCUITS
DAC INPUT
DAC OUTPUT
ANALOG
OUTPUT
+5V
CODE (V - V
VDAC = ———
FS ZERO ) + V ZERO
255
MSB
LSB
Vi
VFS = 0.99 VREF
VZERO = 0.01 V REF
VREF = 5V
R I = RF
1111
255 (.98 V
——
REF) + .01 VREF = .990 V REF
255
V OUT= +4.90V
1000
0000
V
= +0.02V
OUT
0111
1111
V
= -0.02V
OUT
0000
0001
128 (.98 V
——
) + .01 V
= .502 V
REF
REF
REF
255
127
—— (.98 V
) + .01 V
= .498 V
255
REF
REF
REF
1 (.98 V
——
) + .01 V
= .014 V
255
REF
REF
REF
V
= -4.86V
OUT
0000
0000
0 (.98 V
——
) + .01 V
= .010 V
REF
REF
REF
255
V
= -4.90V
OUT
1111
Ri
RF
+15V
VDD
CONTROL
& DATA
VREF H
CAT524
GND
VOUT
–
+
OP 07
-15V
VREF L
VOUT =
VDAC (Ri+ RF ) -Vi R F
Ri
For R i = RF
VOUT = 2VDAC -Vi
Bipolar DPP Output
+5V
Ri
RF
+15V
VDD
CONTROL
& DATA
VREF H
–
CAT524
OPT
504
GND
+
VOUT
OP 07
-15V
VREF L
RF
VOUT = (1 + –––) V DAC
RI
Amplified DPP Output
7
Doc. No. 25076-00 Rev. 4/01
CAT524
APPLICATION CIRCUITS (Cont.)
+5V
VREF
RC = —————
256 * 1 µA
+5V
VDD
VREF
VREFH
FINE ADJUST
DPP
VDD
Fine adjust gives ± 1 LSB change in V OFFSET
VREF
when V OFFSET = ———
2
+VREF
VREFH
127RC
FINE ADJUST
DPP
+
(+VREF ) - (VOFFSET )
RC = ———————————
1 µA
127RC
(-VREF ) + (VOFFSET+ )
Ro = ———————————
1 µA
RC
COARSE ADJUST
DPP
+V
RC
COARSE ADJUST
DPP
V OFFSET
GND
+
VREF L
VOFFSET
-V
REF
–
GND
+V
Ro
+
–
VREF L
-V
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
28 - 32V
V+
I > 2 mA
15K
10 µF
VDD
CONTROL
& DATA
1N5231B
VREF = 5.000V
VREF H
VDD
VREF H
5.1V
10K
CAT524
OPT
505
GND
LT 1029
CONTROL
& DATA
CAT524
CAT514
GND
VREF L
VREF L
+
–
MPT3055EL
LM 324
OUTPUT
4.02 K
1.00K
Digitally Trimmed Voltage Reference
Doc. No. 25076-00 Rev. 4/01 M-1
Digitally Controlled Voltage Reference
8
10 µF
35V
0 - 25V
@ 1A
CAT524
APPLICATION CIRCUITS (Cont.)
+5V
VREF
VIN
1.0 µF
LM 339
+
10K
–
VDD
+5V
VREF H
WINDOW 1
+
CAT524
V
REF
–
WINDOW 1
DPP 1
+
–
10K
+5V
WINDOW 2
VOUT 1
+
CS
WINDOW 2
–
+
DPP 2
DI
VOUT 2
10K
–
+5V
WINDOW 3
WINDOW 3
+
DO
–
DPP 3
PROG
VOUT 3
+
–
WINDOW 4
10K
+5V
WINDOW 4
VOUT 4
+
CLK
–
DPP 4
WINDOW 5
+
GND
10K
–
+5V
WINDOW 5
+
VREF L
GND
WINDOW STRUCTURE
–
Staircase Window Comparator
+5V
VIN
VREF
1.0 F
+
LM 339
10K
–
VDD
VREF H
CAT524
+5V
WINDOW 1
+
VREF
–
WINDOW 1
DPP 1
+
–
10K
+5V
WINDOW 2
VOUT 1
+
CS
DI
WINDOW 2
–
VOUT 2
+
DPP 2
10K
–
+5V
WINDOW 3
WINDOW 3
+
DO
PROG
–
DPP 3
VOUT 3
+
–
WINDOW 4
10K
+5V
WINDOW 4
VOUT 4
+
CLK
–
DPP 4
WINDOW 5
+
GND
10K
–
+5V
WINDOW 5
+
GND
VREF L
WINDOW STRUCTURE
–
Overlapping Window Comparator
9
Doc. No. 25076-00 Rev. 4/01
CAT524
APPLICATION CIRCUITS (Cont.)
+5V
2.2K
VDD
VREF H
4.7 µA
LM385-2.5
ISINK = 2 - 255 mA
+15V
DPP
+
+5V
CONTROL
& DATA
10K
CAT524
1 mA steps
2N7000
–
39 Ω 1W
10K
39 Ω 1W
DPP
+
5 µA steps
2N7000
–
VREF L
GND
5M
5M
3.9K
10K
10K
–
TIP 30
+
Current Sink with 4 Decades of Resolution
-15V
+15V
51K
+
TIP 29
–
10K
10K
+5V
VDD
VREF H
5M
5M
DPP
39 Ω 1W
39 Ω 1W
CONTROL
& DATA
–
CAT524
5M
5M
DPP
GND
BS170P
+
1 mA steps
3.9K
–
VREF L
BS170P
5 µA steps
+
LM385-2.5
-15V
ISOURCE = 2 - 255 mA
Current Source with 4 Decades of Resolution
Doc. No. 25076-00 Rev. 4/01 M-1
10
CAT524
APPLICATION CIRCUITS (Cont.)
+12V
10K
1N914
1.0 µF
+12V
.005 µF
74C14
VCC
1N914
13
0.1 µF
2.5 µF
TREB CAP
0.47 µF
2
INPUT 1
IN 1
BASS CAP
4
0.01 µF
8
0.39 µF
20V
IN5250B
3
Vpp
VDD
CAT524
OPT
504
CHIP SELECT.
PROGRAM
DATA IN
DATA OUT
CLOCK
4
7
5
6
2
VREFH
14
DI
DO
CLK
VOUT 1
VOUT 2
VOUT 3
VOUT 4
VREFL
GND
13
12
11
10
VZ
OUTPUT 1
10
OUT 1
LM1040
1.0 µF
9
CS
PROG
19
1
47K
14
47K
11
47K
5
47K
16
0.22
µF
0.22
µF
0.22
µF
0.22
µF
LOUDNESS
VOLUME
BALANCE
TREBLE
BYPASS
BASS
1
47 µF
7
10 µF
18
10 µF
9
8
OUTPUT 2
0.47 µF
23
INPUT 2
3
IN 2
BASS CAP
STEREO
TREB CAP
15
17
22 ENHANCE
4.7K
GND
GND
0.39 µF
21
24
0.1 µF
OUT 2
0.01 µF
12
Digital Stereo Control
11
Doc. No. 25076-00 Rev. 4/01
CAT524
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
524
J
Optional
Company ID
Product
Number
Package
P: PDIP
J: SOIC
I
Tape & Reel
TE13: 2000/Reel
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
Notes:
(1) The device used in the above example is a CAT524JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 25076-00 Rev. 4/01 M-1
-TE13
12
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