3-BIT SCANNABLE REGISTER SY10E212 SY100E212 DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ Scannable version E112 driver Extended 100E VEE range of –4.2V to –5.5V 1025ps max. CLK to Output Dual differential outputs Master Reset Internal 75KΩ input pull-down resistors Fully compatible with industry standard 10KH, 100K ECL levels ■ Fully compatible with Motorola MC10E/100E212 ■ Available in 28-pin PLCC package The SY10/100E212 are scannable registered ECL drivers typically used as fan-out memory address drivers for ECL cache driving. In a VLSI array-based CPU design, use of the E212 allows the user to conserve array output cell functionality and also output pins. The input shift register is designed with control logic which greatly facilitates its use in boundary scan applications. Q2a Q2b VCCO BLOCK DIAGRAM NC S-OUT SHIFT MR PIN CONFIGURATION S-OUT D Q 18 CLK D2 VEE D1 27 17 D0 S-IN 3 13 4 12 Q1b Q1a Q1a Q1b 28 D 2 5 Q D0 Q0b Q0a Q0a Q0b 16 TOP VIEW PLCC J28-1 1 NC D1 26 6 7 8 9 15 14 Q2b Q2a VCC Q1b Q1a Q1b Q1a 10 11 VCCO D2 LOAD Q0b Q 25 24 23 22 21 20 19 Q2b Q2a Q2a Q2b VCCO Q0a Q0b Q0a D PIN NAMES S-IN LOAD SHIFT Pin CLK MR Function D0 – D2 Data Inputs S-IN Scan Input LOAD LOAD/HOLD Control SHIFT Scan Control CLK Clock MR Master Reset S-OUT Scan Output Q[0:2]a, Q[0:2]b True Outputs Q[0:2]a, Q[0:2]b Inverting Outputs VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E212 SY100E212 Micrel TRUTH TABLE LOAD SHIFT MR Mode L L L Load H L L Hold X H L Shift X X H Reset DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition — — 150 — — 150 — — 150 µA — mA — — — 80 80 96 96 — — 80 80 96 96 — — 80 92 96 110 Unit Condition ps — ps — ps — AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol TA = +25°C TA = +85°C Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tPLH tPHL Propagation Delay to Output CLK MR CLK to S-OUT 575 575 575 800 800 800 1025 1025 1025 575 575 575 800 800 800 1025 1025 1025 575 575 575 800 800 800 1025 1025 1025 tS Set-up Time D SHIFT LOAD S-IN 175 150 225 150 25 –50 50 –50 — — — — 175 150 225 150 25 –50 50 –50 — — — — 175 150 225 150 25 –50 50 –50 — — — — Hold Time D SHIFT LOAD S-IN 250 300 225 300 25 100 0 100 — — — — 250 300 225 300 25 100 0 100 — — — — 250 300 225 300 25 100 0 100 — — — — tRR Reset Recovery 600 350 — 600 350 — 600 350 — ps — tskew Within-Device Skew — 100 — — 100 — — 100 — ps 1 tskew Within-Gate Skew — 50 — — 50 — — 50 — ps 2 tr tf Rise/Fall Times 20% to 80% 275 425 650 275 425 650 275 425 650 ps — tH NOTES: 1. Within-device skew is defined as identical transitions on similar paths through a device. 2. Within-gate skew is defined as the difference in delays between various outputs of a gate when driven from the same input. PRODUCT ORDERING CODE Ordering Code 2 Package Type Operating Range SY10E212JC J28-1 Commercial SY10E212JCTR J28-1 Commercial SY100E212JC J28-1 Commercial SY100E212JCTR J28-1 Commercial SY10E212 SY100E212 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E212 SY100E212 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4