6GHz, 1:4 CML FANOUT BUFFER/TRANSLATOR WITH INTERNAL I/O TERMINATION Micrel Precision Edge™ SY58020U Precision Edge™ SY58020U FEATURES Precision 1:4, 400mV CML fanout buffer Guaranteed AC performance over temperature/ voltage: • > 6GHz fMAX clock • < 60ps tr / tf times • < 250ps tpd • < 15ps max. skew Low jitter performance: • < 10ps(pk-pk) total jitter (clock) • < 1ps(rms) random jitter (data) • < 10ps(pk-pk) deterministic jitter (data) Accepts an input signal as low as 100mV Unique input termination and VT pin accepts DC-coupled and AC-coupled differential inputs: LVPECL, LVDS, and CML 50Ω source terminated CML outputs Power supply 2.5V ±5% and 3.3V ±10% Industrial temperature range: –40°C to +85°C Available in 16-pin (3mm × 3mm) MLF™ package Precision Edge™ DESCRIPTION The SY58020U is a 2.5V/3.3V precision, high-speed, fully differential 1:4 CML fanout buffer. Optimized to provide four identical output copies with less than 15ps of skew and less than 10ps(pk-pk) total jitter, the SY58020U can process clock signals as fast as 6GHz. The differential input includes Micrel’s unique, 3-pin input termination architecture interfaces to differential LVPECL, LVDS, and CML signals (AC-coupled or DC-coupled) as small as 100mV without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an on-board output reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are optimized to drive 400mV typical swing into 50Ω loads, with extremely fast rise/fall times guaranteed to be less than 60ps. The SY58020U operates from a 2.5V ±5% supply or 3.3V ±10% supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). For applications that require LVPECL outputs, consider the SY58021U or SY58022U 1:4 fanout buffer with 800mV and 400mV output swing, respectively. The SY58020U is part of Micrel’s highspeed, Precision Edge™ product line. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. APPLICATIONS ■ ■ ■ ■ ■ All SONET and All GigE clock distribution Fibre Channel clock and data distribution Backplane distribution Data distribution: OC-48, OC-48+FEC, XAUI High-end, low skew, multiprocessor synchronous clock distribution FUNCTIONAL BLOCK DIAGRAM TYPICAL PERFORMANCE Q0 IN 50Ω 2GHz Output /Q0 VT 50Ω Q1 Amplitude /Q1 VREF-AC Q2 (100mV/div.) /IN /Q2 Q3 TIME (70ps/div.) /Q3 Precision Edge is a trademark of Micrel, Inc. MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc. Rev.: A 1 Amendment: /0 Issue Date: July 2003 Precision Edge™ SY58020U Micrel PACKAGE/ORDERING INFORMATION GND Q0 /Q0 VCC Ordering Information(Note 1) Part Number Package Type Operating Range Package Marking Q1 SY58020UMI MLF-16 Industrial 020U /Q1 Q2 /Q2 SY58020UMITR(Note 2) MLF-16 Industrial 020U 16 15 14 13 IN 1 12 VT 2 11 VREF-AC /IN 3 4 10 9 Contact factory for die availability. Die are guaranteed at TA = 25°C, DC electricals only. Note 2. Tape and Reel. GND /Q3 Q3 VCC 5 6 7 8 Note 1. 16-Pin MLF™ (MLF-16) PIN DESCRIPTION Pin Number Pin Name Pin Function 1, 4 IN, /IN Differential Input: This input pair receives the signal to be buffered. Each pin of this pair internally terminates with 50Ω to the VT pin. Note that this input will default to an indeterminate state if left open. See “Input Interface Applications” section. 2 VT Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides a center-tap for each input (IN, /IN) to the termination network for maximum interface flexibility. See “Input Interface Applications” section. 3 VREF-AC 8, 13 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to the pins as possible. 5, 16 GND, Exposed Pad Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pin. 14, 15 11, 12 9, 10 6, 7 /Q0, Q0, /Q1, Q1, /Q2, Q2, /Q3, Q3, Reference Output Voltage: This output biases to VCC –1.2V. It is used when AC-coupling to differential inputs. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR capacitor to VCC. See “Input Interface Applications” section. CML Differential Output Pairs: Differential buffered output copy of the input signal. The output swing is typically 400mV into 50Ω load. Normally terminate CML output pairs with 100Ω across Q and /Q outputs at the receiving end. Unused output pairs may be left floating with no impact on jitter or skew. See “CML Output Termination” section. 2 Precision Edge™ SY58020U Micrel Absolute Maximum Ratings(Note 1) Operating Ratings(Note 2) Power Supply Voltage (VCC) ....................... –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC CML Output Voltage (VOUT) ........... VCC–1.0V to VCC+0.5V Current (VT) Source or sink current on VT pin ........................ ±100mA Input Current Source or sink current on IN, /IN .......................... ±50mA Current (VREF) Source or sink current on VREF-AC, Note 4 ......... ±1.5mA Lead Temperature Soldering, (10 seconds) .............. 270°C Storage Temperature Range (TSTORE) .... –65°C to +150°C Supply Voltage (VCC) ............................ +2.375V to +3.60V Operating Temperature Range (TA) ........... –40°C to +85°C Package Thermal Resistance MLF™ (θJA) Still-Air ............................................................. 60°C/W 500lfpm ............................................................ 54°C/W MLF™ (ψJB) (Junction-to-Board Resistance), Note 3 .......... 33°C/W DC ELECTRICAL CHARACTERISTICS(Notes 5) TA = –40°C to +85°C Symbol Parameter Condition Min Typ Max Units VCC Power Supply Voltage VCC = 2.5V VCC = 3.3V 2.375 3.0 2.5 3.3 2.625 3.60 V V ICC Power Supply Current No load, VCC = max. (includes internal 50Ω pull-up) 150 180 mA VIH Input HIGH Voltage Note 6 VCC–1.6 VCC V VIL Input LOW Voltage 0 VIH–0.1 V VIN Input Voltage Swing See Figure 1a 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing See Figure 1b 0.2 3.4 V RIN IN-to-VT Resistance 60 Ω VREF-AC Output Reference Voltage VT IN IN-to-VT Voltage 40 50 VCC –1.3 VCC –1.2 VCC –1.1 1.28 V V CML DC ELECTRICAL CHARACTERISTICS(Notes5) VCC = 3.3V ±10% or 2.5V ±5%; RL = 100Ω across each output pair or equivalent; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min VOH Output HIGH Voltage VOUT Output Voltage Swing see Figure 1a 325 VDIFF_OUT Differential Output Voltage Swing see Figure 1b ROUT Output Source Impedance Typ Max Units VCC V 400 500 mV 650 800 1000 mV 40 50 60 Ω VCC –0.020 VCC –0.010 Note 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATINGS conditions for extended periods may affect device reliability. Note 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. Note 3. Thermal performance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential on the PCB. Note 4. Due to the limited drive capability, use for input of the same package only. Note 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Note 6. VIH (min.) not lower than 1.2V. 3 Precision Edge™ SY58020U Micrel AC ELECTRICAL CHARACTERISTICS VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 100Ω across each output pair or equivalent, unless otherwise stated. Symbol Parameter Condition Min fMAX Maximum Operating Frequency VOUT ≥ 200mV Clock Propagation Delay tCHAN Channel-to-Channel Skew Note 7 tSKEW Part-to-Part Skew tJITTER Clock Data t r, t f Max Units 6 NRZ Data tpd Typ GHz 10 110 Gbps 180 260 ps 4 15 ps Note 8 50 ps Note 9 1 ps(rms) Total Jitter Note 10 10 ps(pk-pk) Random Jitter Note 11 2.5Gbps – 3.2Gbps 1 ps(rms) Deterministic Jitter Note 12 2.5Gbps – 3.2Gbps 10 ps(pk-pk) 60 ps Cycle-to-Cycle Jitter Output Rise/Fall Time 20% to 80% At full swing 20 40 Note 7. Skew is measured between outputs of the same bank under identical transitions. Note 8. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Note 9. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output signal. Note 10. Total jitter definition: With an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. Note 11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps. Note 12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps with both K28.5 and 223–1 PRBS pattern TIMING DIAGRAM /IN IN /Q Q tpd SINGLE-ENDED AND DIFFERENTIAL SWINGS VDIFF_IN, VDIFF_OUT 800mV VIN, VOUT 400mV Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing 4 Precision Edge™ SY58020U Micrel TYPICAL OPERATING CHARACTERISTICS VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. Skew vs. Temperature Amplitude vs. Frequency 195 6 5 SKEW (ps) 350 300 250 200 150 100 4 3 2 0 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 12000 10000 8000 6000 4000 2000 1 FREQUENCY (MHz) Propagation Delay vs. Temperature 184 PROPAGATION DELAY (ps) 0 AMPLITUDE (V) 450 400 50 0 Propagation Delay vs. Input Voltage Swing 7 PROPAGATION DELAY (ps) 500 183 182 181 180 179 178 177 176 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 5 190 185 180 175 170 165 0 200 400 600 800 1000 1200 INPUT VOLTAGE SWING (mV) Precision Edge™ SY58020U Micrel FUNCTIONAL CHARACTERISTICS VCC = 2.5V, GND = 0, VIN = 100mV, TA = 25°C, unless otherwise stated. 5GHz Output Amplitude (100mV/div.) Amplitude (100mV/div.) 200MHz Output TIME (25ps/div.) TIME (600ps/div.) 6 Precision Edge™ SY58020U Micrel INPUT STAGE VCC IN 50Ω VT GND 50Ω /IN Figure 2. Simplified Differential Input Buffer INPUT INTERFACE APPLICATIONS VCC VCC VCC VCC VCC VCC IN IN CML IN CML /IN LVDS /IN SY58020U SY58020U NC VT NC VREF-AC VT (Option: May connect VT to VCC) Figure 3a. DC-Coupled CML Input Interface VCC VCC Figure 3b. AC-Coupled CML Input Interface VCC VCC IN LVPECL /IN /IN SY58020U SY58020U Rpd Rpd VT VT NC VT NC VREF-AC VCC IN LVPECL Rpd NC VREF-AC 0.01µF 0.01µF /IN SY58020U VREF-AC VREF-AC 0.01µF For VCC = 2.5V, Rpd = 19Ω For VCC = 3.3V, Rpd = 50Ω Figure 3d. LVPECL Input Interface VCC Rpd = 100Ω for a 3.3V system Rpd = 50Ω for a 2.5V system Figure 3e. AC-Coupled LVPECL Input Interface 7 Figure 3c. LVDS Input Interface Precision Edge™ SY58020U Micrel CML OUTPUT TERMINATION Figures 4 and 5 illustrate how to terminate a CML output using both the AC-coupled and DC-coupled configuration. All outputs of the SY58020U are 50Ω with a 16mA current source. VCC VCC 50 50Ω 50Ω W 50 W Q W 50W 50 Q 100Ω /Q /Q DC-bias 16mA 16mA GND per application GND Figure 5. CML AC-Coupled Termination Figure 4. CML DC-Coupled RELATED MICREL PRODUCTS AND SUPPORT DOCUMENTATION Part Number Function Data Sheet Link SY58020U 6GHz, 1:4 CML Fanout Buffer/Translator with Internal I/O Termination http://www.micrel.com/product-info/products/sy58020u.shtml SY58021U 4GHz, 1:4 LVPECL Fanout Buffer/Translator with Internal Termination http://www.micrel.com/product-info/products/sy58021u.shtml SY58022U 5.5GHz, 1:4 Fanout Buffer/Translator w/400mV LVPECL Outputs and Internal Input Termination http://www.micrel.com/product-info/products/sy58022u.shtml 16-MLF™ Manufacturing Guidelines Exposed Pad Application Note www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf HBW Solutions http://www.micrel.com/product-info/as/solutions.shtml M-0317 8 Precision Edge™ SY58020U Micrel 16 LEAD MicroLeadFrame™ (MLF-16) 0.42 +0.18 –0.18 0.23 +0.07 –0.05 0.85 +0.15 –0.65 0.01 +0.04 –0.01 3.00BSC 1.60 +0.10 –0.10 0.65 +0.15 –0.65 0.20 REF. 2.75BSC 0.42 PIN 1 ID +0.18 –0.18 N 16 1 1 0.50 DIA 2 2 2.75BSC 3.00BSC 3 3 1.60 +0.10 –0.10 4 4 12° max 0.5 BSC 0.42 +0.18 –0.18 SEATING PLANE 0.40 +0.05 –0.05 1.5 REF BOTTOM VIEW TOP VIEW CC 0.23 +0.07 –0.05 CL 4 0.01 +0.04 –0.01 SECTION "C-C" SCALE: NONE 0.5BSC 1. 2. 3. 4. DIMENSIONS ARE IN mm. DIE THICKNESS ALLOWABLE IS 0.305mm MAX. PACKAGE WARPAGE MAX 0.05mm. THIS DIMENSION APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20mm AND 0.25mm FROM TIP. 5. APPLIES ONLY FOR TERMINALS Rev. 02 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 16-Pin MLF™ Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: Note 1. Package meets Level 2 qualification. Note 2. All parts are dry-packaged before shipment. Note 3. Exposed pads must be soldered to a ground for proper thermal management. MICREL, INC. TEL 1849 FORTUNE DRIVE SAN JOSE, CA 95131 + 1 (408) 944-0800 FAX + 1 (408) 944-0970 WEB USA http://www.micrel.com The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2003 Micrel, Incorporated. 9