MICREL SY88933VKITR

3.3V/5V 1.25Gbps PECL LOW-POWER
LIMITING POST AMPLIFIER
w/TTL SIGNAL DETECT
Micrel
DESCRIPTION
FEATURES
■
■
■
■
Single 3.3V or 5V power supply
DC to 1.25Gbps operation
Low noise PECL data outputs
Chatter-free OC-TTL signal setect (SD) output with
internal 6.75kΩ pull-up resistor
■ TTL EN input
■ Programmable SD level set (SDLVL)
■ Available in a tiny 10-pin MSOP (3mm) package
The SY88933V low-power limiting post amplifier is
designed for use in fiber-optic receivers. The device connects
to typical transimpedance amplifiers (TIAs). The linear signal
output from TIAs can contain significant amounts of noise
and may vary in amplitude over time. The SY88933V
quantizes these signals and outputs PECL level waveforms.
The SY88933V operates from a single +3.3V or +5V
power supply, over temperatures ranging from –40°C to
+85°C. With its wide bandwidth and high gain, signals with
data rates up to 1.25Gbps and as small as 5mVp-p can be
amplified to drive devices with PECL inputs.
The SY88933V generates a TTL SD output. A
programmable signal-detect level set pin (SDLVL) sets the
sensitivity of the input amplitude detection. SD asserts high
if the input amplitude rises above the threshold set by SDLVL
and deasserts low otherwise. EN deasserts the true output
signal without removing the input signal. Typically 4.6dB
SD hysteresis is provided to prevent chattering.
APPLICATIONS
■
■
■
■
■
SY88933V
SY88933V
Final
1.25Gbps Ethernet
1.55Mbps and 622Mbps SONET/SDH
High-gain line driver and line receiver
531Mbps and 1062Mbps Fibre Channel
Gigabit interface converter
TYPICAL APPLICATIONS CIRCUIT
VCC
SD
From
Transimpedance
Amp.
0.1µF
DIN
0.1µF
/DIN
50Ω
50Ω
EN
SY88933V
SDLVL
GND
DOUT
0.1µF
/DOUT
0.1µF
VREF
VCC
100kΩ
0.1µF
Rpd
To
CDR
Rpd
GND
For 3.3V, Rpd = 120Ω
For 5V, Rpd = 220Ω
Rev.: A
1
Amendment: /0
Issue Date: May 1, 2003
SY88933V
Micrel
PACKAGE/ORDERING INFORMATION
Ordering Information
EN 1
Part Number
Package
Type
Operating
Range
Package
Marking
SY88933VKC
K10-1
Commercial
933V
SY88933VKCTR(Note 1)
K10-1
Commercial
933V
SY88933VKI
K10-1
Industrial
933V
SY88933VKITR(Note 1)
K10-1
Industrial
933V
10 VCC
DIN 2
9 DOUT
/DIN 3
8 /DOUT
VREF 4
7 SD
SDLVL 5
6 GND
Note 1.
10-Pin MSOP (K10-1)
Tape and Reel.
PIN DESCRIPTION
Pin Number
Pin Name
Type
Pin Function
1
EN
TTL Input:
Default is high.
2
DIN
Data Input
True data input.
3
/DIN
Data Input
Complementary data input.
4
VREF
5
SDLVL
Input
6
GND
Ground
7
SD
Open-collector
TTL output w/
internal 6.75kΩ
pull-up resistor
8
/DOUT
PECL Output
Complementary data output.
9
DOUT
PECL Output
True data output.
10
VCC
Power Supply
Positive power supply.
Enable: Deasserts true data output when high.
Reference voltage: capacitor here to VCC helps stabilize SDLVL.
Signal-Detect Level Set: a resistor from this pin to VCC sets the
threshold for the data input amplitude at which SD will be asserted.
Device ground.
Signal-Detect: asserts high when the data input amplitude rises above
the threshold set by SDLVL.
2
SY88933V
Micrel
Absolute Maximum Ratings(Note 1)
Operating Ratings(Note 2)
Supply Voltage (VCC) ....................................... 0V to +7.0V
Input Voltage (DIN, /DIN) .........................................0 to VCC
Output Current (IOUT)
Continuous ............................................................. 50mA
Surge .................................................................... 100mA
EN Voltage ............................................................. 0 to VCC
VREF Current ......................................... –800µA to +500µA
SDLVL Voltage ................................................. VREF to VCC
Storage Temperature (TS) ....................... –55°C to +125°C
Supply Voltage (VCC) .............................. +3.0V to +3.6V or
............................................................ +4.5V to +5.5V
Ambient Temperature (TA), Note 3 ............ –40°C to +85°C
Junction Temperature (TJ), Note 3 .......... –40°C to +120°C
Package Thermal Resistance
MSOP
(θJA) Still-Air .................................................. 113°C/W
Note 1.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
Note 2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Note 3.
Commercial devices are guaranteed from 0°C to +85°C ambient temperature.
DC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC–2V; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
ICC
Power Supply Current
No output load
22
42
mA
SDLVL
SDLVL Voltage
VCC
V
VIH
EN Input HIGH Voltage
VIL
EN Input LOW Voltage
IIH
EN Input HIGH Current
VIN = 2.7V
VIN = VCC
IIL
EN Input LOW Current
VIN = 0.5V
–0.3
mA
VOH
SD Output HIGH Level
VCC ≥ 3.3V
VCC < 3.3V
2.4
2.0
V
V
VOL
SD Output LOW Level
IOL = +2mA
VOH
PECL Output HIGH Voltage
50Ω to VCC–2V output load
VCC–1.085 VCC–0.955 VCC–0.880
V
VOL
PECL Output LOW Voltage
50Ω to VCC–2V output load
VCC–1.830 VCC–1.705 VCC–1.555
V
VOFFSET
Differential Output Offset
VIHCMR
Common Mode Range
Note 1
GND +2.0
VREF
Reference Voltage
Note 2
VCC–1.38
VREF
2.0
V
0.8
V
20
100
µA
µA
0.5
Note 1.
The VIHCMR range is referenced to the most positive side of the differential input signal.
Note 2.
The current provided into or from VREF must be limited to 800µA source and 500µA sink.
3
VCC–1.32
V
±100
mV
VCC
V
VCC–1.26
V
SY88933V
Micrel
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0V to 3.6V or 4.5V to 5.5V; RLOAD = 50Ω to VCC–2V; TA = –40°C to +85°C; typical values at VCC = 3.3V, TA = 25°C.
Symbol
Parameter
Condition
Min
Typ
Max
Units
HYS
SD Hysteresis
electrical signal
2
4.6
8
dB
tOFF
SD Release Time
0.1
0.5
µs
tON
SD Assert Time
0.2
0.5
µs
VID
Differential Input Voltage Swing
1800
mVp-p
VOD
Differential Output Voltage Swing
VSR
SD Sensitivity Range
AV(Diff)
Differential Voltage Gain
B–3dB
3dB Bandwidth
1
S21
Single-Ended Small-Signal Gain
26
tr,tf
Differential Output Rise/Fall Time
(20% to 80%)
5
VID ≥ 18mVp-p
VID = 5mVp-p
1500
400
mVp-p
mVp-p
5
50
38
dB
GHz
32
dB
VID > 100mVp-p and 50Ω to VCC – 2V load
260
TYPICAL OPERATING CHARACTERISTICS
SD Assert and Deassert
Levels vs. SDLVL
120
80
SD Assert and Deassert
Levels vs. RSDLVL
VSUP = 3.3V
TA = 25°C
1.25Gbps
Pattern 223–1
120
100
VID (mVp-p)
100
60
ASSERT
40
80
ASSERT
60
40
1
0
1.2 1.4
SDLVL (referenced to VCC) (V)
RSDLVL (Ω)
4
100000
0.2 0.4 0.6 0.8
10000
0
1000
0
DEASSERT
100
20
DEASSERT
10
20
1
VID (mVp-p)
140
VSUP = 3.3V
TA = 25°C
1.25Gbps
Pattern 223–1
mVp-p
ps
SY88933V
Micrel
DETAILED DESCRIPTION
SDLVL and deasserts low otherwise. SD can be fed back to
the enable (EN) input to maintain output stability under a
loss of signal condition. EN deasserts the true output signal
without removing the input signals. Typically 4.6dB SD
hysteresis is provided to prevent chattering.
The SY88933V low-power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40°C to +85°C. Signals with data rates up to 1.25Gbps
and as small as 5mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88933V generates
an SD output. SDLVL sets the sensitivity of the input
amplitude detection.
Signal-Detect Level Set
A programmable SD level set pin (SDLVL) sets the
threshold of the input amplitude detection. Connecting an
external resistor between VCC and SDLVL sets the voltage
at SDLVL. This voltages ranges from VCC to VREF. The
external resistor creates a voltage divider between VCC and
VREF as shown in Figure 5. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SDLVL to VCC, the smaller the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SDLVL voltage.
Input Amplifier/Buffer
Figure 2 shows a simplified schematic of the SY88933V's
input stage. The high-sensitivity of the input amplifier allows
signals as small as 5mVp-p to be detected and amplified.
The input amplifier allows input signals as large as
1800mVp-p. Input signals are linearly amplified with a
typically 38dB differential voltage gain. Since it is a limiting
amplifier, the SY88933V outputs typically 1500mVp-p
voltage-limited waveforms for input signals that are greater
than 18mVp-p. Applications requiring the SY88933V to
operate with high-gain should have the upstream TIA placed
as close as possible to the SY88933V’s input pins to ensure
the best performance of the device.
Hysteresis
The SY88933V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2IN/R for an
electrical signal. Hence the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence the ratios change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the datasheet. The SY88933V provides typically 2.3dB
SD optical hysteresis. As the SY88933V is an electrical
device, this datasheet refers to hysteresis in electrical terms.
With 6dB SD hysteresis, a voltage factor of two is required
to assert or deassert SD.
Output Buffer
The SY88933V’s PECL output buffer is designed to drive
50Ω lines. The output buffer requires appropriate termination
for proper operation. An external 50Ω resistor to VCC–2V
for each output pin provides this. Figure 3 shows a simplified
schematic of the output stage and includes an appropriate
termination method.
Signal-Detect
The SY88933V generates a chatter-free SD open-collector
TTL output with internal 6.75kΩ pullup resistor as shown in
Figure 4. SD is used to determine that the input amplitude
is large enough to be considered a valid input. SD asserts
high if the input amplitude rises above the threshold set by
5
SY88933V
Micrel
DATA+
2.5mV (Min.)
VIS(mVp-p)
900mV (Max.)
DATA—
(DATA+) — (DATA—)
5mVp-p (Min.)
VID(mVp-p)
1800mVp-p (Max.)
Figure 1. VIS and VID Definitions
VCC
VCC
ESD
STRUCTURE
DOUT
/DOUT
DIN
/DIN
ESD
STRUCTURE
GND
GND
Figure 2. Input Structure
Figure 3. Output Structure
VCC
RSDLVL
SDLVL
VCC
6.75kΩ
3kΩ
SD
VREF
Figure 4. SD Output Structure
Figure 5. SDLVL Setting Circuit
6
SY88933V
Micrel
FUNCTIONAL BLOCK DIAGRAM
DIN
Limiting
Amplifer
DOUT
PECL
Buffer
/DIN
/DOUT
VREF
Enable
VCC
GND
EN
Level
Detect
SD
SDLVL
DESIGN PROCEDURE
Layout and PCB Design
Since the SY88933V is a high-frequency component,
performance can be largely determined by the board layout
and design. A common problem with high-gain amplifiers is
the feedback from the large swing outputs to the input via
the power supply.
The SY88933V’s ground pin should be connected to the
circuit board ground. Use multiple PCB vias close to the
part to connect to ground. Avoid long, inductive runs which
can degrade performance.
7
SY88933V
Micrel
10 LEAD MSOP (K10-1)
Rev. 00
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
USA
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
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