2.5/3.3V 1:22 HIGH-PERFORMANCE, ClockWorks™ LOW-VOLTAGE PECL BUS CLOCK DRIVER SY89825U & TRANSLATOR w/ INTERNAL TERMINATION FINAL FEATURES DESCRIPTION ■ LVPECL or LVDS input to 22 LVPECL outputs The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100Ω internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The SY89825U features low pin-to-pin skew (35ps max.) —performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew. ■ 100K ECL compatible outputs ■ LVDS input includes 100Ω termination ■ Guaranteed AC parameters over voltage: ■ ■ ■ PIN CONFIGURATION VCCO /Q6 Q6 /Q5 Q5 /Q4 Q4 /Q3 Q3 /Q2 Q2 /Q1 Q1 /Q0 Q0 VCCO 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCCO NC NC VCCI LVDS_CLK /LVDS_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GND OE NC NC /Q21 Q21 VCCO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64-Pin EPAD-TQFP (Top View) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCCO Q7 /Q7 Q8 /Q8 Q9 /Q9 Q10 /Q10 Q11 /Q11 Q12 /Q12 Q13 /Q13 VCCO APPLICATIONS ■ High-performance PCs ■ Workstations ■ Parallel processor-based systems ■ Other high-performance computing ■ Communications 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VCCO /Q20 Q20 /Q19 Q19 /Q18 Q18 /Q17 Q17 /Q16 Q16 /Q15 Q15 /Q14 Q14 VCCO ■ • > 2GHz fMAX (toggle) • < 35ps max. ch-ch skew Low voltage operation: 2.5V, 3.3V Temperature range: –40°C to +85°C Output enable pin Available in a 64-Pin EPAD-TQFP Rev.: A 1 Amendment: /0 Issue Date: September 2001 ClockWorks™ SY89825U Micrel LOGIC SYMBOL PIN NAMES Pin Function CLK_SEL LVDS_CLK, /LVDS_CLK Differential LVDS Inputs (Internal 100Ω termination included) LVDS_CLK LVPECL_CLK, /LVPECL_CLK Differential LVPECL Inputs. /LVDS_CLK 0 22 Q0 - Q21 22 CLK_SEL Input CLK Select (LVTTL) OE Output Enable (LVTTL) LVPECL_CLK Q0 – Q21, /Q0 – /Q21 Differential LVPECL Outputs. Terminate with 50Ω to VCC-2V /LVPECL_CLK GND Ground VCCI Power Supply. Connect to VCC on PCB. VCCI and VCCO are not internally connected VCCO Power Supply for Output Buffer. Connect to VCCI on PCB. VCCI and VCCO are not internally connected /Q0 - /Q21 1 LEN Q OE TRUTH TABLE D SIGNAL GROUPS OE(1) CLK_SEL Q0 – Q21 /Q0 – /Q21 0 0 LOW HIGH LVDS_CLK, /LVDS_CLK 0 1 LOW HIGH Q0 – Q21, /Q0 – /Q21 1 0 LVDS_CLK /LVDS_CLK 1 1 LVPECL_CLK /LVPECL_CLK Signal I/O Input Level LVDS Output LVPECL LVPECL_CLK, /LVPECL_CLK Input LVPECL CLK_SEL, OE Input LVCMOS/LVTTL NOTE: 1. The OE (output enable) signal is synchronized with the low level of the LVDS_CLK and LVPECL_CLK signal. ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit VCCI / VCCO VCC Pin Potential to Ground Pin –0.5 to +4.0 V VIN Input Voltage –0.5 to VCCI V IOUT DC Output Current –50 mA Tstore Storage Temperature –65 to +150 °C θJA Package Thermal Resistance (Junction-to-Ambient) With exposed pad soldered to GND – Still-Air (multi-layer PCB) – 200lfpm (multi-layer PCB) – 500lfpm (multi-layer PCB) 23 18 15 °C/W °C/W °C/W 44 36 30 °C/W °C/W °C/W 4.3 °C/W Exposed pad not soldered to GND θJC – Still-Air (multi-layer PCB) – 200lfpm (multi-layer PCB) – 500lfpm (multi-layer PCB) Package Thermal Resistance (Junction-to-Case) NOTE: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect device reliability. 2 ClockWorks™ SY89825U Micrel DC ELECTRICAL CHARACTERISTICS Power Supply TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VCCI, VCCO Power Supply(1) 2.37 — 3.6 2.37 — 3.8 2.37 — 3.6 V ICC Total Supply Current(2) — 100 150 — 100 150 — 100 150 mA NOTES: 1. VCCI and VCCO must be connected together on the PCB such that they remain at the same potential. VCCI and VCCO are not internally connected on the die. 2. No load. Outputs floating. LVDS Input (VCC = 2.37V to 3.6V, GND = 0V) TA = –40°C Symbol Parameter VIN Input Voltage Range VID Differential Input Swing Current(1) IIL Input Low RIN LVDS Differential Input Resistance (LVDS_CLK to /LVDS_CLK) TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 0 — 2.4 0 — 2.4 0 — 2.4 V 100 — — 100 — — 100 — — mV –1.25 — — –1.25 — — –1.25 — — mA 80 100 120 80 100 120 80 100 120 Ω NOTE: 1. For IIL, both LVDS inputs are grounded. LVPECL Input/Output (VCC = 2.37V to 3.6V, GND = 0V) TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Max. Min. Max. Min. Max. Unit VIH Input HIGH Voltage (Single ended) VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88 VCC – 1.165 VCC – 0.88 V VIL Input LOW Voltage VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625 VCC – 1.945 VCC – 1.625 V Swing(1) VPP Minimum Input LVPECL_CLK 600 — 600 — 600 — mV VCMR Common Mode Range(2) LVPECL_CLK –1.5 –0.4 –1.5 –0.4 –1.5 –0.4 V VOH Output HIGH Voltage(3) VCCO – 1.085 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880 VCCO – 1.025 VCCO – 0.880 VOL Output LOW Voltage(3) VCCO – 1.830 VCCO – 1.555 VCCO – 1.810 VCCO – 1.620 VCCO – 1.810 VCCO – 1.620 IIH Input HIGH Current — 150 — 150 — 150 µA IIL Input LOW Current 0.5 — 0.5 — 0.5 — µA V V NOTES: 1. The VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 2. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR (min) will be fixed at 3.3V – |VCMR (min)|. 3. Outputs loaded with 50Ω to VCC -2V. LVCMOS/LVTTL Control Inputs (OE, CLK_SEL) (VCC = 2.37V to 3.6V, GND = 0V) TA = –40°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VIH Input HIGH Voltage 2.0 — — 2.0 — — 2.0 — — V VIL Input LOW Voltage — — 0.8 — — 0.8 — — 0.8 V IIH Input HIGH Current +20 — –250 +20 — –250 +20 — –250 µA IIL Input LOW Current — — –600 — — –600 — — –600 µA 3 ClockWorks™ SY89825U Micrel AC ELECTRICAL CHARACTERISTICS(1) VCC = 2.37V to 3.6V, GND = 0V TA = –40°C Symbol Parameter Frequency(2) fMAX Max Toggle tPHL tPLH Propagation Delay (Differential)(3) LVPECL IN LVDS IN tSKEW Within-Device Skew(4) Part-to-Part Skew(5) TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 2 — — 2 — — 2 — — GHz 0.600 0.800 — — 1.2 1.4 0.600 0.800 0.900 1.1 1.2 1.4 0.600 0.800 — — 1.2 1.4 — — 35 — 20 35 — — 35 ns ps — 100 200 — 100 200 — 100 200 ps tS(OE) OE Set-Up Time(6) 1.0 — — 1.0 — — 1.0 — — ns tH(OE) OE Hold Time(6) 0.5 — — 0.5 — — 0.5 — — ns tr tf Output Rise/Fall Time (20% – 80%) 300 — 600 300 450 600 300 — 600 ps — — 1.2 — — 1.2 — — 1.2 ns t(switchover) Input Switchover CLK_SEL-to-valid output NOTES: 1. Outputs loaded with 50Ω to VCC – 2V. Airflow ≥ 300lfpm. 2. fMAX is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50Ω to VCC –2V. 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. 6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. PRODUCT ORDERING CODE 4 Ordering Code Package Type Operating Range Package Marking SY89825UHI H64-1 Industrial SY89825UHI ClockWorks™ SY89825U Micrel LVDS/LVPECL INPUTS VCC VCC 1.9k 1.9k 75k LVPECL_CLK 1.9k 75k 75k 1.9k VIN 100Ω VIN /LVPECL_CLK GND GND LVPECL Input Stage LVDS Input Stage Figure 1. Simplified LVPECL & LVDS Input Stage 5 ClockWorks™ SY89825U Micrel TYPICAL CHARACTERISTICS Frequency Response vs. Output Amplitude Frequency Response vs. Output Amplitude 900 300 4000 3500 0 FREQUENCY (MHz) 3000 200 100 4000 3500 3000 2500 2000 1500 0 100 1000 200 400 2500 300 500 2000 400 600 1500 500 700 1000 600 VSUP = 3.3V VDIFFIN = 800mV 800 500 700 OUTPUT AMPLITUDE (mV) VSUP = 2.5V VDIFFIN = 800mV 800 500 OUTPUT AMPLITUDE (mV) 900 FREQUENCY (MHz) Frequency Response vs. Output Amplitude @2.5V Frequency Response vs. Output Amplitude @3.3V 6 ClockWorks™ SY89825U Micrel LVPECL TERMINATION RECOMMENDATIONS down resistor at the output of each driver. The emmiter follower outputs requires a DC current path to GND. Unused outputs can be left floating with minimal impact on skew and jitter. Output Considerations Be sure to properly terminate all outputs as shown below, or equivalent. For AC coupled applications, be sure to include a pull +3.3V R1 130Ω R1 130Ω +3.3V ZO = 50Ω +3.3V ZO = 50Ω R2 82Ω R2 82Ω Vt = VCC —2V Figure 1. Parallel Termination–Thevenin Equivalent Notes: 1. For +2.5V systems: R1 = 250Ω R2 = 62.5Ω +3.3V +3.3V Z = 50Ω “source” “destination” Z = 50Ω 50Ω 46Ω to 49Ω 50Ω Rb Figure 2. Three-Resistor “Y–Termination” Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage equal to Vt. For +3.3V systems Rb = 46Ω to 49Ω. 4. Precision, low-cost 3-Resistor networks are available from resistor manufacturers such as Thin Film Technology (www.thinfilm.com). 7 ClockWorks™ SY89825U Micrel 64 LEAD EPAD-TQFP (DIE UP) (H64-1) 12.00 0.472 BSC SQ. 1.00 +0.05 –0.05 0.039 +0.002 –0.002 4 10.00 0.394 BSC SQ. 4.50 0.177 +0.05 –0.05 +0.012 –0.012 48 64 6 DETAIL "A" 0° MIN. 6 7 0.20 0.008 0.09 0.004 0.15 0.006 0.05 0.002 48 0°- 7° 4.50 +0.03 –0.03 0.177+0.012 –0.012 0.60 +0.15 –0.15 0.024 +0.006 –0.006 1.00 0.039 REF. 33 16 17 32 5 0.50 0.020 1.20 0.047 MAX SEE DETAIL "A" BSC 0.01 0.004 7 0.22 +0.05 –0.05 0.009 +0.002 –0.002 Rev. 03 MICREL-SYNERGY 3250 SCOTT BOULEVARD TEL + 1 (408) 980-9191 FAX SANTA CLARA CA 95054 + 1 (408) 914-7878 WEB USA http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2001 Micrel Incorporated 8