STMicroelectronics M41T60 Serial access real-time clock Datasheet

M41T60
Serial Access Real-Time Clock
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
■
■
■
350nA TIMEKEEPING CURRENT @ 3V
TIMEKEEPING DOWN TO 1.0V
1.3V TO 3.6V I2C BUS OPERATING
VOLTAGE
COUNTERS FOR SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH, YEARS, AND
CENTURY
SERIAL INTERFACE SUPPORTS I2C BUS
(400kHz)
SOFTWARE CLOCK CALIBRATION
LOW OPERATING CURRENT OF 35µA
OSCILLATOR STOP DETECTION
AUTOMATIC LEAP YEAR COMPENSATION
SOFTWARE PROGRAMMABLE OUTPUT
(OUT)
OPERATING TEMPERATURE OF –40 TO
85°C
LEAD-FREE 16-PIN QFN PACKAGE
TOTAL SURFACE AREA OF IC AND 32KHz
CRYSTAL IS 21.5mm2
Figure 1. Package
QFN16 (Q)
Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20
VSOJ20 (47.6mm2)
2
GND Plane Guard Ring (21.5mm )
SMT
CRYSTAL
1
XI
2
XO
3
4
ST QFN16
AI11107
NC
NC
VCC
NC
Figure 3. 16-pin QFN Connections
16
15
14
13
XO
2
11
OFIRQ/OUT
VSS
3
10
SCL
(1)
4
9
SDA
FT
5
6
7
8
NC
NC
NC
12
NC
1
VSS
XI
(1)
AI08870
Note: 1. Open Drain Output.
May 2005
1/23
M41T60
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. 32KHz Crystal + QFN16 vs. VSOJ20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 3. 16-pin QFN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4.
Table 1.
Figure 5.
Figure 6.
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Hardware Hookup for Battery Back-up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2-Wire Bus Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Bus not busy.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Start data transfer.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Stop data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data valid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 7. Serial Bus Data Transfer Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. Acknowledgement Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. Slave Address Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10.READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11.Alternate READ Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 12.WRITE Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Century Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Driver Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Century Bits Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/23
M41T60
Figure 15.AC Testing Input/Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 16.Crystal Isolation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Crystal Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17.Bus Timing Requirements Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline . . . . . . . . 18
Table 11. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data . 19
Figure 19.QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint . . 20
Figure 20.32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M41T60
SUMMARY DESCRIPTION
The M41T60 Serial Access TIMEKEEPER® is a
low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight registers
are used for the clock/calendar function and are
configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a
two-line bi-directional bus. The built-in address
register is incremented automatically after each
WRITE or READ data byte.
The eight clock address locations contain the century, year, month, date, day, hour, minute, and
second; in 24-hour BCD format. Corrections for
28-, 29- (leap year), 30-, and 31-day months are
made automatically.
The M41T60 is supplied in 16-lead QFN package.
Figure 4. Logic Diagram
Table 1. Signal Names
VCC
XI
FT(1)
XO
M41T60
SCL
OFIRQ/OUT(1)
SDA
VSS
AI08869
Note: 1. Open Drain
4/23
XI
Oscillator Input
XO
Oscillator Output
FT
Frequency Test Output (Open
Drain)
SDA
Serial Data Address Input /
Output
SCL
Serial Clock
OFIRQ/OUT
Oscillator Fail Interrupt/OUT
Output (Open Drain)
VCC
Supply Voltage
VSS
Ground
M41T60
Figure 5. Block Diagram
FT(1)
FT
OUT
OFIRQ/OUT(1)
OFIE
1 Hz
OSCILLATOR
FAIL DETECT
XI
OSCILLATOR
32.768 kHz
SECONDS
DIVIDER
XO
MINUTES
HOURS
CONTROL
LOGIC
VCC
VSS
DAY
DATE
SCL
CENTURY/
MONTH
SERIAL
BUS
INTERFACE
YEAR
ADDRESS
REGISTER
SDA
CALIBRATION
AI08871
Note: 1. Open drain output.
Figure 6. Hardware Hookup for Battery Back-up Operation
VCC
MCU
M41T60
VCC
XI
XO
VSS
VCC
(1)
OFIRQ/OUT
(1)
FT
Port
Port
SCL
Serial Clock Line
SDA
Serial Data Line
AI10476
Note: 1. Open drain output.
5/23
M41T60
OPERATION
The M41T60 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave address (D0h). The 8 bytes contained in the device
can then be accessed sequentially in the following
order:
1. Seconds Register
2. Minutes Register
3. Hours Register
4. Day Register
5. Date Register
6. Century/Month Register
7. Years Register
8. Calibration Register
2-Wire Bus Characteristics
This bus is intended for communication between
different ICs. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
6/23
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition, a device that gives out a message is
called “transmitter”, the receiving device that gets
the message is called “receiver”. The device that
controls the message is called “master”. The devices that are controlled by the master are called
“slaves”.
Acknowledge. Each byte of eight bits is followed
by one Acknowledge Bit. This Acknowledge Bit is
a low level put on the bus by the receiver, whereas
the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also, a master receiver must generate
an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse
in such a way that the SDA line is a stable Low during the High period of the acknowledge related
clock pulse. Of course, setup and hold times must
be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not
generating an acknowledge on the last byte that
has been clocked out of the slave. In this case, the
transmitter must leave the data line High to enable
the master to generate the STOP condition.
M41T60
Figure 7. Serial Bus Data Transfer Sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
Figure 8. Acknowledgement Sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
7/23
M41T60
READ Mode
In this mode, the master reads the M41T60 slave
after setting the slave address (see Figure 9). Following the WRITE Mode Control Bit (R/W = 0) and
the Acknowledge Bit, the word address An is written to the on-chip address pointer. Next the
START condition and slave address are repeated,
followed by the READ Mode Control Bit (R/W = 1).
At this point, the master transmitter becomes the
master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave
transmitter. The address pointer is only incremented on reception of an Acknowledge Bit. The
M41T60 slave transmitter will now place the data
byte at address An+1 on the bus. The master receiver reads and acknowledges the new byte and
the address pointer is incremented to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (0h to 6h). The update will resume due to
a Stop Condition or when the pointer increments to
any non-clock address (7h).
An alternate READ Mode may also be implemented, whereby the master reads the M41T60 slave
without first writing to the (volatile) address pointer. The first address that is read is the last one
stored in the pointer (see Figure 11., page 9).
WRITE Mode
In this mode the master transmitter transmits to
the M41T60 slave receiver. Bus protocol is shown
in Figure 12., page 9. Following the START condition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed
device that word address An will follow and is to be
written to the on-chip address pointer. The data
word to be written to the memory is strobed in next
and the internal address pointer is incremented to
the next address location on the reception of an
acknowledge clock. The M41T60 slave receiver
will send an acknowledge clock to the master
transmitter after it has received the slave address
and again after it has received the word address
and each data byte (see Figure 9).
Figure 9. Slave Address Location
R/W
START
A
1
LSB
MSB
SLAVE ADDRESS
1
0
1
0
0
0
AI00602
8/23
M41T60
SLAVE
ADDRESS
DATA n+1
ACK
DATA n
ACK
S
ACK
BUS ACTIVITY:
R/W
START
WORD
ADDRESS (An)
ACK
S
R/W
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. READ Mode Sequence
STOP
SLAVE
ADDRESS
P
AI00899
NO ACK
DATA n+X
STOP
SLAVE
ADDRESS
P
NO ACK
BUS ACTIVITY:
DATA n+X
ACK
DATA n+1
ACK
DATA n
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
START
Figure 11. Alternate READ Mode Sequence
AI00895
SLAVE
ADDRESS
STOP
DATA n+X
P
ACK
DATA n+1
ACK
BUS ACTIVITY:
DATA n
ACK
WORD
ADDRESS (An)
ACK
S
ACK
SDA LINE
R/W
BUS ACTIVITY:
MASTER
START
Figure 12. WRITE Mode Sequence
AI00591
9/23
M41T60
CLOCK OPERATION
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32.768KHz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC. The eight-byte Clock Register (see Table 2., page 11) is used to both set the
clock and to read the date and time from the clock,
in a binary coded decimal format. Seconds, Minutes, and Hours are contained within the first three
registers.
Bits D6 and D7 of Clock Register 05h (Century/
Month Register) contain the CENTURY Bit 0
(CB0) and the CENTURY Bit 1 (CB1). See Table
3., page 13 for additional explanation. Bits D0
through D2 of Register 03h contain the Day (day
of the week). Registers 04h, 05h, and 06h contain
the Date (day of the month), Century/Month, and
Years. the eighth clock register is the Calibration
Register (this is described in the Clock Calibration
section). Bit D7 of Register 00h contains the STOP
Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0,' the oscillator restarts within one second (typical).
Note: Upon initial power-up, the user should set
the ST Bit to a '1,' then immediately reset the ST
Bit to '0.' This provides an additional “kick-start” to
the oscillator circuit.
Bit D7 of Register 01h contains the Oscillator Fail
Interrupt Enable Bit (OFIE - see the description in
the Oscillator Fail Detection section).
Note: A WRITE to ANY location within the first
seven bytes of the clock register (0h-6h), including
the OFIE and ST Bit, will result in an update of the
system clock and a reset of the divider chain. This
could result in an inadvertent change of the current
time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also
written.
The seven Clock Registers may be read one byte
at a time, or in a sequential block. The Calibration
Register (Address location 7h) may be accessed
independently. Provision has been made to ensure that a clock update does not occur while any
of the clock addresses are being read. If a clock
address is being read, an update of the clock registers will be halted. this will prevent a transition of
data during the READ.
Calibrating the Clock
The M41T60 is driven by a quartz-controlled oscillator with a nominal frequency of 32,768Hz. The
accuracy of the clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscillator circuit and the
capacitive load for which the crystal was trimmed.
10/23
The M41T60 oscillator is designed for use with a
6pF crystal load capacitance. When the Calibration circuit is properly employed, accuracy improves to better than ±2 ppm at 25°C.
The oscillation rate of crystals changes with temperature (see Figure 13., page 12). The M41T60
design employs periodic counter correction. The
calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 256
stage, as shown in Figure 14., page 12. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration Bits found in the Calibration
Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower-order bits (D4-D0)
in the Calibration Register 07h. These bits can be
set to represent any value between 0 and 31 in binary format. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64-minute cycle. The
first 62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary '1'
is loaded into the register, only the first 2 minutes
in the 64-minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is,
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per day which
corresponds to a total range of +5.5 or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M41T60 may require:
– The first involves setting the clock, letting it run
for a month and comparing it to a known
accurate reference and recording deviation
over a fixed period of time. Calibration values,
including the number of seconds lost or gained
in a given period, can be found in Application
Note 934, “TIMEKEEPER® CALIBRATION.”
This allows the designer to give the end user
the ability to calibrate the clock as the
environment requires, even if the final product
is packaged in a non-user serviceable
enclosure. The designer could provide a
simple utility that accesses the Calibration
byte.
M41T60
–
The second approach is better suited to a
manufacturing environment, and involves the
use of the Frequency Test (FT) pin. The FT pin
will toggle at 512Hz when the ST Bit is set to
'0,' and the OUT Bit and FT Bit are set to '1.'
Any measured deviation from the 512Hz
frequency indicates the degree and direction
of oscillator frequency shift at the test
temperature. For example, a reading of
512.010124Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10
(XX001010) to be loaded into the Calibration
Byte for correction.
Note: Setting or changing the Calibration Byte
does not affect the Frequency Test output
frequency. the FT pin is an open drain pin
which requires a pull-up resistor to VCC for
proper operation. A 500-10k resistor is
recommended in order to control the rise time.
Table 2. Register Map
Data
Address
D7
D6
D5
D4
D3
D2
D1
D0
Function/Range
BCD Format
0
ST
10 Seconds
Seconds
Seconds
00-59
1
OFIE
10 Minutes
Minutes
Minutes
00-59
2
0
0
Hours
Hours
00-23
3
0
0
Day
01-07
4
0
0
Date
Date
01-31
5
CB1
CB0
Month
Century/Month
0-3/01-12
Years
Year
00-99
6
7
10 Hours
0
0
10 Date
0
10 Years
OUT
FT
S
Keys: 0 = Must be set to '0.'
CB0, CB1 = Century Bits
FT = Frequency Test Bits
OFIE = Oscillator Fail Interrupt Enable Bit
10 M.
0
Day
Calibration
Calibration
OUT = Output level
S = Sign Bit
ST = STOP Bit
11/23
M41T60
Figure 13. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
∆F = K x (T – T )2
O
F
–80
2
2
K = –0.036 ppm/°C ± 0.006 ppm/°C
–100
TO = 25°C ± 5°C
–120
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI07888
Figure 14. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
12/23
M41T60
Century Bits
These two bits will increment in a binary fashion at
the turn of the century, and handle leap years correctly. See Table 3 for additional explanation.
Output Driver Pin
When the OFIE Bit is not set to generate an interrupt, the OFIRQ/OUT pin becomes an output driver that reflects the contents of D7 of the Calibration
Register. In other words, when D7 (OUT Bit) is a
'0,' then the OFIRQ/OUT pin will be driven low.
Note: The OFIRQ/OUT pin is an open drain which
requires an external pull-up resistor.
Oscillator Stop Detection
In the event that the oscillator has either stopped,
or was stopped for some period of time, and if the
Oscillator Fail Interrupt Enable (OFIE) Bit is set to
a '1,' an interrupt will be generated. This interrupt
can be used to judge the validity of the clock and
date data.
The interrupt will be active any time the oscillator
stops while VCC is ≥ 1.0V. The following conditions
will cause the OFIRQ pin to be active:
– the ST Bit is set to '1.'
– external interference or removal of the crystal.
The Oscillator Fail Interrupt (OFIRQ) will remain
active until the OFIE Bit is reset to '0,' or the oscillator restarts.
The oscillator must start and have run for at least
4 seconds before attempting to set the OFIE Bit to
'1.'
Initial Power-on Defaults
Upon initial application of power to the device, the
OUT Bit will be set to a '1,' while the ST, OFIE, and
FT Bits will be set to '0.' All other Register bits will
initially power-on in a random state.
Table 3. Century Bits Examples
CB0
CB1
Leap Year?
Example(1)
0
0
Yes
2000
0
1
No
2100
1
0
No
2200
1
1
No
2300
Note: 1. Leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. The only exceptions
are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not).
13/23
M41T60
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 4. Absolute Maximum Ratings
Sym
Parameter
Conditions(1)
Value(2)
Unit
TSTG
Storage Temperature (VCC Off, Oscillator Off)
–55 to 125
°C
VCC
Supply Voltage
–0.3 to 4.6
V
260
°C
–0.2 to Vcc+0.3
V
TSLD
(3)
VIO
Lead Solder Temperature for 10 Seconds
Input or Output Voltages
IO
Output Current
20
mA
PD
Power Dissipation
1
W
VESD(HBM)
VESD(RCDM)
Electro-static discharge voltage (Human Body Model)
TA = 25°C
>1000
V
Electro-static discharge voltage (Robotic Charged Device
Model)
TA = 25°C
>1000
V
Note: 1. Test conforms to JEDEC standard.
2. Data based on characterization results, not tested in production.
3. Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds).
14/23
M41T60
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 5. Operating and AC Measurement Conditions
Parameter
M41T60
Supply Voltage (VCC)
1.3V to 3.6V
Ambient Operating Temperature (TA)
–40 to 85°C
Load Capacitance (CL)
50pF
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0.2VCC to 0.8 VCC
Input and Output Timing Ref. Voltages
0.3VCC to 0.7 VCC
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 15. AC Testing Input/Output Waveform
Figure 16. Crystal Isolation Example
Local Grounding Plane
(Layer 2)
XI
Crystal
0.8VCC
0.7VCC
XO
GND
0.3VCC
0.2VCC
AI02568
AI09127
Note: Substrate pad should be tied to VSS.
Table 6. Capacitance
Symbol
CIN
COUT(3)
tLP
Parameter(1,2)
Min
Max
Unit
Input Capacitance (SCL)
7
pF
Output Capacitance (SDA, OUT)
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Note: 1. Effective capacitance measured with power supply at 3.6V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
15/23
M41T60
Table 7. DC Characteristics
Sym
Parameter
VCC(3) Operating Voltage
ICC1
Min
Clock(2)
I2C Bus (400kHz)
SCL = 400kHz
(No Load)
Supply Current
SCL = 0Hz
All inputs
≥ VCC – 0.2V
≤ VSS + 0.2V
Supply Current
(Standby)
ICC2
Test Condition(1)
Typ
Max
Unit
1.0
3.6
V
1.3
3.6
V
100
µA
VCC = 3.6V
50
VCC = 3.0V
35
µA
VCC = 2.5V
30
µA
VCC = 2.0V
20
µA
3.6V
375
3.0V @ 25°C
350
nA
2.0V @ 25°C
310
nA
700
nA
VIL
Input Low Voltage
–0.2
0.3 VCC
V
VIH
Input High Voltage
0.7 VCC
VCC + 0.3
V
VCC = 3.6V, IOL = 3mA (SDA)
0.4
V
VOL
Output Low Voltage
VCC = 3.6V, IOL = 1mA (OFIRQ/OUT)
0.4
V
Pull-up Supply
Voltage (Open Drain)
FT, OFIRQ/OUT
3.6V
V
ILI
Input Leakage
Current
0V ≤ VIN ≤ VCC
–1.0
+1.0
µA
ILO
Output Leakage
Current
0V ≤ VOUT ≤ VCC
–1.0
+1.0
µA
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3 to 3.6V (except where noted).
2. Oscillator start-up guaranteed at 1.5V only.
3. When using battery back-up, VCC fall time should not exceed 10mV/µs.
Table 8. Crystal Electrical Characteristics
Symbol
Parameter(1,2)
fO
Resonant Frequency
RS
Series Resistance
CL
Load Capacitance
Min
Typ
Max
32.768
kHz
65(3)
6
Unit
kΩ
pF
Note: 1. These values are externally supplied. STMicroelectronics recommends the Citizen CFS-145 (1.5x5mm) and the KDS DT-38
(3x8mm) for thru-hole, or the KDS DMX-26S (3.2x8mm) for surface-mount, tuning fork-type quartz crystals.
KDS can be contacted at [email protected] or http://www.kdsj.co.jp.
Citizen can be contacted at [email protected] or http://www.citizencrystal.com.
2. Load capacitors are integrated within the M41T60. Circuit board layout considerations for the 32.768KHz crystal of minimum trace
lengths and isolation from RF generating signals should be taken into account.
3. Guaranteed by design.
16/23
M41T60
Table 9. Oscillator Characteristics
Symbol
Parameter
VSTA
Oscillator Start Voltage
tSTA
Oscillator Start Time
Conditions
Min
≤ 10 seconds
1.5
Typ
Max
Unit
V
VCC = 3.0V
1
s
Cg
XIN
12
pF
Cd
XOUT
12
pF
IC-to-IC Frequency Variation (1)
–10
+10
ppm
Note: 1. Reference value. T A = 25°C, VCC = 3.0V, CMJ-145 (CL = 6pF, 32,768Hz) manufactured by Citizen.
Figure 17. Bus Timing Requirements Sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Note: P = STOP and S = START
Table 10. AC Characteristics
Parameter(1)
Symbol
Min
Typ
Max
Unit
400
kHz
fSCL
SCL Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
0
tR
SDA and SCL Rise Time
300
ns
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
Data Setup Time
100
ns
tHD:DAT(2)
Data Hold Time
0
µs
STOP Condition Setup Time
600
ns
Time the bus must be free before a new transmission can start
1.3
µs
tSU:STO
tBUF
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 1.3 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
17/23
M41T60
PACKAGE MECHANICAL INFORMATION
Figure 18. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Outline
D
E
A3
A
A1
ddd C
e
b
L
K
1
2
E2
Ch
3
K
D2
QFN16-A
Note: Drawing is not to scale.
18/23
M41T60
Table 11. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm body size, Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
0.90
0.80
1.00
0.035
0.032
0.039
A1
0.02
0.00
0.05
0.001
0.000
0.002
A3
0.20
–
–
0.008
–
–
b
0.25
0.18
0.30
0.010
0.007
0.012
D
3.00
2.90
3.10
0.118
0.114
0.122
D2
1.70
1.55
1.80
0.067
0.061
0.071
E
3.00
2.90
3.10
0.118
0.114
0.122
E2
1.70
1.55
1.80
0.067
0.061
0.071
e
0.50
–
–
0.020
–
–
K
0.20
–
–
0.008
–
–
L
0.40
0.30
0.50
0.016
0.012
0.020
ddd
–
0.08
–
–
0.003
–
Ch
–
0.33
–
–
0.013
–
N
16
16
19/23
M41T60
Figure 19. QFN16 – 16-lead, Quad, Flat Package, No Lead, 3x3mm, Recommended Footprint
1.60
3.55
2.0
0.28
AI09126
Note: Substrate pad should be tied to VSS.
Figure 20. 32KHz Crystal + QFN16 vs. VSOJ20 Mechanical Data
7.0 ± 0.3
VSOJ20
6.0 ± 0.2
3.2
SMT
CRYSTAL
1
XI
2
XO
2.9
3
4
1.5
ST QFN16
2.9
AI11146
Note: Dimensions shown are in millimeters (mm).
20/23
M41T60
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M41T
60
Q
6
F
Device Family
M41T
Device Type and Supply Voltage
60 = VCC = 1.3 to 3.6V
Package
Q = QFN16
Temperature Range
6 = –40 to 85°C
Shipping Method
F = Lead-Free Package, Tape & Reel
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
21/23
M41T60
REVISION HISTORY
Table 13. Document Revision History
Date
Version
Revision Details
November 13, 2003
1.0
First Issue
20-Nov-03
1.1
Update characteristics (Figure 3, 4, 5; Table 1, 2, 5, 7, 10)
25-Dec-03
2.0
Reformatted; add crystal isolation, footprint (Figure 16)
13-Jan-04
2.1
Update characteristics (Figure 13, 14, 16; Table 7, 12)
26-Feb-04
2.2
Update characteristics and mechanical dimensions (Figure 18, 19; Table 4, 7, 11)
02-Mar-04
2.3
Update characteristics (Table 7)
26-Apr-04
3.0
Reformat and republish
13-May-04
4.0
Update characteristics (Table 4, 7, 8; Figure 16, 19)
06-Aug-04
5.0
Update characteristics (Figure 5; Table 7, 9)
25-Oct-04
6.0
Document Status Promotion; update characteristics (Figure 4, ; Table 4, 5, 7, 8, 9,
12)
20-Dec-04
7.0
Corrected footprint; update characteristics (Figure 6, 19; Table 4, 7)
05-May-05
8.0
Add package comparison and mechanical data (Figure 2, 20)
M41T60, 41T60, T60, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,
NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,
TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial,
Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Access,
Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access,
Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, Access, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C,
I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C, I2C,
I2C, I2C, I2C, I2C, Leap year, Leap year, Leap year, Leap year, Leap year, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock,
clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock,
clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock,
clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock,
clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock,
clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial,
Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Industrial, Temperature, Temperature, Temperature,
Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature,
Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Temperature, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor, Microprocessor,
Microprocessor, Microprocessor, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 2V, 5V,
5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,
5V, 5V, 5V, 5V, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP, DIP,
DIP, DIP, DIP, DIP, DIP
22/23
M41T60
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
23/23