SL2524 1.3GHz Dual Wideband Logarithmic Amplifier DS4548 - 2.1 July 1995 The SL2524 is a pin compatible replacement for the SL2521 and SL2522 series of log amplifiers, and exhibits a superior stability performance. The amplifier is a successive detection type which provides linear gain and accurate logarithmic signal compression over a wide bandwidth. The two stages can be operated independently. When six stages (three SL2524s) are cascaded the strip can be used for IFs between 30-650MHz whilst achieving greater than 65dB dynamic range with a log accuracy of <±1.0dB. The balanced limited output also offers accurate phase information with input amplitude. FEATURES ■ ■ ■ ■ ■ ■ 1.3GHz Bandwidth (-3dB) Balanced IF limiting 3ns Rise Times/5ns Fall Times (six stages) 20ns Pulse Handling (six stages) Temperature Stabilised Surface Mountable APPLICATIONS ■ ■ ■ Ultra Wideband Log Receivers Channelised Receivers Monopulse Applications OPTIONAL PIN REFERENCE ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC above VEE) +7.0V Storage temperature -65°C to +150°C Operating temperature range SL2524/B/LC -40°C to +85°C SL2524/C/HP -30°C to +85°C Junction temperature - LC20 +175°C - HP20 +150°C Applied DC voltage to RF input ±0.4V (between RF I/P pins) Applied RF power to RF input +15dBm NOT less than 180Ω Value of RSET resistors Thermal resistance:Die to case -LC 20 28°C/W - HP20 20°C/W Die to ambient - LC20 73°C/W - HP20 82°C/W ORDERING INFORMATION SL2524/B/LC (Ceramic leadless chip carrier package) SL2524/C/HP (Plastic J lead chip carrier package) SL2524/NA/1C (DC probe tested bare die) 5962 - 92315 (SMD) PIN DESCRIPTION PIN DESCRIPTION 1 2 3 4 5 6 7 8 9 10 SUB VEE IF OUTPUT (A) IF OUTPUT (A) VEE (A) OUTPUT VC (A) IF INPUT (A) IF INPUT (A) VCC (A) DET. OUTPUT (A) R SET (A) 11 12 13 14 15 16 17 18 19 20 N/C R SET (B) DET. OUTPUT (B) VCC (B) IF OUTPUT (B) IF OUTPUT (B) OUTPUT VCC (B) VEE (B) IF INPUT (B) IF INPUT (B) Fig.1 Pin connections top view SL2524 Fig.2 Circuit diagram of single stage A - (stage B pin Nos bracketed) Fig.3 Pad map for SL2524 naked die 2 SL2524 ELECTRICAL CHARACTERISTICS - SL2524B Guaranteed at the following test conditions unless otherwise stated Frequency = 200MHz, Tamb = +25°C, Input power = -30dBm, VCC = 6V ±0.1V, Source Impedance = 50Ω. Load impedance = 50Ω, Test Circuit = Fig. 4, RSET = 300Ω. Tested as a dual stage. Characteristic Value Units Conditions Min Typ Max Supply current 70 87 100 mA Small signal gain (dual stage, single ended) 9.6 11.4 13.0 dB Tamb = +25°C f = 25MHz See Notes 1, 3 10.1 9.9 9.5 11.6 11.3 11.0 13.1 12.7 12.5 dB dB dB Tamb = -40°C f = 200MHz See Notes 2, 3 Tamb = +25°C f = 200MHz See Note 3 Tamb = +85°C f = 200MHz See Notes 2, 3 9.7 9.3 8.2 11.2 10.7 9.7 12.7 12.1 11.2 dB dB dB Tamb = -40°C f = 500MHz See Notes 2, 3 Tamb = +25°C f = 500MHz See Note 3 Tamb = +85°C f = 500MHz See Notes 2, 3 3.20 3.45 3.70 mA 3.05 3.25 3.45 mA 3.15 3.10 3.30 3.30 3.45 3.50 mA mA Tamb = +25°C, VIN = 0dBm, f = 25MHz See Note 1 Tamb = -40°C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = +25°C, VIN = 0dBm, f = 200MHz Tamb = +85°C, VIN = 0dBm, f = 200MHz See Note 2 2.80 3.10 3.30 mA 2.90 2.85 3.15 3.10 3.45 3.65 mA mA Detected output current (no signal) 0.85 0.80 0.80 0.95 0.93 0.90 1.15 1.10 1.10 mA mA mA Tamb = -40°C, See Note 2 Tamb = +25°C, See Note 2 Tamb = +85°C, See Note 2 Upper cut off frequency (RF) 600 1100 MHz 900 1100 MHz -3dB w.r.t 200MHz, Tamb = -40°C See Note 2 -3dB w.r.t 200MHz, Tamb = +25°C 600 800 MHz -3dB w.r.t 200MHz, Tamb = +85°C See Note 2 MHz -3dB w.r.t 200MHz, Tamb = +25°C MHz 50% O/P current w.r.t. 200MHz I/P power = 0dBm, Tamb = +25°C Detected output current (max) Lower cut off frequency (RF) 0.35 Detector cut off frequency 700 1 155 175 mV 0±2.0 0±3.0 Degree -4.0±2.0 -4.0±3.0 Degree Limited O/P var with temp. ±12 ±25 mV Noise figure 14 dB Max I/P before overload 15 dBm Input impedance 1 kΩ Output impedance 50 Ω Limited IF O/P voltage Phase variation with input level (normalised to -30dBm) 135 Tamb = -40°C, VIN = 0dBm, f = 500MHz See Note 2 Tamb = +25°C, VIN = 0dBm, f = 500MHz Tamb = +85°C, VIN = 0dBm, f = 500MHz See Note 2 Frequency = 70MHz, -55 to +3dBm See Note 2 Frequency = 200MHz, -55 to +3dBm See Note 2 See Note 1 1kΩ in parallel with 2pF NOTES 1. Parameter guaranteed but not tested 2. Tested at 25°C only, but guaranteed at temperature 3. Gain will typically increase by 6dB, when RF outputs use 1kΩ loads in place of 50Ω 3 SL2524 ELECTRICAL CHARACTERISTICS - SL2524C Guaranteed at the following test conditions unless otherwise stated Frequency = 200MHz, Tamb = +25°C, Input power = -30dBm, VCC = 6V ±0.1V, Source Impedance = 50Ω. Load impedance = 50Ω, Test Circuit = Fig. 4, RSET = 300Ω. Tested as a dual stage. Characteristic Value Units Conditions Min Typ Max Supply current 70 87 100 mA Small signal gain (dual stage, single ended) 9.6 11.4 13.0 dB Tamb = +25°C f = 25MHz See Note 3 9.6 9.4 9.0 11.6 11.3 11.0 13.6 13.2 13.0 dB dB dB Tamb = -30°C f = 200MHz See Notes 2, 3 Tamb = +25°C f = 200MHz See Note 3 Tamb = +85°C f = 200MHz See Notes 2, 3 9.2 8.8 7.7 11.2 10.7 9.7 13.2 12.6 11.7 dB dB dB Tamb = -30°C f = 500MHz See Notes 1, 3 Tamb = +25°C f = 500MHz See Note 1 Tamb = +85°C f = 500MHz See Notes 1, 3 3.20 2.95 3.45 3.25 3.70 3.55 mA mA 3.05 3.00 3.30 3.30 3.55 3.50 mA mA 2.70 3.10 3.30 mA 2.80 3.15 3.55 mA 2.75 3.10 3.75 mA Tamb = +25°C, VIN = 0dBm, f = 25MHz Tamb = -30°C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = +25°C, VIN = 0dBm, f = 200MHz Tamb = +85°C, VIN = 0dBm, f = 200MHz See Note 2 Tamb = -30°C, VIN = 0dBm, f = 500MHz See Note 1 Tamb = +25°C, VIN = 0dBm, f = 500MHz See Note 1 Tamb = +85°C, VIN = 0dBm, f = 500MHz See Note 1 0.75 0.70 0.70 0.95 0.93 0.90 1.25 1.20 1.20 mA mA mA Tamb = -30°C, See Note 2 Tamb = +25°C, See Note 2 Tamb = +85°C, See Note 2 MHz -3dB w.r.t 200MHz, Tamb = +25°C See Note 1 MHz -3dB w.r.t 200MHz, Tamb = +25°C MHz 50% O/P current w.r.t. 200MHz mV I/P power = 0dBm, Tamb = +25°C Detected output current (max) Detected output current (no signal) Upper cut off frequency (RF) 1000 Lower cut off frequency (RF) 0.35 Detector cut off frequency 600 Limited IF O/P voltage Phase variation with input level (normalised to -30dBm) 105 135 2 175 0±2.0 Degree -4.0±2.0 Degree Limited O/P var with temp. ±12 ±25 Noise figure 14 dB Max I/P before overload 15 dBm Input impedance 1 kΩ Output impedance 50 Ω mV NOTES 1. Parameter guaranteed but not tested 2. Tested at 25°C only, but guaranteed at temperature 3. Gain will typically increase by 6dB, when RF outputs use 1kΩ loads in place of 50Ω 4 Frequency = 70MHz, -55 to +3dBm See Note 1 Frequency = 200MHz, -55 to +3dBm See Note 1 See Note 1 1kΩ in parallel with 2pF SL2524 GENERAL DESCRIPTION The SL2524 is primarily intended for use in Radar and EW receivers. Six stages (3 chip carriers) can be cascaded to form a very wideband logarithmic ampifier offering >65dB of input dynamic range, with pulse handling of better than 25ns. (See figs 5 and 6.) A six stange strip also offers balanced IF limiting, linearity (log accuracy) of < ±1.0dB, temperature stabilisation and programmable detector characteristics. The detector has an external resistor set (RSET) pin which allows the major characteristics of the detector to be programmed. With six stage strip it is possible to vary the value of RSET on each detector and so improve the overall log error/linearity. The detector is full wave and good slew rates are achieved with 2ns rise and 5ns fall times (no video filter). The video bandwidth of a six stage strip is typically 600MHz (-3dB). The amplifier also offers balanced IF limiting, low phase shift versus input amplitude, and at an IF of 120MHz, less than 5° of phase change is achievable over the input level of -55dBm to +5dBm. The IF and Video ports can be used simultaneously, so offering phase, frequency and pulse (video) information. A slight loss of dynamic range (2dB) will be observed when the IF ports are used in conjunction with the video. Fig.4 Test circuit Fig.5 Schematic diagram showing configuration of SD Log strip 5 SL2524 Fig.6 Circuit diagram for 6-log strip (results shown in figs. 11 to 24 were achieved with this circuit) Typical characteristics for a dual - stage amplifier (i.e. One SL2524) Fig.7 IF Gain vs frequency of 2 amplifiers (One SL2524) 6 SL2524 Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont. Fig.8 Normalised phase vs CW input level at 50, 250 and 450MHz for 50Ω O/P termination (25°C) Fig.9 Detector current vs RSET at 200MHz (25°C) 7 SL2524 Typical characteristics for a dual - stage amplifier (i.e. One SL2524) cont. Fig.10 Detector current vs frequency at RSET = 200Ω and 500Ω (25°C) Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) Fig.11 Detector bandwidth (25°C) 8 SL2524 Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont. 0 Fig.12 Detected O/P vs CW input at 60, 125, 450 and 600MHz at 25°C Fig.13 Detected O/P vs CW input level and temperature at 60 and 125MHz 9 SL2524 Typical characteristics for a six stage strip, using detected output (Ref. figs 5 & 6) cont. Fig.14 Detected O/P vs CW input level at 450MHz across temperature Fig.15 Typical log linearity of detected output measured at 450MHz (25°C) 10 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.16 IF limiting characteristics at 60MHz and 500MHz (25°C) Fig.17 IF limiting characteristic at 60MHz across temperature 11 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.18 IF limiting characteristic at 500MHz across temperature Fig.19 Small signal gain vs frequency across temperature 12 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.20 Phase deviation vs CW input level (normalised at -30dBm) at 25°C across input frequency Fig.21 Phase deviation vs CW input level (normalised at -30dBm) at 50MHz across temperature 13 SL2524 Typical characteristics for a six stage strip as a low phase shift wideband limiter (Ref. figs 5 & 6) Fig.22 Phase deviation vs CW input level (normalised at -30dBm) at 450MHz across temperature Fig.23 Peak phase deviation over -65dBm → +10dBm CW input level vs CW input frequency. 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