Renesas M61323SP Wide frequency band analog switch Datasheet

M61323SP/FP
Wide Frequency Band Analog Switch
REJ03F0201-0201
Rev.2.01
Mar 31, 2008
Description
The M61323SP/FP is a semiconductor integrated circuit for the RGBHV interface. The device features switching
signals input from two types of image sources and outputting the signals to the CRT display, etc. Synchronous signals,
meeting a frequency band of 10 kHz to 200 kHz, are output at TTL. The frequency band of video signals is 250 MHz,
acquiring high-resolution images, and are optimum as an interface IC with high-resolution CRT display and various
new media.
The M61323SP/FP keeps the power saving mode, and it can reduce ICC about 10 mA under the condition that all VCC
are supplied.
Features
• Frequency band : RGB
250 MHz
H, V
10 kHz to 200 kHz
• Input level:
RGB
0.7 VP-P (Typ.)
H, V TTL input
3 to 5 VO-P (bipolar)
• Only the G channel is provided with Sync-on video output. The TTL format is adopted for HV output.
Application
Display monitor
Recommended Operating Condition
Supply voltage range:
4.75 to 5.25 V
Rated voltage range:
5.0 V
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 1 of 19
M61323SP/FP
Block Diagram
M61323SP
Output (G)
Output (R)
GND
VCC (R)
32
31
30
29
VCC (R)
28
27
26
25
VCC (G)
2
Input1 (R)
VCC (R)
B
4
21
20
6
Input1 (G)
Sync-Sep.
G
7
8
Input1 (B)
VCC (B)
19
18
17
9
10
Input1 (V)
Input1 (H)
V
H
POWER
SAVE SW
GND
5
VCC (G)
22
VCC
VCC (B)
3
23
GND
VCC
Sync-Sep. INPUT
24
Output (V)
Output (H)
VCC (B)
G
VCC (R)
GND
VCC (B)
VCC (G)
R
1
GND
VCC (G)
Sync-Sep. OUT
Output
(G-Buffer)
Output (B)
11
12
Input2 (R)
13
Input2 (G)
Power Save SW
GND
14
15
Input2 (B)
Input SW
16
Input2 (V)
Input2 (H)
M61323FP
GND
VCC (R)
36
35
NC
VCC (R)
34
33
32
1
VCC (R)
30
3
29
5
28
27
B
VCC (B)
4
Sync-Sep. INPUT
26
25
24
6
7
8
GND
GND
9
10
Input1 (R)
Input1 (G)
Input1 (B)
Input1 (V)
VCC (G)
VCC (B)
Input1 (H)
GND
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 2 of 19
22
VCC
21
20
11
12
19
V
H
POWER
SAVE SW
Input2 (R)
GND
23
VCC
Sync-Sep.
G
GND
VCC
VCC
VCC (B)
G
VCC (G)
2
31
Output (V)
Output (H)
GND
VCC (B)
VCC (G)
R
VCC (R)
GND
VCC (G)
Sync-Sep. OUT
Output
(G-Buffer)
Output (B)
Output (G)
Output (R)
NC
13
14
Input2 (G)
Power Save SW
15
16
Input2 (B)
Input SW
17
Input2 (V)
Input2 (H)
18
M61323SP/FP
Pin Arrangement
M61323SP
M61323FP
VCC1 (R)
1
36 NC
31 Output (R)
Input1 (R)
2
35 VCC2 (R)
3
30 GND2 (R)
VCC1 (G)
3
34 Output (R)
Input1 (G)
4
29 VCC2 (G)
Input1 (G)
4
33 GND2 (R)
VCC1 (B)
5
28 Output (G)
VCC1 (B)
5
32 VCC2 (G)
Input1 (B)
6
27 GND2 (G)
Input1 (B)
6
31 Output (G)
7
26
Input1 (H)
7
30 GND2 (G)
Input1 (V)
VCC1 (R)
1
32 VCC2 (R)
Input1 (R)
2
VCC1 (G)
Input1 (H)
VCC2 (B)
8
25 Output (B)
8
29
GND1
9
24 GND2 (B)
GND1
9
28 Output (B)
Input2 (R)
10
23 G Buffer out
GND1
10
27 GND2 (B)
Power Save SW
11
22 Sync SEP in
Input2 (R)
11
26 G Buffer out
Input2 (G)
12
21 Sync SEP out
Power Save SW
12
25 Sync SEP in
Input SW
13
20 VCC3
Input2 (G)
13
24 Sync SEP out
Input2 (B)
14
19 Output (H)
Input SW
14
23 VCC3
Input2 (H)
15
18 Output (V)
Input2 (B)
15
22 VCC3
Input2 (V)
16
17 GND3
Input2 (H)
16
21 Output (H)
Input2 (V)
17
20 Output (V)
NC
18
19 GND3
Input1 (V)
(Top view)
Outline: PRDP0032BA-A (32P4B)
VCC2 (B)
(Top view)
Outline: PRSP0036GA-B (36P2R-D)
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 3 of 19
M61323SP/FP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
7.0
Unit
V
Supply voltage
VCC
Power dissipation
Operating temperature
Storage temperature
Electrostatic discharge
Recommended supply voltage
Pd
Topr
Tstg
Surge
Vopr
1603 (SP), 1068 (FP)
−20 to +85 (SP), −20 to +75 (FP)
−40 to +150
±200
5.0
mW
°C
°C
V
V
Recommended supply voltage range
Vopr'
4.75 to 5.25
V
Electrical Characteristics
(M61323SP VCC = 5.0 V, Ta = 25°C)
Test
Input
SW
Point
SW2 SW4 SW6 SW7 SW8 SW10 SW12 SW14 SW15 SW16 SW22 SW11 SW13
Symbol Min. Typ. Max. Unit (s) Rin1 Gin1 Bin1 Hin1 Vin1 Rin2 Gin2 Bin2 Hin2 Vin2 Sync P.sav Switch
Limits
Item
Circuit current1
ICC

70

mA

b
b
b
b
b
b
b
b
b
b
b
Circuit current2
ICCSTBY


10
mA

b
b
b
b
b
b
b
b
b
b
b
Output DC voltage1
Vdc1

1.5

V
b
b
b
b
b
b
b
b
b
b
b
a
3V
b
Output DC voltage2
Vdc2

1.5

V
b
b
b
b
b
b
b
b
b
b
b
a
3V
a
3V
Output DC voltage3
Vdc3

0.9

V
31
28
25
31
28
25
23
b
b
b
b
b
b
b
b
b
b
b
b
Output DC voltage4
Vdc4

0.9

V
23
b
b
b
b
b
b
b
b
b
b
b
Maximum allowable
input level1
Vimax1

1.8

VP-P
abb
SG1
bab
SG1
bba
SG1
b
b
b
b
b
b
b
b
Maximum allowable
input level2
Vimax2

1.8

VP-P
b
b
b
b
b
abb
SG1
bab
SG1
bba
SG1
b
b
b
a
3V
a
3V
Voltage gain1
GV1
−0.1
0.7
1.3
dB
31
28
25
31
28
25
31
28
25

a
3V
a
3V
a
3V
abb
SG2
bab
SG2
bba
SG2
b
b
b
b
b
b
b
b
a
3V
b
b
b
b
b
b
b
a
3V
a
3V
a
SG2
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
a
SG2
b
b
b
b
a
3V
a
3V
a
3V
b
b
b
RGB SW
Relative voltage gain1 ∆GV1
−0.4
0
0.4
dB
Voltage gain2
−0.1
0.7
1.3
dB
Relative voltage gain2 ∆GV2
−0.4
0
0.4
dB
31
28
25

Voltage gain3
GV3
−0.6
0
0.6
dB
23
b
Voltage gain4
GV4
−0.6
0
0.6
dB
23
b
GV2
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 4 of 19
a
3V
b
Relative to measured values above
b
b
abb
SG2
bab
SG2
bba
SG2
Relative to measured values above
a
3V
M61323SP/FP
Electrical Characteristics (cont.)
Limits
Item
Freq. characteristic1
(100 MHz)
Test
Point SW2 SW4
Symbol Min. Typ. Max. Unit (s) Rin1 Gin1
dB
−1
0
1
abb bab
31
FC1
Relative
Freq.characteristic1
(100 MHz)
∆FC1
−1
0
1
dB
Freq.characteristic2
(100 MHz)
FC2
−1
0
1
dB
Relative
Freq.characteristic2
(100 MHz)
Freq.characteristic3
(250 MHz)
∆FC2
−1
0
1
dB
FC3
−3


dB
Freq.characteristic4
(250 MHz)
FC4
−3


dB
Crosstalk between
two inputs1 (10 MHz)
C.T.I.1

−60
−45
dB
Crosstalk between
two inputs2 (10 MHz)
C.T.I.2

−60
−45
dB
Crosstalk between
C.T.I.3
two inputs3 (100 MHz)

−40
−30
dB
Crosstalk between
C.T.I.4
two inputs4 (100 MHz)

−40
−30
dB
Crosstalk between
channels1 (10 MHz)
C.T.C1

−50
−40
dB
Crosstalk between
channels2 (10 MHz)
C.T.C2

−50
−40
dB
Crosstalk between
C.T.C3
channels3 (100 MHz)

−30
−25
dB
Crosstalk between
C.T.C4
channels4 (100 MHz)

−30
−25
dB
Pulse characteristic1
Tr1

1.6
2.5
ns
Tf1

1.6
2.5
ns
Tr2

1.6
2.5
ns
Tf2

1.6
2.5
ns
Pulse characteristic2
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 5 of 19
SG4
Input
SW6
Bin1
bba
SG4
SW7
Hin1
b
SW
SW8 SW10 SW12 SW14 SW15 SW16 SW22 SW11 SW13
Vin1 Rin2 Gin2 Bin2 Hin2 Vin2 Sync P.sav Switch
b
b
b
b
b
b
a
b
b
3V
28
25

SG4
31
28
25

b
31
28
25
31
28
25
31
28
25
31
28
25
abb
SG5
bab
SG5
bba
SG5
b
b
b
b
b
b
b
b
b
abb
SG5
abb
SG3
bab
SG3
bba
SG3
b
b
b
b
b
b
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
31
28
25
abb
SG4
bab
SG4
bba
SG4
b
b
abb
SG3
Relative to measured values above
b
b
b
a
3V
a
3V
b
b
b
b
a
3V
b
bab
SG5
bba
SG5
b
b
b
a
3V
a
3V
b
b
b
b
b
b
a
3V
a
3V
b
abb
SG3
bab
SG3
bba
SG3
b
b
b
a
3V
b
b
b
b
b
b
b
b
b
a
3V
a
3V
b
b
b
abb
SG4
bab
SG4
bba
SG4
b
b
b
a
3V
b
bab
SG3
bba
SG3
b
b
b
b
b
b
b
b
a
3V
b
b
b
b
b
b
abb
SG3
bab
SG3
bba
SG3
b
b
b
a
3V
a
3V
abb
SG4
bab
SG4
bba
SG4
b
b
b
b
b
b
b
b
a
3V
b
b
b
b
b
b
abb
SG4
bab
SG4
bba
SG4
b
b
b
a
3V
a
3V
abb
SG6
bab
SG6
bba
SG6
b
b
b
b
b
b
b
b
a
3V
b
abb
SG6
bab
SG6
bba
SG6
b
b
b
b
b
b
b
b
a
3V
b
b
b
b
b
b
abb
SG6
bab
SG6
bba
SG6
b
b
b
a
3V
a
3V
b
b
b
b
b
abb
SG6
bab
SG6
bba
SG6
b
b
b
a
3V
a
3V
b
b
b
b
abb
SG4
bab
SG4
bba
SG4
Relative to measured values above
M61323SP/FP
Electrical Characteristics (cont.)
Test
Input
SW
Point SW2 SW4 SW6 SW7 SW8 SW10 SW12 SW14 SW15 SW16 SW22 SW11 SW13
Symbol Min. Typ. Max. Unit (s)
Rin1 Gin1 Bin1 Hin1 Vin1 Rin2 Gin2 Bin2 Hin2 Vin2 Sync P.sav Switch
Limits
Item
HV SW
High level
output voltage1
Vdch1
3.8
4.2

V
18
19
b
b
b
a
SG8
a
SG8
b
b
b
b
b
b
a
3V
b
High level
output voltage2
Vdch2
3.8
4.2

V
18
19
b
b
b
b
b
b
b
b
a
SG8
a
SG8
b
a
3V
a
3V
Low level
output voltage1
Vdcl1

0.2
0.5
V
18
19
b
b
b
a
SG8
a
SG8
b
b
b
b
b
b
a
3V
b
Low level
output voltage2
Vdcl2

0.2
0.5
V
18
19
b
b
b
b
b
b
b
b
a
SG8
a
SG8
b
a
3V
a
3V
Input threshold
voltage H
VithH
1.8
2.0
2.2
V
18
19
b
b
b
a
SG8
a
SG8
b
b
b
b
b
b
a
3V
b
Input threshold
voltage L
VithL
1.0
1.4
1.6
V
18
19
b
b
b
a
SG8
a
SG8
b
b
b
b
b
b
a
3V
b
Rising time3
Tr3

25

ns
b
b
b
b
b
b
b
15

ns
b
b
b
b
b
b
b
b
b
Rising delay time
HVDr

40
60
ns
b
b
b
b
b
b
b
b
b
a
3V
a
3V
a
3V
b

a
SG8
a
SG8
a
SG8
b
Tf3
a
SG8
a
SG8
a
SG8
b
Falling time3
18
19
18
19
18
19
Falling delay time
HVDf

40
60
ns
18
19
b
b
b
a
SG8
a
SG8
b
b
b
b
b
b
a
3V
b
Sync on G input
minimum voltage
SYrv
0.2


VP-P
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
high level voltage
SYVH
3.8
4.3

V
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
low level voltage
SYVL

0.2
0.5
V
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
rising time 3
STr

25

ns
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
falling time 3
STf

15

ns
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
rising delay time
SDr

40
60
ns
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V

Sync output
falling delay time
SDf

40
60
ns
21
b
b
b
b
b
b
b
b
b
b
a
SG7
a
3V


V

a
SG6
a
SG6
a
SG6
a
SG8
a
SG8
b
b
b
b
b
a
SG7
a
3V
variable
a
SG6
a
SG6
a
SG6
a
SG8
a
SG8
b
a
SG7
a
3V
variable
b
b
Sync SEP.
Channel Select SW, Power Save SW

Channel select SW
threshold voltage1
Vthch1
Channel select SW
threshold voltage2
Vthch2
Power save SW
threshold voltage1
VthPH
2.0


V

a
SG6
a
SG6
a
SG6
a
SG8
a
SG8
b
b
b
b
b
a
a
SG7 variable
b
Power save SW
threshold voltage2
VthPL


1.0
V

a
SG6
a
SG6
a
SG6
a
SG8
a
SG8
b
b
b
b
b
a
a
SG7 variable
b
2.5


1.0
V
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 6 of 19

b
b
b
b
a
a
M61323SP/FP
Electrical Characteristics Test Method (M61323SP)
Circuit Current 1
No signal. Measure the total circuit current as ICC when supplying 3 VDC to pin 11.
Circuit Current 2
No signal. Measure the total circuit current as ICCSTBY when pin 11 connected to GND.
Output DC Voltage 1, 2
Set SW13 to GND (or OPEN), measure the DC voltage of TP31 (TP28, TP25) when there is no signal input.
The DC voltage is as vdc1 (vdc2).
Output DC Voltage 3, 4
Measure the DC voltage TP23 same as "Output DC voltage 1, 2". The DC voltage is Vdc3 (Vdc4).
Maximum Allowable Input Level 1, 2
Set SW13 to GND, input SG1 to pin 2 only. Gradually increasing the SG1 amplitude, read the amplitude of the input
signal when the output waveform of TP31 is strained. The value is as Vimax1. In the same way, measure Vimax1 in
response to inputs in pin 4 and pin 6 only.
Then set SW13 to OPEN, measure Vimax2 in response to inputs in pin 10, 12 and 14 only.
Voltage Gain 1, 2
1. The conditions is as table.
2. Set SW13 to GND, input SG2 (0.7 VP-P) to pin 2 only. Read the output amplitude of TP31. The value is as VOR1.
3. Voltage gain GV1 is
GV1 = 20log
VOR1 [VP-P]
0.7
(dB)
4. In the same way, calculate GV1 in response to inputs in pin 4 and pin 6 only.
5. Then set SW13 to OPEN, measure GV2 in response to inputs in pin l0, 12 and 14 only.
Relative Voltage Gain 1, 2
1. Calculate relative voltage gain ∆GV1 by the following formula.
∆GV1 = GV1R − GV1G, GV1G − GV1B, GV1B − GV1R
2. In the same way, calculate ∆GV2
Voltage Gain 3, 4
1. The conditions is as table.
2. Read the output amplitude of TP23.
3. Calculate GV3, GV4 same as "Voltage gain 1".
Freq. Characteristic 1, 2/Relative Freq. Characteristic 1, 2
1. The conditions is as table. This measurement shall use active probe.
2. Set SW13 to GND, input SG4 (0.7 VP-P) to pin 2 only. Measure TP31 output amplitude as VOR1.
In the same way, input SG2 (0.7 VP-P) to pin 2 only. Measure TP31 output amplitude as VOR2.
3. Freq.characteristic1 FC1 is
FC1 = 20log
VOR2 [VP-P]
VOR1 [VP-P]
(dB)
4. In the same way, calculate FC1 in response to inputs in pin 4 and pin 6 only.
5. The difference between of each channel Freq.characteristic is as ∆FC1.
6. Then set SW13 to OPEN, measure FC2 and ∆FC2 in response to inputs in pin 10, 12 and 14 only.
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 7 of 19
M61323SP/FP
Freq. Characteristic 3, 4
Measure the FC3, FC4 when SG5 of input signal. (For reference)
Crosstalk between Two Inputs 1, 2
1.
2.
3.
4.
The conditions is as table. This measurement shall use active probe.
Set SW13 to GND, input SG3 to pin 2 only. Read the output amplitude of TP31. The value is as VOR3.
Then set SW13 to OPEN, read the output amplitude of TP31. The value is as VOR3'.
Crosstalk between two inputs 1 C.T.I.1 is
C.T.I.1 = 20log
5.
6.
7.
8.
VOR3' [VP-P]
VOR3 [VP-P]
(dB)
In the same way, calculate C.T.I.1 in response to inputs in pin 4 and pin 6 only.
Then set SW13 to OPEN, input SG2 to pin 10 only. Read the output amplitude of TP31. The value is as VOR4.
Set SW13 to GND, read the output amplitude of TP31. The value is as VOR4'.
Crosstalk between two inputs 1 C.T.I.2 is
C.T.I.2 = 20log
VOR4' [VP-P]
VOR4 [VP-P]
(dB)
9. In the same way, calculate C.T.I.2 in response to inputs in pin 12 and pin 14 only.
Crosstalk between Two Inputs 3, 4
Set SG4 as the input signal, and then the same method as table, measure C.T.I.3, C.T.I.4.
Crosstalk between Channels 1, 2
1.
2.
3.
4.
The conditions is as table. This measurement shall use active probe.
Set SW13 to GND, input SG3 (0.7 VP-P) to pin 2 only. Read the output amplitude of TP31. The value is as VOR5.
Next, measure TP28, TP25 in the same state, and the amplitude is as VOG5, VOB5.
Crosstalk between channels1 C.T.C1 is
C.T.C1 = 20log
VOG5 or VOB5
VOR5
(dB)
5. In the same way, calculate C.T.C1 in response to inputs in pin 4 and pin 6 only.
6. Then set SW13 to OPEN, input SG3 (0.7 VP-P) to pin 10 only.
Read the output amplitude of TP31. The value is as VOR6.
7. Next, measure TP28, TP25 in the same state, and the amplitude is as VOG6, VOB6.
8. Crosstalk between two inputs 1 C.T.C2 is
C.T.C2 = 20log
VOG6 or VOB6
VOR6
(dB)
9. In the same way, calculate C.T.C2 in response to inputs in pin 9 and pin 11 only.
Crosstalk between Channels 3, 4
Set SG4 as the input signal, and then the same method astable, measure C.T.C3, C.T.C4.
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 8 of 19
M61323SP/FP
Pulse Characteristic 1, 2
1.
2.
3.
4.
The conditions is as table (SG5 amplitude 0.7 VP-P). Set SW13 to GND (or OPEN).
Measure rising Tri and falling Tfi for 10% to 90% of the input pulse with active probe.
Next, measure rising Tro and falling Tfo for 10% to 90% of the output pulse with active probe.
Pulse characteristic Tr1, Tf1 (Tr2, Tf2) is
100%
Tr1 (Tr2) = √ (Tro)2 − (Tri)2
Tf1 (Tf2) = √
(Tfo)2
−
(Tfi)2
90%
(ns)
(ns)
10%
0%
Tr
Tf
<HV-SW>
High Level Output Voltage 1, 2/Low Level Output Voltage 1, 2
1. The conditions is as table. Input SG8 to pin 7 (or pin 8). Set SW13 to GND, read the output high level and low
voltage of TP19, TP18. The value is as Vdch1, Vdcl1.
2. Input SG8 to pin 15 (or pin 16). Set SW13 to OPEN, read the output high level and low voltage of TP19, TP18.
The value is as Vdch2, Vdcl2.
Input Threshold Voltage H/Input Threshold Voltage L
1. Set SW13 to GND (or OPEN). Gradually increasing the voltage of pin 7 (or pin 15) from 0 V, measure the input
voltage of pin 7 (or pin 15) when the TP19 voltage turned high level (3.8 V or more). The value is as VithH.
2. Gradually decreasing the voltage of pin 7 (or pin 15) from 3 V, measure the input voltage of pin 7 (or pin 15) when
the TP19 voltage turned low level (0.5 V or less). The value is as VithL.
3. In the same way, measure the input voltage of pin 8 (or pin 16) as VithH, VithL.
Rising Time/Falling Time
1. The conditions is as table. This measurement shall use active probe.
2. Measure rising Tri and falling Tfi for 20% to 80% of the output pulse as Tr3, Tf3 (Tr4, Tf4).
100%
80%
20%
0%
Tr'
Tf'
Rising Delay Time/Falling Delay Time
Set SW13 to GND (or OPEN), input SG8 to pin 7 (or pin 15).
Measure the rising delay time HVDr and the falling delay time HVDf.
In the same way, measure HVDr and HVDf when input SG8 to pin 8 (or pin 16)
50%
SG8
HVDr
Waveform output
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 9 of 19
HVDf
50%
M61323SP/FP
<Sync-Separation>
Sync Input Minimum Voltage
Gradually decreasing the amplitude of SG7 in pin 22, measure the amplitude of SG7 when the Sync-Sep output signal
turn off. The value is as SYrv.
Sync Output High Level Voltage/Sync Output Low Level Voltage
Input SG7 to pin 22, read the output high level and low voltage of TP21. The value is as SYVH, SYVL.
Sync Output Rising Time/Sync Output Falling Time
1. The conditions is as table. (SG7 amplitude 0.3 VP-P)
This measurement shall use active probe.
2. Measure rising Tri and falling Tfi for 10% to 90% of the input pulse as STr, STf.
100%
90%
10%
0%
STr
STf
Sync Output Rising Delay Time/Sync Output Falling Delay Time
Input SG7 to pin 22. Measure the rising delay time SDr and the falling delay time SDf.
50%
SG7
SDr
Waveform output
SDf
50%
<Others>
Channel Select SW Threshold 1, 2
1. Gradually increasing the voltage of pin 13 from 0 V, measure the maximum voltage of pin 13 when the channel 1 is
selected. The value is as Vthch1.
2. Gradually decreasing the voltage of pin 13 from 5 V, measure the minimum voltage of pin 13 when the channel 2 is
selected. The value is as Vthch2.
Power Save SW Threshold 1, 2
1. Gradually increasing the voltage of pin 11 from 0 V, measure the maximum voltage of pin 11 when the power save
mode. The value is as VthPL.
2. Gradually decreasing the voltage of pin 13 from 5 V, measure the minimum voltage of pin 11 when the power save
mode. The value is as VthPH.
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 10 of 19
M61323SP/FP
Input Signal
SG No.
SG1
Signals
Sine wave (f = 60 kHz, 0.7 VP-P (Amplitude variable) )
0.7 VP-P
(variable)
SG2
SG3
SG4
SG5
SG6
Sine wave (f = 1 MHz, 0.7 VP-P (Amplitude variable) )
Sine wave (f = 10 MHz, 0.7 VP-P (Amplitude variable) )
Sine wave (f = 100 MHz, 0.7 VP-P (Amplitude variable) )
Sine wave (f = 250 MHz, 0.7 VP-P (Amplitude variable) )
DUTY 80%
fH = 60 kHz
0.7 VP-P
0.7 VP-P
SG7
Sync (fH = 60 kHz)
Amplitude variable
(Typ. = 0.3 VP-P)
4.5 µs
SG8
TTL
5V
DUTY 50%
fH = 60 kHz
0V
Typical Characteristics
Thermal Derating (M61323SP)
Thermal Derating (M61323FP)
1750
1750
Power Dissipation Pd (mW)
Power Dissipation Pd (mW)
1603
1500
1250
1000
833
750
500
250
0
−25
1500
1250
1068
1000
750
640
500
250
0
25
50
75
85
100
125
Ambient Temperature Ta (°C)
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 11 of 19
150
0
−25
0
25
50
75
100
125
Ambient Temperature Ta (°C)
150
M61323SP/FP
Test Circuit (M61323SP)
TP23
SG
SS
b
0.01 µ
a
VCCC 5 V
SW22
29
G-SW
VCC
0.01 µ
24
23
4
TP19 TP18
22
21
20
6
7
8
9
10
0.01 µ
11
12
13
TP11
TP13
SW11
SW13
SW7 SW8
a
SW2
a
SW4
b
a
ba
17
14
15
16
a
SG
RGB
+
75
+
75
+
SW15 SW16
75
b
a
SW6
b
18
a b c
open
47 µ
47 µ
75
0.01 µ
75
19
+
47 µ
75
0.01 µ
+
47 µ
0.01 µ
a b c
open
+
47 µ
ECO-SW
5
0.01 µ
0.01 µ
a
A
VCC
47 µ
0.01 µ
25
0.01 µ
VCC A 5 V
26
1µ
B-OUT
VCC
B-SW
VCC
3
47 µ
SW A
2
0.01 µ
b
0.01 µ
1
a
27
G-OUT
VCC
R-SW
VCC
+
28
TP21
47 µ
30
47 µ
+
31
R-OUT
VCC
b
TP25
0.01 µ
47 µ
47 µ
0.01 µ
TP28
+
32
SW C
a
SW26
+
A
SW B b
A
b
TP31
a
VCCB
5V
a
SW29
0.01 µ
b
+
a
SW32
+
+
b
47 µ
SW10
b
a
SW12
b
a
b a
SW14
b
a
b
SG
HV
Units Resistance: Ω
Capacitance: F
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 12 of 19
b
M61323SP/FP
Application Example (M61323SP)
OUTPUT
VCC
5V
+
ROUT
GOUT
BOUT
G Buffer OUT
Sync SEP OUT
47 µ
Hout
47 µ
47 µ
47 µ
+
0.01 µ
+
0.01 µ
+
0.01 µ
0.01 µ
Vout
1µ
+
47 µ
+
30
29
VCC
28
27
26
VCC
R
VCC
(5 V)
75
20
5
19
18
H
75
POWER SAVE VCC
(H-SW, V-SW,
G-Buffer, Sync-SEP)
Power save
SW
6
7
8
9
10
11
12
13
14
15
16
75
75
+
75
+
+
47 µ
+
0.01 µ
0 to 0.8 V : INPUT1
2.0 to 5.0 V: INPUT2
47 µ
+
17
0.01 µ
V
0.01 µ
0.01 µ
47 µ
+
21
Sync
Sepa
G
VCC
(5 V)
4
0.01 µ
0.01 µ
0.01 µ
3
22
0.01 µ
2
23
VCC
B
47 µ
1
24
VCC
G
VCC
(5 V)
25
47 µ
31
0.01 µ
32
0.01 µ
47 µ
47 µ
0.01 µ
VCC
5V
+
VCC
5V
PowerSave VCC
75
INPUT1
INPUT2
Rin1
Gin1
Bin1
Hin1
Vin1
Rin2
Gin2
Bin2
Hin2
Vin2
Units Resistance: Ω
Capacitance: F
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 13 of 19
M61323SP/FP
Pin Description (M61323SP)
pin No.
1
3
5
20
26
29
32
2
4
6
10
12
14
Name
VCC (R)
VCC (G)
VCC (B)
VCC (H, V,
Sync-Sep.)
VCC (ROUT)
VCC (GOUT)
VCC (BOUT)
Input1 (R)
Input1 (G)
Input1 (B)
Input2 (R)
Input2 (G)
Input2 (B)
DC Voltage (V)
5.0
Peripheral Circuit


Function
5.0


Input signal with low impedance
2.3
750
3V
643
2.48 V
2.2 mA
7
8
15
16
Input1 (H)
Input1 (V)
Input2 (H)
Input2 (V)

Input pulse between 3 V and 5 V
3 to 5 V
500
0 to 0.8 V
7k
SW
9
17
24
27
30
GND (V-SW)
GND
(H, V, SyncSep.)
GND (B-out)
GND (G-out)
GND (R-out)
GND
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 14 of 19


M61323SP/FP
Pin Description (M61323SP) (cont.)
pin No.
11
Name
PwrSave-SW
DC Voltage (V)
2.5
Peripheral Circuit
Function
Do not apply more 5 V DC
voltage
30 k
15 k
25 k
2.0 V
10 k
20 k
13
CONT-SW
20 k
25 k
20 k
2.4
Do not apply more 5 V DC
voltage
26 k
15 k
5k
2.4 V
24 k
18
19
Vout
Hout
7.3 k


20 k
100
15 k
15 k
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 15 of 19
M61323SP/FP
Pin Description (M61323SP) (cont.)
pin No.
21
Name
Sync sep OUT
DC Voltage (V)

Peripheral Circuit
Function

15 k
100
15 k
15 k
22
Sync sep IN

Connect a capacitance
between the pin and GND
when not use SYNC-SEP
10 k
10 k
2k
Vth
CLAMPref
23
G Buffer OUT


5k
5k
2k
25
28
31
Video OUT (B)
Video OUT (G)
Video OUT (R)
1.5
32, 29, 26 pin
50
31, 28, 25 pin
30, 27, 24 pin
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 16 of 19

M61323SP/FP
Note How to Use This IC (M61323SP)
1.
2.
3.
4.
R, G, B input signal is 0.7 VP-P of standard video signal.
H, V input is 5.0 V TTL type.
Input signal with sufficient low impedance to input terminal.
The terminal of R, G, B output pin are shown as figure 1.
When resistance is connected between the pin 31 (28, 25) and GND, ICC will be increase.
5. Switch (pin 13) can be changed by supplying some voltage as figure 2.
0 to 0.5 V: INPUT1
2.5 to 5 V: INPUT2
Do not apply VCC or more DC voltage.
6. Power save mode is provided for saving ICC less than about 10 mA as figure 3.
0 to 0.5 V: Power save mode (H.V-SW, Sync-Sep., G-Buffer)
2.5 to 5 V: Normal mode
Do not apply 5 V or more DC voltage
7. When not use the Sync-separation circuit built in this IC, capacitance of several tens of pF is required between the
pin 22 and GND.
5V
I < 5 mA
50 Ω
R
600 Ω
Figure 1
13
Figure 2
11
Figure 3
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 17 of 19
M61323SP/FP
Cautions for Manufacturing Boards
Built-in wide band preamplifier may cause oscillation due to the wiring shape on the board.
Be careful for the following points.
• VCC shall use a stable power supply.
(Individual VCC should use an independent power supply.)
• GND should be as wide as possible. Basically, solid earth should be used.
Make the load capacitance of output pins as small as possible.
• Also ground the hold capacitance to stable GND, which is as near to the pin as possible.
• Insertion of a resistance of several tens of ohms between the output pin and the circuit at the next stage makes
oscillation harder.
• When inserting an output pull-down resistance, make wire between the output pin and the resistance as short as
possible.
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 18 of 19
M61323SP/FP
Package Dimensions
RENESAS Code
PRDP0032BA-A
Previous Code
32P4B
MASS[Typ.]
2.2g
17
1
16
*1
E
32
e1
JEITA Package Code
P-SDIP32-8.9x28-1.78
c
D
Reference
Symbol
e1
D
E
A
A1
A2
bp
b2
b3
c
L
A1
A
A2
*2
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
SEATING PLANE
*3 b
3
e
bp
*3
b2
e
L
JEITA Package Code
P-SSOP36-8.4x15-0.80
RENESAS Code
PRSP0036GA-B
Previous Code
36P2R-D
Min Nom Max
9.86 10.16 10.46
27.8 28.0 28.2
8.75 8.9 9.05
5.08
0.51
3.8
0.35 0.45 0.55
0.63 0.73 1.03
0.9 1.0 1.3
0.22 0.27 0.34
0°
15°
1.528 1.778 2.028
3.0
MASS[Typ.]
0.5g
19
*1
E
36
HE
Dimension in Millimeters
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
18
1
Index mark
c
D
A
*2
A2
y
*3
bp
L
e
A1
Detail F
REJ03F0201-0201 Rev.2.01 Mar 31, 2008
Page 19 of 19
Reference
Symbol
D
E
A2
A
A1
bp
c
HE
e
y
L
Dimension in Millimeters
Min Nom Max
14.8 15.0 15.2
8.2 8.4 8.6
2.05
2.35
0
0.1 0.2
0.3 0.35 0.45
0.18 0.2 0.25
0°
8°
11.63 11.93 12.23
0.65 0.8 0.95
0.10
0.3 0.5 0.7
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