Sony ILX520K 7078 x 3pixel ccd linear sensor (color) Datasheet

ILX520K
7078 × 3pixel CCD Linear Sensor (Color)
For the availability of this product, please contact the sales office.
Description
The ILX520K is a reduction type CCD linear sensor
developing for color image scanner. This sensor reads
A3-size documents at a density of 600 DPI.
GND
Driver
12
7078
7078
GND 12
7078
φROG-R 11
9
7
6
GND
4
φRS
3
Driver
GND
Red
Green
Blue
15 NC
NC 10
S7078
CCD Register Read Out Gate
16 φ2
VOUT-R 2
9
CCD Register Read Out Gate S7078
φ1
VOUT-G 23
17 VDD
CCD Register Read Out Gate S7078
8
A
A
A
A
A
A
AA
AA
NC
VOUT-B 22
18 φ2
18
7
φ2
φ1
5
19 NC
φLH
GND 6
21
20 NC
VDD
5
B
φLH
G
21 VDD
R
4
D14
D15
φRS
φ1
φ2
16
17
VDD
1
1
1
22 VOUT-B
D14
D15
D63
S1
GND 3
D14
D15
23 VOUT-G
D63
S1
2
24 NC
D63
S1
VOUT-R
D64
1
D64
NC
D64
D75
Pin Configuration (Top View)
D75
V
°C
°C
D75
Absolute Maximum Ratings
• Supply voltage
VDD
15
• Operating temperature
–10 to +55
• Storage temperature
–30 to +80
φ1
13 φROG-G
Driver
11 φROG-R
14 φROG-B
Block Diagram
Driver
Features
• Number of effective pixels: 21234 pixels
(7078 pixels × 3)
• Pixel size:
8µm × 8µm (8µm pitch)
• Distance between line:
64µm (8 Lines)
• Single-sided readout
• Ultra low lag / Ultra high sensitivity
• Single 12V power supply
• Input clock pulse:
CMOS 5V drive
• Number of output
3 (R, G, B)
• Package:
24 pin DIP (400 mil)
24 pin DIP
14 φROG-B
13 φROG-G
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96539-ST
ILX520K
Pin Description
Pin No.
Symbol
Description
Pin No.
Symbol
Description
1
NC
NC
13
φROG-G
Clock pulse input
2
VOUT-R
Signal out (red)
14
φROG-B
Clock pulse input
3
GND
GND
15
NC
NC
4
φRS
Clock pulse input
16
φ2
Clock pulse input
5
φLH
Clock pulse input
17
VDD
12V power supply
6
GND
GND
18
φ2
Clock pulse input
7
φ1
Clock pulse input
19
NC
NC
8
NC
NC
20
NC
NC
9
φ1
Clock pulse input
21
VDD
12V power supply
10
NC
NC
22
VOUT-B
Signal out (blue)
11
φROG-R
Clock pulse input
23
VOUT-G
Signal out (green)
12
GND
GND
24
NC
NC
Recommended Supply Voltage
Item
Min.
Typ.
Max.
Unit
VDD
11.4
12
12.6
V
Clock Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
Input capacity of φ1, φ2
Cφ1, Cφ2
—
1100
—
pF
Input capacity of φLH
CφLH
—
10
—
pF
Input capacity of φRS
CφRS
—
10
—
pF
Input capacity of φROG∗
CφROG
—
10
—
pF
∗ It indicates that φROG-R, φROG-G, φROG-B as φROG.
Clock Frequency
Item
Symbol
φ1, φ2, φLH, φRS
fφ1, fφ2, fφLH, fφRS
Min.
Typ.
Max.
Unit
—
1
5
MHz
Input Clock Pulse Voltage Condition
Item
φ1, φ2, φLH, φRS,
φROG pulse voltage
Min.
Typ.
Max.
Unit
High level
4.75
5.0
5.25
V
Low level
—
0
0.1
V
–2–
ILX520K
Electrooptical Characteristics (Note 1)
Ta = 25°C, VDD = 12V, fφRS = 1MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
V/(lx · s)
Note 2
Red
RR
1.3
2.0
2.7
Green
RG
2.1
3.2
4.3
Blue
RB
1.6
2.5
3.4
Sensitivity nonuniformity
PRNU
—
4
20
%
Note 3
Saturation output voltage
VSAT
2
3.2
—
V
Note 4
Red
SER
0.74
1.6
—
Green
SEG
0.46
1
—
lx · s
Note 5
Blue
SEB
0.58
1.28
—
Dark voltage average
VDRK
—
0.3
2
mV
Note 6
Dark signal nonuniformity
DSNU
—
1.5
5
mV
Note 6
Image lag
IL
—
0.02
—
%
Note 7
Supply current
IVDD
—
26
50
mA
—
Total transfer efficiency
TTE
92
98
—
%
—
Output impedance
ZO
—
250
—
Ω
—
Offset level
VOS
—
6.5
—
V
Note 8
Dynamic range
DR
1000
10670
—
—
Note 9
Sensitivity
Saturation
exposure
Note
1) In accordance with the given electrooptical characteristics, the black level is defined as the average value
of D2, D3 to D12.
2) For the sensitivity test light is applied with a uniform intensity of illumination.
3) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2.
VOUT = 500mV (Typ.)
PRNU =
(VMAX – VMIN) /2
VAVE
× 100 [%]
Where the 7078 pixels are divided into blocks of 114 (Last block is 124 pixel). The maximum output of
each block is set to VMAX, the minimum output to VMIN and the average output to VAVE.
4) Use below the minimum value of the saturation output voltage.
5) Saturation exposure is defined as follows.
SE =
VSAT
R
Where R indicates RR, RG, RB, and SE indicates SER, SEG, SEB.
6) Optical signal accumulated time τ int stands at 10ms.
7) VOUT = 500mV (Typ.)
VOUT
8) Vos is defined as indicated bellow.
VOUT indicates VOUT-R, VOUT-G, and VOUT-B.
9) Dynamic range is defined as follows.
DR =
VSAT
VDRK
AA
AA
AAAA
VOS
GND
When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical
signal accumulated time is in proportion to the dark voltage.
–3–
VOUT
φRS
φ2
φ1
φLH
φROG
–4–
AAAAAAA A
D62
D15
D14
D13
4
Dummy signal (63 pixels)
S7077
S7076
S2
S1
D63
1-line output period (7153 pixels)
Optical black (49 pixels)
D61
D3
D2
3
D1
2
1
Note) The transfer pulses (φ1, φ2, φLH) must have more than 7153 cycles.
0
5
0
5
0
5
0
5
Clock Timing Chart 1
ILX520K
D75
7153
D71
D70
D65
D64
S7078
ILX520K
Clock Timing Chart 2
t4
t5
φROG
t2
t7
t6
φ1
t1
t3
φ2
Clock Timing Chart 3
t7
t6
φ1
φLH
φ2
t10
t11
t9
φRS
t8
AAAAAAAA
AAAAAAAA
AAAAAAAA
t13
VOUT
t12
–5–
AAA
AAA
AAA
ILX520K
Clock Pulse Recommended Timing
Item
Symbol
φROG, φ1 pulse timing
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
φROG pulse high level period
φROG, φ1 pulse timing
φROG pulse rise time
φROG pulse fall time
φ1 pulse rise time /φ2 pulse fall time
φ1 pulse fall time /φ2 pulse rise time
φRS pulse high level period
φRS, φLH pulse timing
φRS pulse rise time
φRS pulse fall time
Signal output delay time
∗1 These timing is the recommended condition under fφRS = 1MHz.
–6–
Min.
Typ.
Max.
Unit
50
100
—
ns
1200
1500
—
ns
1200
1500
—
ns
0
5
10
ns
0
5
10
ns
0
20
60
ns
0
20
60
ns
—
ns
—
ns
45
250∗1
250∗1
0
10
30
ns
0
10
30
ns
—
10
—
ns
—
10
—
ns
45
Tr1
47µF/16V
∗ Data rate fφRS = 1MHz.
0.1µF
12V
VOUT-G
5.1kΩ
NC
VOUT-R
2
100Ω
VOUT-R
1
Tr1
3
100Ω
φRS
φLH
7
6
8
2Ω
φ1
9
10
φROG-R
11
IC1
12
IC1: 74AC04
Tr1: 2SC2785
IC1
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
100Ω
4
5
13
14
15
16
17
18
19
20
21
22
2Ω
23
100Ω
φROG-G
24
100Ω
Tr1
VOUT-B
φROG-B
NC
φ2
VOUT-G
5.1kΩ
VOUT-B
5.1kΩ
VDD
GND
NC
φRS
NC
φLH
φ2
GND
–7–
φ1
VDD
NC
φ2
φ1
NC
NC
φROG-B
φROG-R
φROG-G
GND
Application Circuit∗
ILX520K
ILX520K
Example of Representative Characteristics (VDD = 12V, Ta = 25°C)
Spectral sensitivity characteristics (Standard characteristics)
1
Relative sensitivity
0.8
0.6
0.4
0.2
0
400
450
500
550
600
650
700
Wavelength [nm]
Dark signal output temperature characteristics
(Standard characteristics)
Integration time output voltage characteristics
(Standard characteristics)
10
Output voltage rate
Output voltage rate
5
1
0.5
0.1
1
0.5
0.1
0
10
20
30
40
50
60
1
5
10
Ta – Ambient temperature [°C]
τint – Integration time [ms]
Offset level vs. VDD characteristics
(Standard characteristics)
Offset level vs. temperature characteristics
(Standard characteristics)
12
12
Ta = 25°C
10
VOS – Offset level [V]
VOS – Offset level [V]
10
8
6
∆VOS
∆VDD
4
0.3
2
0
11.4
8
6
∆VOS
∆Ta
4
–0.5mV/°C
2
0
12
12.6
0
VDD [V]
10
20
30
40
50
Ta – Ambient temperature [°C]
–8–
60
ILX520K
Notes of Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W
soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an imaging device, do not use a solder suction equipment. When using an electric
desoldering tool, ground the controller. For the control system, use a zero cross type.
3) Dust and dirt protection
a) Operate in clean environments.
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch
the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
4) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.
–9–
5.0 ± 0.5
– 10 –
H
24
PACKAGE WEIGHT
5.8g
42ALLOY
GOLD PLATING
LEAD TREATMENT
LEAD MATERIAL
Ceramic
2.54
PACKAGE MATERIAL
1
68.0
12
13
56.624 (8µm × 7078Pixels)
71.0 ± 0.9
No.1 Pixel (Green)
1st. pin Index
V
8.5 ± 0.8
PACKAGE STRUCTURE
4.0 ± 0.5
0.46
M
0° to 9°
0.25
(AT STAND OFF)
10.16
10.0 ± 0.5
2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.
1. The height from the bottom to the sensor surface is 1.4 ± 0.3mm.
0.3
9.0
2.29
0.97
Package Outline
3.1 ± 0.5
24Pin DIP (400mil)
ILX520K
Unit: mm
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