Infineon IPD050N03LG Optimosâ®3 power-transistor Datasheet

Type
OptiMOS®3 Power-Transistor
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
Product Summary
Features
• Fast switching MOSFET for SMPS
• Optimized technology for DC/DC converters
VDS
30
V
RDS(on),max
5
mW
ID
50
A
1)
• Qualified according to JEDEC for target applications
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Very low on-resistance R DS(on)
• Avalanche rated
• Pb-free plating; RoHS compliant
Type
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
Package
PG-TO252-3-11
PG-TO252-3-23
PG-TO251-3-11
PG-TO251-3-21
Marking
050N03L
050N03L
050N03L
050N03L
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
ID
Value
V GS=10 V, T C=25 °C
50
V GS=10 V, T C=100 °C
50
V GS=4.5 V, T C=25 °C
50
V GS=4.5 V,
T C=100 °C
50
Unit
A
Pulsed drain current2)
I D,pulse
T C=25 °C
350
Avalanche current, single pulse3)
I AS
T C=25 °C
50
Avalanche energy, single pulse
E AS
I D=35 A, R GS=25 W
60
mJ
Reverse diode dv /dt
dv /dt
I D=50 A, V DS=24 V,
di /dt =200 A/µs,
T j,max=175 °C
6
kV/µs
Gate source voltage
V GS
1)
±20
V
J-STD20 and JESD22
Rev. 2.0
page 1
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Power dissipation
P tot
Operating and storage temperature
T j, T stg
Value
T C=25 °C
IEC climatic category; DIN IEC 68-1
Parameter
Unit
68
W
-55 ... 175
°C
55/175/56
Values
Symbol Conditions
Unit
min.
typ.
max.
-
-
2.2
minimal footprint
-
-
75
6 cm² cooling area4)
-
-
50
Thermal characteristics
Thermal resistance, junction - case
R thJC
SMD version, device on PCB
R thJA
K/W
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0 V, I D=1 mA
30
-
-
Gate threshold voltage
V GS(th)
V DS=V GS, I D=250 µA
1
-
2.2
Zero gate voltage drain current
I DSS
V DS=30 V, V GS=0 V,
T j=25 °C
-
0.1
1
V DS=30 V, V GS=0 V,
T j=125 °C
-
10
100
V
µA
Gate-source leakage current
I GSS
V GS=20 V, V DS=0 V
-
10
100
nA
Drain-source on-state resistance5)
R DS(on)
V GS=4.5 V, I D=30 A
-
5.8
7.3
mW
V GS=10 V, I D=30 A
-
4.2
5
-
1.5
-
W
38
77
-
S
Gate resistance
RG
Transconductance
g fs
2)
See figure 3 for more detailed information
3)
See figure 13 for more detailed information
|V DS|>2|I D|R DS(on)max,
I D=30 A
4)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
5)
Measured from drain tab to source pin
Rev. 2.0
page 2
2013-10-28
Parameter
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
Values
Symbol Conditions
Unit
min.
typ.
max.
-
2400
3200
-
920
1200
Dynamic characteristics
Input capacitance
C iss
V GS=0 V, V DS=15 V,
f =1 MHz
Output capacitance
C oss
Reverse transfer capacitance
Crss
-
49
-
Turn-on delay time
t d(on)
-
6.7
-
Rise time
tr
-
13
-
Turn-off delay time
t d(off)
-
25
-
Fall time
tf
-
3.8
-
Gate to source charge
Q gs
-
7.4
-
Gate charge at threshold
Q g(th)
-
3.8
-
Gate to drain charge
Q gd
-
3.5
-
Switching charge
Q sw
-
7.1
-
Gate charge total
Qg
-
15
20
Gate plateau voltage
V plateau
-
3.1
-
Gate charge total
Qg
V DD=15 V, I D=30 A,
V GS=0 to 10 V
-
31
-
Gate charge total, sync. FET
Q g(sync)
V DS=0.1 V,
V GS=0 to 4.5 V
-
13
17
Output charge
Q oss
V DD=15 V, V GS=0 V
-
24
-
-
-
50
-
-
350
V DD=15 V, V GS=10 V,
I D=30 A, R G,ext=1.6 W
pF
ns
Gate Charge Characteristics6)
V DD=15 V, I D=30 A,
V GS=0 to 4.5 V
nC
V
nC
Reverse Diode
Diode continuous forward current
IS
A
T C=25 °C
Diode pulse current
I S,pulse
Diode forward voltage
V SD
V GS=0 V, I F=30 A,
T j=25 °C
-
0.86
1.1
V
Reverse recovery charge
Q rr
V R=15 V, I F=I S,
di F/dt =400 A/µs
-
-
15
nC
6)
See figure 16 for gate charge parameter definition
Rev. 2.0
page 3
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
70
60
60
50
50
40
ID [A]
Ptot [W]
40
30
30
20
20
10
10
0
0
0
50
100
150
200
0
50
100
TC [°C]
150
200
TC [°C]
3 Safe operating area
4 Max. transient thermal impedance
I D=f(V DS); T C=25 °C; D =0
Z thJC=f(t p)
parameter: t p
parameter: D =t p/T
103
10
1 µs
limited by on-state
resistance
10 µs
102
100 µs
0.5
1
ZthJC [K/W]
ID [A]
DC
101
1 ms
0.2
0.1
0.05
10 ms
0.1
0.02
100
0.01
single pulse
10-1
0.01
10-1
100
101
102
VDS [V]
Rev. 2.0
0
0
0
0
0
0
1
10-6
10-5
10-4
10-3
10-2
10-1
100
tp [s]
page 4
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
5 Typ. output characteristics
6 Typ. drain-source on resistance
I D=f(V DS); T j=25 °C
R DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
150
15
3.2 V
10 V
120
12
5V
4.5 V
3.5 V
ID [A]
90
RDS(on) [mW]
4V
3.5 V
60
9
4V
4.5 V
6
5V
10 V
11.5 V
3.2 V
30
3
3V
2.8 V
0
0
0
1
2
3
0
20
40
VDS [V]
60
80
100
80
100
ID [A]
7 Typ. transfer characteristics
8 Typ. forward transconductance
I D=f(V GS); |V DS|>2|I D|R DS(on)max
g fs=f(I D); T j=25 °C
parameter: T j
150
120
120
90
90
ID [A]
gfs [S]
150
60
60
30
30
175 °C
25 °C
0
0
0
1
2
3
4
5
VGS [V]
Rev. 2.0
0
20
40
60
ID [A]
page 5
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
10 Typ. gate threshold voltage
R DS(on)=f(T j); I D=30 A; V GS=10 V
V GS(th)=f(T j); V GS=V DS; I D=250 µA
10
2.5
8
2
6
1.5
VGS(th) [V]
RDS(on) [mW]
9 Drain-source on-state resistance
98 %
typ
4
2
1
0.5
0
0
-60
-20
20
60
100
140
180
-60
-20
20
60
Tj [°C]
100
140
180
Tj [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
C =f(V DS); V GS=0 V; f =1 MHz
I F=f(V SD)
parameter: T j
104
103
Ciss
25 °C, 98%
103
102
25 °C
Coss
IF [A]
C [pF]
175 °C
102
175 °C, 98%
z
101
Crss
101
100
0
10
20
30
VDS [V]
Rev. 2.0
0
0.5
1
1.5
2
VSD [V]
page 6
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
13 Avalanche characteristics
14 Typ. gate charge
I AS=f(t AV); R GS=25 W
V GS=f(Q gate); I D=30 A pulsed
parameter: T j(start)
parameter: V DD
100
12
15 V
6V
24 V
10
25 °C
150 °C
8
VGS [V]
IAV [A]
100 °C
10
6
4
2
1
10-1
0
100
101
102
0
103
5
tAV [µs]
10
15
20
25
30
35
40
Qgate [nC]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V BR(DSS)=f(T j); I D=1 mA
34
V GS
Qg
32
VBR(DSS) [V]
30
28
26
V gs(th)
24
Q g(th)
22
Q sw
Q gs
20
-60
-20
20
60
100
140
Q gate
Q gd
180
Tj [°C]
Rev. 2.0
page 7
2013-10-28
Package Outline
Rev. 2.0
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
PG-TO252-3-11
page 8
2013-10-28
Package Outline
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
PG-TO252-3-23
PG-TO251-3-11: Outline
PG-TO251-3-21: Outline
Rev. 2.0
page 9
2013-10-28
Package Outline
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
PG-TO251-3-11
PG-TO251-3-11: Outline
PG-TO251-3-21: Outline
Rev. 2.0
page 10
2013-10-28
Package Outline
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
PG-TO251-3-21
PG-TO251-3-11: Outline
PG-TO251-3-21: Outline
Rev. 2.0
page 11
2013-10-28
IPD050N03L G
IPF050N03L G
IPS050N03L G
IPU050N03L G
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of
conditions or characteristics. With respect to any examples or hints given herein, any typical
values stated herein and/or any information regarding the application of the device,
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,
including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please
contact the nearest Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information
on the types in question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with
the express written approval of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life-support device or system or to affect
the safety or effectiveness of that device or system. Life support devices or systems are
intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
Rev. 2.0
page 12
2013-10-28
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