AVAGO AJAV-5505-TR1 W-cdma/hspa band v power amplifier Datasheet

AJAV-5505
W-CDMA/HSPA Band V Power Amplifier
Data Sheet
Description
Features
The AJAV-5505 is a complete, high-performance power
amplifier for W-CDMA and HSPA wireless communications. Based on a unique, patented architecture, the AJAV5505 integrates circuitry for TX filtering, RF coupling,
power regulation, input and output matching and power
control. The PA is powered by a single connection to the
battery and is implemented in a standard CMOS process.
• High-performance 3G power amplifier
Pin Assignments
• Integrated regulators and PA bias
- UMTS Band V (824 - 849 MHz)
- W-CDMA, HSPA, and HSPA+ Compliant
• Integrated TX filtering
- Delivers best noise in the industry
• Integrated directional coupler
• Single direct connection to the battery
Top View (x-ray)
VBAT
- No external switches or isolation inductors
VBAT
RFI
• High linear efficiency
RFO
• Low average current
CPLI
• High capacity CMOS process
VM0
GND
• Small 3×3 mm package
VEN
CPLO
Applications
GND
PAD
VM1
• Smartphones, data cards and 3G modules
US Patent # 7,728,661; 7,768,350;
7,872,528; 8,022,766
Other patents pending
• Tablets, netbooks and network PCs
• E-books and wireless electronic readers
Functional Block Diagram
Top View
VBAT
AJAV-5505
REGULATOR/BIAS
RFI
INPUT
MATCH
OUTPUT
MATCH
RFO
CPLI
CPLO
PA
CONTROL
VM0 VM1 VEN
Electrical Characteristics
Table 1. Absolute Minimum and Maximum Ratings [1]
Parameter
Symbol
Supply Voltage [2]
VBATT
Control Voltage [3]
VCTRL
Condition
VCTRL < VBATT
RF Input Power [4]
Electrostatic Discharge (ESD) [5]
Storage Temperature
Human Body Model (HBM)
TSTG
Min.
Typ.
Max.
Unit
-0.3
-
4.5
V
-0.3
-
4.5
V
-
-
+10
dBm
-
-
3.0
kV
-55
-
125
°C
Notes:
1. Permanent device damage may occur if the ratings above are exceeded. Functional operation is not guaranteed under these conditions and
should be restricted to the recommended operating conditions in Table 2. Exposure to absolute ratings for extended periods may affect device
reliability.
2. Supply voltage is applied to VBAT pin.
3. Control voltages are applied to VEN, VM0, VM1 pins.
4. RF input is applied to RFI, CPLI pins.
5. For all pins.
Table 2. Operating Conditions [1]
Parameter
Symbol
Supply Voltage [2]
VBATT
Control Voltage – High [3]
VIH
Control Voltage – Low [3]
Ambient Temperature
Condition
Min.
Typ.
Max.
Unit
2.5
3.8
4.2
V
1.3
1.8
VBATT
V
VIL
0.0
-
0.5
V
TA
-30
25
90
°C
VIH < VBATT
Notes:
1. To ensure proper operation, the VEN pin should be asserted from VIL to VIH at least 2 ms after power is applied to the VBAT pins.
2. Device to remain functional down to VBATT = 2.5 V. At VBATT < 3.4 V, output power is derated by 0.5 dB.
3. Logic states for VEN, VM0, VM1 pins.
Table 3. Mode Control Logic [1]
Mode
Output Power Range [2]
VEN
VM0
VM1
High Power Mode (HP)
16.5 dBm < POUT ≤ PMAX
High
Low
Low
Mid Power Mode (MP)
9.0 dBm < POUT ≤ 16.5 dBm
High
High
Low
Low Power Mode (LP)
POUT ≤ 9.0 dBm
High
High
High
Low
X
X
Powerdown
Notes:
1. The VM0 and VM1 pins are controlled externally to achieve maximum PA efficiency. High and low logic states are specified in Table 2.
2. Maximum linear output power, PMAX, is defined in Table 4.
Table 4. Electrical Specifications [1]
Parameter
Symbol
Frequency
FRF
Maximum Linear Output Power [2]
PMAX
Gain [2]
G
RX Band Gain [2,3]
2
GRX
Condition
Min.
Typ.
Max.
Unit
824
-
849
MHz
HP mode
MP mode
LP mode
HP mode
MP mode
+26.0
+16.0
+8.5
26.5
16.0
+26.5
+16.5
+9.0
28.5
18.0
-
dBm
dBm
dBm
dB
dB
LP mode
RX Band, 45 MHz offset
GPS Band, 1524 – 1577 MHz
ISM Band, 2400 – 2484 MHz
8.0
-
10.0
-4.5
-57
-62
-
dB
dBc
dBc
dBc
Table 4. Electrical Specifications [1] (continued)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Adjacent Channel Leakage Ratio [2,4]
ACLR1
± 5 MHz offset
-
-42
-38
dBc
ACLR2 [5]
± 10 MHz offset
-
-53
-48
dBc
Noise [14]
N
Error Vector Magnitude [2,4,5]
EVM
RX Band, 45 MHz offset
GPS Band, 1524 – 1577 MHz
ISM Band, 2400 – 2484 MHz
POUT ≤ PMAX
-
-140
-164
-164
1.5
3.35
dBm/Hz
dBm/Hz
dBm/Hz
%
Power Added Efficiency [2,5,6]
PAE
Quiescent Idle Current
ICQ
HP mode
MP mode
LP mode
-
40
27
3.5
-
%
%
mA
Average Current [2,5,7]
IAVG
Total current from all pins
-
19
-
mA
Powerdown Current [4,8]
IPD
VEN = VIL
-
5
10
mA
Logic Current [4,9]
ICTRL
-
5
10
mA
Input Impedance [5]
ZIN
-
1.4:1
2.5:1
VSWR
2F0
± 5 MHz offset
± 10 MHz offset
Second harmonic
-
-
-31
-41
-35
dBc
dBc
dBc
3F0, 4F0
Third and fourth harmonic
-
-
-35
dBc
LP mode ↔ MP mode
MP mode ↔ HP mode
-
90
50
-20
-
degree (°)
degree (°)
dB
Reverse Intermodulation [4,5,10]
Harmonics [2,4,5]
Instantaneous Phase Change [4,5,15]
Coupling Factor [11]
s31
Daisy Chain Insertion Loss [5]
s34
UMTS Band V
UMTS Band I, II
-
-0.7
-1.1
-
dB
dB
Daisy Chain Return Loss [5,11]
s33, s44
UMTS Band V
UMTS Band I, II
Load VSWR = 2.5:1
-1
-27
-20
-
+1
dB
dB
dB
-
12
15
ms
-
Output Power Error [5,12]
Turn-on Time [13]
TON
Turn-off Time [5,13]
TOFF
8
10
ms
Other Spurious [4,5]
Load VSWR ≤ 5:1
-
-
-70
dBc
Ruggedness [5]
No permanent damage or degradation -
-
10:1
VSWR
Notes:
1. Specifications at nominal operating conditions VIH = 1.8 V, VEN = 1.8 V, VBAT = 3.8 V, TA = 25 °C, RF ports at 50 Ω, guaranteed over the full range of
operating frequency and guaranteed by production test unless indicated otherwise.
2. Specification is guaranteed using W-CDMA modulation RMC (12.2 kbps) in compliance with 3GPP Release 99.
3. RX band gain is specified relative to PA gain at 836.5 MHz.
4. Specification is guaranteed over all power modes given in Table 3.
5. Specification is guaranteed by characterization.
6. Power-Added Efficiency (PAE) includes total current consumption through all pins while PA is operating at maximum linear output power.
7. Calculated using three power modes (HP, MP, LP) with handset W-CDMA transmitter power distribution in GSMA DG.09 specification assuming 3
dB of post-PA loss.
8. Total supply current measured when the PA is disabled.
9. Specification applies to each VEN, VM0, and VM1 pin.
10. Interferer is CW at a relative power level of -40 dBc and offset from the W-CDMA modulated carrier.
11. Measured at CPLO pin.
12. Power variation measured at the RFO pin across 8 phase angles while power at CPLO pin is held constant.
13. Specified from the start of the PA enable transition to when the output power is within ±1 dB of final value.
14. Specification is guaranteed by characterization at PMAX.
15. Phase change should be measured at the center channel at each switch point and compensated in the baseband.
3
Application Information
VBAT
4.7 µF
0603
Low current <10 µA
Pin 1 can be directly
connected to VBAT
VBAT
RF IN
VM1
VM0
VEN
1
2
3
4
5
VBAT
VBAT
RFI
VM1
RFO
AJAV-5505
CPLI
VM0
GND
VEN
CPLO
10
9
8
10 pF
0402
RF OUT
CPLI
7
6
CPLO
GND Paddle
Figure 1. Typical Single-Band Application Circuit
The AJAV-5505 is the world’s first 3G Band V power amplifier (PA) implemented in a standard CMOS process. The
AJAV-5505 delivers low current and integrates TX filtering
that produces the best noise in the industry. Only a single
RF bypass capacitor is required, enabling a very low billof-materials (BOM). The AJAV-5505 is fully compliant with
W-CDMA, HSPA, and HSPA+ standards through 3GPP Release 7 and supports Power Class 3 and 4.
Figure 1 shows the typical application circuit. The AJAV5505 supports three power modes controlled by a standard CMOS interface enabling a direct connection to the
baseband with no level shifters. The VEN, VM0 and VM1
power control pins are high impedance with logic levels
defined in Table 2.
The AJAV-5505 may be powered by a single direct connection to the battery, or controlled with an external DC/
DC converter. All power supply current flows through pin
10. Pin 1 is a low current input that can be directly connected to VBAT or any other high level signal. No external
switches, isolation inductors, or bypass capacitors are required on Pin 1.
4
Standard RF practice should be followed for the PCB layout
of the RF traces for pins 2, 6, 8, and 9. Multiple vias should
be placed underneath the GND paddle to create a low resistance path to ground and to ensure good heat conduction. Refer to Application Note 5565, (AV02-4080EN) AJAV5xxx PCB Guidelines, for additional information.
The AJAV-5505 features an integrated directional coupler
that can be daisy-chained through the CPLI and CPLO
ports. For best performance, at least one port should see
a 50 Ω path to GND. The CPLI port accepts an RF input or
can be terminated. The CPLO port provides the coupled
RF output that can be passed to the RF detector, terminated, or passed to the next PA in the daisy chain.
The AJAV-5505 includes integrated TX filtering that ensures excellent receiver sensitivity. As the RF signal passes
through the PA, the unwanted out-of-band noise produced by the transceiver is filtered out. Furthermore, the
thermal noise at the PA output is greatly reduced below
the level of a conventional GaAs PA. The resulting signal
at the output of the AJAV-5505 is spectrally very clean, ensuring the best receiver sensitivity and producing minimal
interference to other radios in the system.
Top View (x-ray)
1
10
2
9
epad
3
8
4
7
5
6
Figure 2. Pin Descriptions
TOP BRAND
J5505
YWWXX
RFAT
Laser dot
Pin 1 indicator:
Manufacturing part number: J5505
YWWXX
Trace code:
Y - Year
WW - Work week
XX - Lot number
Manufacturing information: RFAT
Figure 3. Package Marking
5
Pin #
Name
Description
1
2
3
4
5
6
7
8
9
10
epad
VBAT
RFI
VM1
VM0
VEN
CPLO
GND
CPLI
RFO
VBAT
GND
DC Supply Voltage
RF Input
Mode Control
Mode Control
PA Enable
Coupler Output
Ground
Coupler Input
RF Output
DC Supply Voltage
Ground
DFN Package Information
Symbol
Min.
Nom.
Max.
Total Thickness
A
0.8
0.85
0.9
Stand Off
A1
0
0.035
0.05
Mold Thickness
L/F Thickness
A2
A3
-
0.7
0.152 REF
-
Lead Width
Lead Width
b
b1
0.35
0.25
0.4
0.3
X
D
3 BSC
Y
E
e
3 BSC
0.6 BSC
X
Y
J
K
1.4
2.5
Lead Length
L
0.25
Lead Edge
N
0.15
Package Edge Tolerance
aaa
0.1
Mold Flatness
bbb
0.1
Coplanatary
Lead Offset
ccc
ddd
0.08
0.1
Exposed Pad Offset
eee
0.1
Body Size
Lead Pitch
EP Size
0.45
0.35
1.5
2.6
1.6
2.7
0.3
0.35
(dimensions in mm)
Figure 4. DFN Package Information
Ordering Guide
Part Number
AJAV-5505-BLK
AJAV-5505-TR1
Description
W-CDMA/HSPA Band V Power Amplifier
Package Type Operating Temperature
3×3 DFN
-30 to 90 °C
Note: Shipping method is tape and reel, quantity 5000 pieces per reel.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-4065EN - May 16, 2013
Quantity
Container
100
Antistatic bag
5000
Tape & Reel
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