Hanbit HMD2M32M4E 8mbyte(2mx32) edo mode, 1k refresh 72pin simm, 5v design Datasheet

HANBit
HMD2M32M4E/4EG
8Mbyte(2Mx32) EDO Mode, 1K Refresh 72Pin SIMM, 5V Design
Part No. HMD2M32M4E, HMD2M32M4EG
GENERAL DESCRIPTION
The HMD2M32M4E is a 2M x 32bit dynamic RAM high-density memory module. The module consists of four CMOS 1M
x 16bit DRAMs in 42-pin SOJ packages mounted on a 72 -pin, double-sided, FR-4-printed circuit board.
A 0.1 or 0.22uF
decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In -line
Memory Module with edge connections and is intended for mounting in to 72 -pin edge connector sockets. All module
components may be powered from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
PIN
ASSIGNMENT
w Part Identification
PIN
SYMBOL
PIN
SYMBOL
1
Vss
25
DQ22
49
DQ8
w Access times : 50, 60ns
2
DQ0
26
DQ7
50
DQ24
w High-density 8MByte design
3
DQ16
27
DQ23
51
DQ9
w Single + 5V ±0.5V power supply
4
DQ1
28
A7
52
DQ25
w JEDEC standard pinout
5
DQ17
29
A11
53
DQ10
w EDO mode operation
6
DQ2
30
Vcc
54
DQ26
w TTL compatible inputs and outputs
7
DQ18
31
A8
55
DQ11
8
DQ3
32
A9
56
DQ27
9
DQ19
33
/RAS3
57
DQ12
10
Vcc
34
/RAS2
58
DQ28
11
NC
35
NC
59
Vcc
12
A0
36
NC
60
DQ29
13
A1
37
NC
61
DQ13
14
A2
38
NC
62
DQ30
15
A3
39
Vss
63
DQ14
16
A4
40
/CAS0
64
DQ31
17
A5
41
/CAS2
65
DQ15
18
A6
42
/CAS3
66
NC
HMD2M32M4E---- 1024 Cycles/16ms Ref . Solder
HMD2M32M4EG- -1024 Cycles/16ms Ref . Gold
w FR4-PCB design
OPTIONS
MARKING
w Timing
50ns access
-50
60ns access
-60
70ns access
-70
w Packages
72-pin SIMM
M
PERFORMANCE RANGE
PIN
SYMBOL
Speed
tRAC
tCAC
tRC
19
A10
43
/CAS1
67
PD1
5
50ns
15ns
90ns
20
DQ4
44
/RAS0
68
PD2
6
60ns
15ns
110ns
21
DQ20
45
/RAS1
69
PD3
7
70ns
15ns
130ns
22
DQ5
46
NC
70
PD4
23
DQ21
47
/WE
71
NC
24
DQ6
48
NC
72
Vss
PRESENCE DETECT PINS
Pin
50ns
60ns
70ns
PD1
NC
NC
NC
PD2
NC
NC
NC
PD3
Vss
NC
Vss
PD4
Vss
NC
NC
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HMD2M32M4E/4EG
Functional Block Diagram
DQ0
U2 DQ1
/RAS0
/CAS0
/CAS1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/RAS
/LCAS
/UCAS
/OE
/W
A0-A11
U1
/RAS2
/CAS2
/CAS3
/RAS
/LCAS
/UCAS
/OE
/W
DQ0-15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U4
/CAS0
LCAS
/CAS1
/UCAS
/OE
/W
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ16-31
DQ11
DQ12
DQ13
DQ14
DQ15
A0-A11
/RAS1
/RAS
/W
A0-A11
U3
/RAS
/RAS3
/CAS2
/LCAS
/CAS3
/UCAS
/OE
A0-A11
/WE
A0-A11
Vcc
0.1uFor
0.22uF
Capacitor
for each DRAM
Vss
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To all DRAMs
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HANBit
HMD2M32M4E/4EG
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
VIN ,OUT
-1V to 7.0V
Voltage on Vcc Supply Relative to Vss
Vcc
-1V to 7.0V
Power Dissipation
PD
4W
TSTG
-55oC to 150oC
Voltage on Any Pin Relative to Vss
Storage Temperature
Short Circuit Output Current
IOS
50mA
w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be
restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage reference to V SS, TA=0 to 70 o C )
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Supply Voltage
Vcc
4.5
5.0
5.5
V
Ground
Vss
0
0
0
V
Input High Voltage
VIH
2.4
-
Vcc+1
V
Input Low Voltage
VIL
-1.0
-
0.8
V
DC AND OPERATING CHARACTERISTICS
SYMBOL
SPEED
MIN
MAX
UNITS
-5
-
305
mA
-6
-
284
mA
-
8
mA
-5
-
304
mA
-6
-
284
mA
-5
-
244
mA
-6
-
224
mA
-
4
mA
-5
-
304
mA
-6
-
284
mA
Il(L)
-20
20
mA
IO(L)
-10
10
mA
VOH
2.4
-
V
VOL
-
0.4
V
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
ICC1 : Operating Current * (/RAS , /CAS , Address cycling
@t RC=min.)
ICC2 : Standby Current ( /RAS=/CAS=V IH )
ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @t RC=min )
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HMD2M32M4E/4EG
ICC4 : Fast Page Mode Current * (/RAS=V IL, /CAS, Address cycling @t PC=min )
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min )
IIL : Input Leakage Current (Any input 0V £ VIN £ 6.5V, all other pins not under test = 0V)
IOL : Output Leakage Current (Data out is disabled, 0V £ VOUT £ 5.5V
VOH : Output High Voltage Level (I OH= -5mA )
VOL : Output Low Voltage Level (I OL = 4.2mA )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained wi th the
output open. I CC is specified as an average current. In I CC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
o
( TA=25 C, Vcc = 5V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A10)
CIN1
-
44
pF
Input Capacitance (/W)
C IN2
-
48
pF
Input Capacitance (/RAS0)
CIN3
-
40
pF
Input Capacitance (/CAS0-/CAS3)
CIN4
-
29
pF
Input/Output Capacitance (DQ0-31)
CDQ1
-
29
pF
AC CHARACTERISTICS
o
( 0 C £ TA £ 70oC , Vcc = 5V±10%, See notes 1,2.)
STANDARD OPERATION
SYMBOL
-5
MIN
-6
MAX
MAX
tRC
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
15
17
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
3
Output buffer turn-off delay
tOFF
3
13
3
15
ns
Transition time (rise and fall)
tT
2
50
2
50
ns
/RAS precharge time
tRP
30
/RAS pulse width
tRAS
50
/RAS hold time
tRSH
13
17
ns
/CAS hold time
tCSH
40
50
ns
/CAS pulse width
tCAS
8
10K
10
10K
ns
/RAS to /CAS delay time
tRCD
20
37
20
45
ns
/RAS to column address delay time
tRAD
15
25
15
30
ns
/CAS to /RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
9
110
UNIT
Random read or write cycle time
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REV.1.0 (August.2002)
90
MIN
ns
3
ns
40
10K
60
ns
10K
ns
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HANBit
HMD2M32M4E/4EG
Column address set-up time
tASC
0
0
ns
Column address hold time
tCAH
8
10
ns
Column Address to /RAS lead time
tRAL
25
30
ns
Read command set-up time
tRCS
0
0
ns
Read command hold referenced to /CAS
tRCH
0
0
ns
Read command hold referenced to /RAS
tRRH
0
0
ns
Write command hold time
tWCH
10
10
ns
Write command pulse width
tWP
10
10
ns
Write command to /RAS lead time
tRWL
13
15
ns
Write command to /CAS lead time
tCWL
13
15
ns
Data-in set-up time
tDS
0
0
ns
Data-in hold time
tDH
8
10
ns
Refresh period
(1K Ref. Normal)
tREF
16
16
ms
Write command set-up time
tWCS
0
0
ns
/CAS setup time (C-B-R refresh)
tCSR
5
5
ns
/CAS hold time (C-B-R refresh)
tCHR
10
10
ns
/RAS precharge to /CAS hold time
tRPC
5
5
ns
Access time from /CAS precharge
tCPA
/CAS precharge time (Fast page)
tCP
8
/RAS pulse width (Fast page )
tRASP
50
/W to /RAS precharge time (C-B-R refresh)
tWRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
tWRH
10
10
ns
30
35
10
200K
60
ns
ns
200K
ns
NOTES
1.An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 2TTL loads and 100pF
4.Operation within the t RCD(max) limit insures that t RAC(max) can be met. t RCD(max) is specified as a reference point only. If t RCD
is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that t RCD ³ tRCD(max)
6. tAR, tWCR, tDHR are referenced to tRAD(max)
7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH
or VOL.
8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter.
They are included in the data sheet as e lectrical characteristic only. If t WCS ³ tWCS(min) the cycle is an early write
cycle and the data out pin will remain high impedance for the duration of the cycle.
9. Either tRCH or tRRH must be satisfied for a read cycle.
10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read write cycles.
11. Operation within the t RAD(max) limit insures that t RAC(max) can be met. t RAD(max) is specified as a reference
point only. If t RAD is greater than the specified t RAD(max) limit. then access time is controlled by t AA.
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HMD2M32M4E/4EG
TIMING DIAGRAMS TIMING
WAVEFORM OF READ CYCLE
/RAS
tRC
tRAS
VIHVILtCRP
/CAS
tCSH
tRCD
tCRP
tRSH
VIH-
tCAS
tRAD
VIL-
tASR
A VIHVIL/W
tRP
tRAH
tCAH
tASC
ROW ADDRESS
tRAL
COLUMN ADDRESS
tRCS
VIH-
tRRH
VIL-
tOFF
tOEZ
tAA
/OE VIH-
tRCH
tOEA
VIL-
tCAC
tCLZ
tRAC
DQ V
OHVOL-
DATA-OUT
OPEN
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE)
tRC
/RAS
VIHVILtCRP
/CAS VIHVILA VIHVIL-
VIH-
tRP
tRAS
tCSH
tRCD
tCRP
tRSH
tCAS
tRAD
tASR
tRAH
ROW ADDRESS
tCAH
tASC
tRAL
COLUMN ADDRESS
tCWL
tRWL
tWCS
tWCH
tWP
/W VILVIH/OE
VILtDS
DQ0
VOHVOL-
tDH
DATA-IN
NOTE : Dout = Open
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HMD2M32M4E/4EG
PACKAGING INFORMATION
72pin -SIMM Design
(Front view)
107.95 mm
3.38 mm
R 1.57 mm
101.19 mm
3.18 mm DIA
0.51 mm
19.05mm
10.16 mm
6.35 mm
1
2.03 mm
6.35 mm
1.02 mm
6.35 mm
1.27 mm
3.17 mm
95.25 mm
2.54 mm
0.25 mm MAX
MIN
1.29±0.08 mm
Gold : 1.04±0.10 mm
1.27mm
Solder:0.914±0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Vcc
SPEED
HMD2M32M4EG-5
8MByte
2MX 32bit
72 Pin-SIMM
5.0V
50ns
HMD2M32M4EG-6
8MByte
2MX 32bit
72 Pin-SIMM
5.0V
60ns
HMD2M32M4EG-7
8MByte
2MX 32bit
72 Pin-SIMM
5.0V
70ns
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