Cypress CY2305CSXI-1H 3.3v zero delay clock buffer Datasheet

CY2305C
CY2309C
3.3V Zero Delay Clock Buffer
Features
skew clocks. The -1H versions of each device operate up to
100-133 MHz frequencies and have higher drive than the -1
devices. All parts have on-chip PLLs which lock to an input clock
on the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
■
10 MHz to 100-133 MHz operating range
■
Zero input and output propagation delay
■
Multiple low skew outputs
■
One input drives five outputs (CY2305C)
■
One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309C)
■
50 ps typical cycle-cycle jitter (15 pF, 66 MHz)
■
Test Mode to bypass phase locked loop (PLL) (CY2309C) only,
see “Select Input Decoding for CY2309C” on page 3
■
Available in space saving 16-pin 150 Mil SOIC or 4.4 mm
TSSOP packages (CY2309C), and 8-pin, 150 Mil SOIC
package (CY2305C)
■
3.3V operation
■
Commercial, Industrial and Automotive-A flows available
Functional Description
The CY2305C and CY2309C are die replacement parts for
CY2305 and CY2309.
The CY2309C is a low cost 3.3V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC or
TSSOP package. The CY2305C is an 8-pin version of the
CY2309C. It accepts one reference input and drives out five low
The CY2309C has two banks of four outputs each that are
controlled by the select inputs as shown in the “Select Input
Decoding for CY2309C” on page 3. If all output clocks are not
required, BankB is three-stated. The input clock is directly
applied to the outputs by the select inputs for chip and system
testing purposes.
The CY2305C and CY2309C PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off. This
results in less than 12.0 μA of current draw for commercial
temperature devices and 25.0 μA for industrial and automotive-A
temperature parts. The CY2309C PLL shuts down in one
additional case as shown in the “Select Input Decoding for
CY2309C” on page 3.
In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum allowable frequency. The
part behaves as a non-zero delay buffer in this mode and the
outputs are not three-stated.
The CY2305C or CY2309C is available in two or three different
configurations as shown in the “Ordering Information” on page 9.
The CY2305C-1 or CY2309C-1 is the base part. The CY2305-1H
or CY2309-1H is the high drive version of the -1. Its rise and fall
times are much faster than the -1.
Logic Block Diagram for CY2305C
PLL
REF
CLKOUT
CLK1
CLK2
CLK3
CLK4
Cypress Semiconductor Corporation
Document Number: 38-07672 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 27, 2008
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CY2305C
CY2309C
Logic Block Diagram for CY2309C
PLL
CLKOUT
MUX
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
CLKB2
CLKB3
S1
CLKB4
Pinouts
CY2305C
Figure 1. Pin Diagram - 8 Pin SOIC
Top View
REF
CLK2
CLK1
GND
1
2
CY2305C
8
7
3
6
4
5
CLKOUT
CLK4
VDD
CLK3
Table 1. Pin Description - 8 Pin SOIC
Pin
Signal
Description
1
REF[1]
Input reference frequency
2
CLK2[2]
Buffered clock output
3
CLK1[2]
Buffered clock output
4
GND
Ground
5
CLK3[2]
Buffered clock output
6
VDD
3.3V supply
7
CLK4[2]
Buffered clock output
8
CLKOUT[2]
Buffered clock output, internal feedback on this pin
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
Document Number: 38-07672 Rev. *H
Page 2 of 12
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CY2305C
CY2309C
CY2309C
Figure 2. Pin Diagram - 16 Pin SOIC/TSSOP
Top View
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
CY2309C
14
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Table 2. Pin Definition - 16 Pin SOIC/TSSOP
Pin
Signal
Description
1
REF[1]
Input reference frequency
2
CLKA1[2]
Buffered clock output, Bank A
3
CLKA2[2]
Buffered clock output, Bank A
4
VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Buffered clock output, Bank B
7
CLKB2[2]
Buffered clock output, Bank B
8
S2[3]
Select input, bit 2
9
S1[3]
Select input, bit 1
10
CLKB3[2]
Buffered clock output, Bank B
11
CLKB4[2]
Buffered clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Buffered clock output, Bank A
15
CLKA4[2]
Buffered clock output, Bank A
16
CLKOUT[2]
Buffered output, internal feedback on this pin
Table 3. Select Input Decoding for CY2309C
S2
CLOCK B1–B4
CLKOUT[4]
Output Source
PLL Shutdown
Three state
Three state
Driven
PLL
N
Driven
Three state
Driven
PLL
N
S1
CLOCK A1–A4
0
0
0
1
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal
feedback to the PLL, its relative loading can adjust the input or output delay.
For applications requiring zero input or output delay, all outputs including CLKOUT are equally loaded. Even if CLKOUT is not used,
it must have a capacitive load equal to that on other outputs for obtaining zero input or output delay.
For zero output or output skew, all outputs are loaded equally. For further information refer to the application note entitled “CY2305
and CY2309 as PCI and SDRAM Buffers”.
Notes
3. Weak pull ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output is adjusted to change the skew between the reference and output.
Document Number: 38-07672 Rev. *H
Page 3 of 12
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CY2305C
CY2309C
Absolute Maximum Conditions
Storage Temperature ................................. –65°C to +150°C
Supply Voltage to Ground Potential................–0.5V to +4.6V
DC Input Voltage (Except REF) ............ –0.5V to VDD + 0.5V
Junction Temperature ................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
DC Input Voltage REF ........................... –0.5V to VDD + 0.5V
Operating Conditions for CY2305CSXC-XX and CY2309CSXC-XX
Operating Conditions table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices.
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
70
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
tPU
Power up time for all VDDs to reach minimum specified voltage
(power ramps are monotonic)
0.05
7
pF
50
ms
Operating Conditions for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Operating conditions table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
Devices.
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
–40
85
°C
CL
Load Capacitance, below 100 MHz
–
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
–
10
pF
CIN
Input Capacitance
tPU
Power up time for all VDDs to reach minimum specified voltage
(power ramps are monotonic)
–
7
pF
0.05
50
ms
Electrical Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Electrical Characteristics table for CY2305CSXC-XX and CY2309CSXC-XX Commercial Temperature Devices.
Parameter
VIL
Description
Min
Max
Unit
[5]
Test Conditions
–0.3
0.8
V
[5]
2.0
VDD + 0.3
V
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
–
50
μA
IIH
Input HIGH Current
VIN = VDD
–
100
μA
–
0.4
V
2.4
–
V
[6]
VOL
Output LOW Voltage
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
IDD (PD mode)
Power Down Supply Current
REF = 0 MHz
–
12
μA
IDD
Supply Current
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–
32
mA
Notes
5. .REF input has a threshold voltage of VDD/2.
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *H
Page 4 of 12
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CY2305C
CY2309C
Electrical Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Electrical characteristics table for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX Industrial / Automotive-A Temperature
Devices.
Parameter
Description
VIL
Input LOW Voltage[5]
[5]
Test Conditions
Min
Max
Unit
–0.3
0.8
V
2.0
VDD + 0.3
V
–
50
μA
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
IIH
Input HIGH Current
VIN = VDD
–
100
μA
VOL
Output LOW Voltage[6]
IOL = 8 mA (–1)
IOH =12 mA (–1H)
–
0.4
V
VOH
Output HIGH Voltage[6]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
2.4
–
V
IDD (PD mode) Power down Supply Current
REF = 0 MHz
–
25
μA
IDD
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
–
35
mA
Supply Current
Switching Characteristics for CY2305CSXC-XX and CY2309CSXC-XX
Switching characteristics table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature Devices. All parameters are
specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
tDC
t3
Rise Time[6]
t4
Fall Time[6]
Measured between 0.8V and 2.0V
t5
Output to Output Skew[6]
All outputs equally loaded
t6A
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
t6B
30 pF load
10 pF load
10
10
–
100
133.33
MHz
MHz
Output Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, Fout > 50 MHz
40
50
60
%
Measured at 1.4V, Fout ≤ 50 MHz
45
50
55
%
Measured between 0.8V and 2.0V
–
–
2.25
ns
–
–
2.25
ns
–
–
200
ps
–
0
±350
ps
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
CLKOUT Rising Edge[6]
Bypass Mode, CY2309C device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT pins
of devices
–
0
700
ps
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
50
175
ps
tLOCK
PLL Lock Time[6]
–
–
1.0
ms
Stable power supply, valid clock
presented on REF pin
Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature Devices. All parameters are
specified with loaded outputs.
Parameter
Name
Description
Min
Typ
Max
Unit
10
10
–
100
133.33
MHz
MHz
t1
Output Frequency
tDC
Output Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, Fout > 50 MHz
40
50
60
%
Measured at 1.4V, Fout ≤ 50 MHz
45
50
55
%
Measured between 0.8V and 2.0V
–
–
1.5
ns
Measured between 0.8V and 2.0V
–
–
1.5
ns
All outputs equally loaded
–
–
200
ps
Time[6]
t3
Rise
t4
Fall Time[6]
t5
Output to Output
Skew[6]
Document Number: 38-07672 Rev. *H
30-pF load
10-pF load
Page 5 of 12
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CY2305C
CY2309C
Switching characteristics table for CY2305CSXC-1H and CY2309CSXC-1H Commercial Temperature Devices. All parameters are
specified with loaded outputs.
Min
Typ
Max
Unit
t6A
Parameter
Delay, REF Rising Edge to Measured at VDD/2
CLKOUT Rising Edge[6]
–
0
±350
ps
t6B
Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL
CLKOUT Rising Edge[6]
Bypass Mode, CY2309C device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT pins
of devices
–
0
700
ps
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V using
Test Circuit #2
1
–
–
V/ns
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
–
175
ps
–
–
1.0
ms
tLOCK
Name
PLL Lock
Time[6]
Description
Stable power supply, valid clock
presented on REF pin
Switching Characteristics for CY2305CSXI-XX, CY2305CSXA-XX and CY2309CSXI-XX
Switching characteristics table for CY2305CSXI-1, CY2305CSXA-1, and CY2309CSXI-1 Industrial Temperature Devices. All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
t1
Output Frequency
tDC
Output Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, Fout > 50 MHz
t3
Rise Time[6]
t4
30 pF load
10 pF load
Min
Typ
10
10
Max
Unit
100
133.33
MHz
MHz
60
%
40
50
Measured at 1.4V, Fout <= 50 MHz
45
50
55
%
Measured between 0.8V and 2.0V
–
–
2.25
ns
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
2.25
ns
t5
Output to Output Skew[6]
All outputs equally loaded
–
–
200
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
0
±350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in PLL
Bypass Mode, CY2309C device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
50
175
ps
tLOCK
PLL Lock Time[6]
–
–
1.0
ms
Stable power supply, valid clock
presented on REF pin
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H Industrial / Automotive-A Temperature
Device. All parameters are specified with loaded outputs.
Parameter
Name
Description
Min
Typ
Max
Unit
10
10
–
100
133.33
MHz
MHz
40
50
60
%
Measured at 1.4V, Fout <= 50 MHz
45
50
55
%
Measured between 0.8V and 2.0V
–
–
1.5
ns
Fall Time[6]
Measured between 0.8V and 2.0V
–
–
1.5
ns
t5
Output to Output Skew[6]
All outputs equally loaded
–
–
200
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2
–
0
±350
ps
t1
Output Frequency
tDC
Output Duty Cycle[6] = t2 ÷ t1 Measured at 1.4V, Fout > 50 MHz
t3
Rise Time[6]
t4
Document Number: 38-07672 Rev. *H
30 pF load
10 pF load
Page 6 of 12
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CY2305C
CY2309C
Switching characteristics table for CY2305CSXI-1H, CY2305CSXA-1H and CY2309CSXI-1H Industrial / Automotive-A Temperature
Device. All parameters are specified with loaded outputs.
Min
Typ
Max
Unit
t6B
Parameter
Delay, REF Rising Edge to
CLKOUT Rising Edge[6]
Measured at VDD/2. Measured in PLL
Bypass Mode, CY2309C device only.
1
5
8.7
ns
t7
Device to Device Skew[6]
Measured at VDD/2 on the CLKOUT
pins of devices
–
0
700
ps
t8
Output Slew Rate[6]
Measured between 0.8V and 2.0V
using Test Circuit #2
1
–
tJ
Cycle to Cycle Jitter, peak[6] Measured at 66.67 MHz, loaded outputs
–
–
175
ps
–
–
1.0
ms
tLOCK
Name
Description
[6]
PLL Lock Time
Stable power supply, valid clock
presented on REF pin
V/ns
Switching Waveforms
Figure 3. Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Figure 4. All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
t3
3.3V
0V
t4
Figure 5. Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
t5
Document Number: 38-07672 Rev. *H
Page 7 of 12
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CY2305C
CY2309C
Figure 6. Input-Output Propagation Delay
VDD/2
INPUT
VDD/2
OUTPUT
t6
Figure 7. Device-Device Skew
CLKOUT, Device 1
VDD/2
VDD/2
CLKOUT, Device 2
t7
Test Circuits
Test Circuit # 2
Test Circuit # 1
V DD
V DD
CLK
0.1 μ F
0.1 μ F
out
OUTPUTS
OUTPUTS
10 pF
C LOAD
GND
GND
1 kΩ
V DD
V DD
0.1 μ F
1 kΩ
0.1 μ F
GND
GND
For parameter t8 (output slew rate) on -1H devices
Document Number: 38-07672 Rev. *H
Page 8 of 12
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CY2305C
CY2309C
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-Free - CY2305C
CY2305CSXC-1
8-pin 150 Mil SOIC
Commercial
CY2305CSXC-1T
8-pin 150 Mil SOIC – Tape and Reel
Commercial
CY2305CSXC-1H
8-pin 150 Mil SOIC
Commercial
CY2305CSXC-1HT
8-pin 150 Mil SOIC – Tape and Reel
Commercial
CY2305CSXI-1
8-pin 150 Mil SOIC
Industrial
CY2305CSXI-1T
8-pin 150 Mil SOIC – Tape and Reel
Industrial
CY2305CSXI-1H
8-pin 150 Mil SOIC
Industrial
CY2305CSXI-1HT
8-pin 150 Mil SOIC – Tape and Reel
Industrial
CY2305CSXA-1H
8-pin 150 Mil SOIC
Automotive-A
CY2305CSXA-1HT
8-pin 150 Mil SOIC – Tape and Reel
Automotive-A
CY2305CSXA-1
8-pin 150 Mil SOIC
Automotive-A
CY2305CSXA-1T
8-pin 150 Mil SOIC – Tape and Reel
Automotive-A
Pb-Free- CY2309C
CY2309CSXC-1
16-pin 150 Mil SOIC
Commercial
CY2309CSXC-1T
16-pin 150 Mil SOIC – Tape and Reel
Commercial
CY2309CSXC-1H
16-pin 150 Mil SOIC
Commercial
CY2309CSXC-1HT
16-pin 150 Mil SOIC – Tape and Reel
Commercial
CY2309CSXI-1
16-pin 150 Mil SOIC
Industrial
CY2309CSXI-1T
16-pin 150 Mil SOIC – Tape and Reel
Industrial
CY2309CSXI-1H
16-pin 150 Mil SOIC
Industrial
CY2309CSXI-1HT
16-pin 150 Mil SOIC – Tape and Reel
Industrial
CY2309CZXC-1
16-pin 4.4 mm TSSOP
Commercial
CY2309CZXC-1T
16-pin 4.4 mm TSSOP – Tape and Reel
Commercial
CY2309CZXC-1H
16-pin 4.4 mm TSSOP
Commercial
CY2309CZXC-1HT
16-pin 4.4 mm TSSOP – Tape and Reel
Commercial
CY2309CZXI-1
16-pin 4.4 mm TSSOP
Industrial
CY2309CZXI-1T
16-pin 4.4 mm TSSOP – Tape and Reel
Industrial
CY2309CZXI-1H
16-pin 4.4 mm TSSOP
Industrial
CY2309CZXI-1HT
16-pin 4.4 mm TSSOP – Tape and Reel
Industrial
Document Number: 38-07672 Rev. *H
Page 9 of 12
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CY2305C
CY2309C
Package Drawing and Dimensions
Figure 8. 8-Pin (150 Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.0075[0.190]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Figure 9. 16-Pin (150 Mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.386[9.804]
0.393[9.982]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0°~8°
0.0138[0.350]
0.0192[0.487]
Document Number: 38-07672 Rev. *H
0.004[0.102]
0.0098[0.249]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85068-*B
Page 10 of 12
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CY2305C
CY2309C
Figure 10. 16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05gms
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
Document Number: 38-07672 Rev. *H
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Page 11 of 12
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CY2305C
CY2309C
Document History Page
Document Title: CY2305C CY2309C 3.3V Zero Delay Clock Buffer
Document Number: 38-07672
REV.
ECN NO.
Issue Date
Orig. of
Change
**
224421
See ECN
RGL
New data sheet
*A
268571
See ECN
RGL
Added bullet for 5V tolerant inputs in the features
*B
276453
See ECN
RGL
Minor Change: Moved one sentence from the features to the Functional
Description
*C
303063
See ECN
RGL
Updated data sheet as per characterization data
*D
318315
See ECN
RGL
Data sheet rewrite
*E
344815
See ECN
RGL
Minor Error: Corrected the header of all the AC/DC tables with the right part
numbers.
*F
1279889
See ECN
KVM
Changed title from “Low Cost 3.3V Zero Delay Buffer” to “3.3V Zero Delay
Clock Buffer”
Specified the VIL minimum value to -0.3V
Specified the VIH maximum value to VDD + 0.3V
Changed DC Input Voltage (REF) maximum value in Absolute Maximum
section
Removed references to 5V tolerant inputs (pages 1 and 2)
Removed Pentium compatibility reference
Added CY2305C block diagram
Added “peak” to the jitter specifications
Changed typical jitter from 75 ps to 50 ps for standard drive devices
For standard drive devices, tightened rise/fall times from 2.5 ns to 2.25 ns
Tightened cycle-to-cycle jitter from 200 ps to 175 ps
Tightened output-to-output skew from 250 ps to 200 ps
*G
1561504
See ECN
*H
2558537
08/27/08
Description of Change
KVM/NSI Added CY2305C Automotive-A grade devices
/AESA
Extended duty cycle specs to cover entire frequency range
Changed from Preliminary to Final
KVM/AESA Added CY2305CSXA-1 and CY2305CSXA-1T parts in Ordering Information
table under Pb-free CY2305C
© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07672 Rev. *H
Revised August 27, 2008
Page 12 of 12
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
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