Infineon IPD05N03LA Optimos 2 power-transistor Datasheet

OptiMOS®2 Power-Transistor
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Product Summary
Features
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
V DS
25
V
R DS(on),max (SMD version)
5.1
mΩ
ID
50
A
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
Type
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Type
Package
Ordering Code
Marking
IPD05N03LA
P-TO252-3-11
Q67042-S4144
05N03LA
IPF05N03LA
Package
P-TO252-3-11
P-TO252-3-23
P-TO252-3-23
Q67042-S
05N03LA
P-TO251-3-11
P-TO251-3-21
IPS05N03LA
Ordering
Code
Q67042-S4144
P-TO251-3-11
Q67042-S4194
Q67042-S
05N03LA
Q67042-S4244
Q67042-S4230
IPU05N03LA
Marking
05N03LA
P-TO251-3-21
05N03LA
Q67042-S4230
05N03LA
05N03LA
05N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Parameter
Symbol Conditions
Continuous drain current
ID
Value
T C=25 °C2)
50
T C=100 °C
50
Pulsed drain current
I D,pulse
T C=25 °C3)
350
Avalanche energy, single pulse
E AS
I D=45 A, R GS=25 Ω
300
Reverse diode dv /dt
dv /dt
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
T j,max=175 °C
6
Gate source voltage4)
V GS
Power dissipation
P tot
Operating and storage temperature
T j, T stg
T C=25 °C
IEC climatic category; DIN IEC 68-1
Rev. 1.7
Unit
A
mJ
kV/µs
±20
V
94
W
-55 ... 175
°C
55/175/56
page 1
2004-05-19
Parameter
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Values
Symbol Conditions
Unit
min.
typ.
max.
-
-
1.6
minimal footprint
-
-
75
6 cm2 cooling area5)
-
-
50
25
-
-
Thermal characteristics
Thermal resistance, junction - case
R thJC
SMD version, device on PCB
R thJA
K/W
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V (BR)DSS V GS=0 V, I D=1 mA
Gate threshold voltage
V GS(th)
V DS=V GS, I D=50 µA
1.2
1.6
2
Zero gate voltage drain current
I DSS
V DS=25 V, V GS=0 V,
T j=25 °C
-
0.1
1
V DS=25 V, V GS=0 V,
T j=125 °C
-
10
100
V
µA
Gate-source leakage current
I GSS
V GS=20 V, V DS=0 V
-
10
100
nA
Drain-source on-state resistance
R DS(on)
V GS=4.5 V, I D=30 A
-
6.9
8.6
mΩ
V GS=4.5 V, I D=30 A,
SMD version
-
6.7
8.4
V GS=10 V, I D=30 A
-
4.4
5.3
V GS=10 V, I D=30 A,
SMD version
-
4.2
5.1
-
1
-
Ω
31
62
-
S
Gate resistance
RG
Transconductance
g fs
|V DS|>2|I D|R DS(on)max,
I D=30 A
1)
J-STD20 and JESD22
2)
Current is limited by bondwire; with an R thJC=1.6 K/W the chip is able to carry 106 A.
3)
See figure 3
4)
T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.7
page 2
2004-05-19
Parameter
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Values
Symbol Conditions
Unit
min.
typ.
max.
-
2413
3110
-
921
1225
Dynamic characteristics
Input capacitance
C iss
Output capacitance
C oss
Reverse transfer capacitance
Crss
-
112
167
Turn-on delay time
t d(on)
-
10
15
Rise time
tr
-
7.8
12
Turn-off delay time
t d(off)
-
31
38
Fall time
tf
-
4.8
6.0
Gate to source charge
Q gs
-
7.6
10
Gate charge at threshold
Q g(th)
-
3.9
5.0
Gate to drain charge
Q gd
-
5.2
7.8
Switching charge
Q sw
-
9.0
13
Gate charge total
Qg
-
19
25
Gate plateau voltage
V plateau
-
3.2
-
Gate charge total, sync. FET
Q g(sync)
V DS=0.1 V,
V GS=0 to 5 V
-
17
22
Output charge
Q oss
V DD=15 V, V GS=0 V
-
20
27
-
-
50
-
-
350
V GS=0 V, V DS=15 V,
f =1 MHz
V DD=15 V, V GS=10 V,
I D=25 A, R G=2.7 Ω
pF
ns
Gate Charge Characteristics 6)
V DD=15 V, I D=25 A,
V GS=0 to 5 V
nC
V
nC
Reverse Diode
Diode continous forward current
IS
Diode pulse current
I S,pulse
Diode forward voltage
V SD
V GS=0 V, I F=50 A,
T j=25 °C
-
0.91
1.2
V
Reverse recovery charge
Q rr
V R=15 V, I F=I S,
di F/dt =400 A/µs
-
-
10
nC
6)
Rev. 1.7
T C=25 °C
A
See figure 16 for gate charge parameter definition
page 3
2004-05-19
1 Power dissipation
2 Drain current
P tot=f(T C)
I D=f(T C); V GS≥10 V
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
60
100
90
50
80
70
40
I D [A]
P tot [W]
60
50
30
40
20
30
20
10
10
0
0
0
50
100
150
200
0
50
100
T C [°C]
150
200
T C [°C]
3 Safe operating area
4 Max. transient thermal impedance
I D=f(V DS); T C=25 °C; D =0
Z thJC=f(t p)
parameter: t p
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
10 µs
100
1
DC
1 ms
0.2
0.1
0.05
10 ms
10
0.5
Z thJC [K/W]
I D [A]
100 µs
0.1
0.02
0.01
single pulse
1
0.1
1
10
100
V DS [V]
Rev. 1.7
0.01
0
0
0
0
0
0
1
10-6
10-5
10-4
10-3
10-2
10-1
100
t p [s]
page 4
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
5 Typ. output characteristics
6 Typ. drain-source on resistance
I D=f(V DS); T j=25 °C
R DS(on)=f(I D); T j=25 °C
parameter: V GS
parameter: V GS
20
100
10 V
90
4.1 V
4.5 V
3.2 V
3.8 V
3.5 V
4.1 V
16
80
70
14
R DS(on) [mΩ]
3.8 V
60
I D [A]
3V
18
50
3.5 V
40
12
10
8
4.5 V
6
30
3.2 V
10 V
4
20
3V
10
2
2.8 V
0
0
0
1
2
0
3
20
40
V DS [V]
60
80
100
I D [A]
7 Typ. transfer characteristics
8 Typ. forward transconductance
I D=f(V GS); |V DS|>2|I D|R DS(on)max
g fs=f(I D); T j=25 °C
parameter: T j
100
80
70
80
60
50
I D [A]
g fs [S]
60
40
40
30
20
20
175 °C
10
25 °C
0
0
0
1
2
3
4
5
Rev. 1.7
0
10
20
30
40
50
60
I D [A]
V GS [V]
page 5
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
R DS(on)=f(T j); I D=30 A; V GS=10 V
V GS(th)=f(T j); V GS=V DS
parameter: I D
10
2.5
9
8
2
500 µA
6
98 %
5
1.5
V GS(th) [V]
R DS(on) [mΩ]
7
typ
4
50 µA
1
3
2
0.5
1
0
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. capacitances
12 Forward characteristics of reverse diode
C =f(V DS); V GS=0 V; f =1 MHz
I F=f(V SD)
parameter: T j
10000
1000
Ciss
Coss
100
25 °C
Crss
25 °C, 87%
10
100
1
10
0
5
10
15
20
25
30
0.0
0.5
1.0
1.5
2.0
V SD [V]
V DS [V]
Rev. 1.7
175 °C, 98%
175 °C
I F [A]
C [pF]
1000
page 6
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
13 Avalanche characteristics
14 Typ. gate charge
I AS=f(t AV); R GS=25 Ω
V GS=f(Q gate); I D=25 A pulsed
parameter: Tj(start)
parameter: V DD
100
12
15 V
10
100 °C
150 °C
5V
25 °C
20 V
V GS [V]
I AV [A]
8
10
6
4
2
1
0
1
10
100
1000
0
20
40
Q gate [nC]
t AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V BR(DSS)=f(T j); I D=1 mA
29
V GS
28
Qg
27
V BR(DSS) [V]
26
25
24
V g s(th)
23
22
Q g(th)
21
Q sw
Q gs
20
-60
-20
20
60
100
140
Q g ate
Q gd
180
T j [°C]
Rev. 1.7
page 7
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Package Outline
P-TO252-3-11: Outline
Footprint:
Packaging:
Dimensions in mm
Rev. 1.7
page 8
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Package Outline
P-TO252-3-23: Outline
Footprint:
Dimensions in mm
Rev. 1.7
page 9
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Package Outline
P-TO251-3-11: Outline
P-TO251-3-21: Outline
Dimensions in inch [mm]
Rev. 1.7
page 10
2004-05-19
IPD05N03LA
IPF05N03LA
IPS05N03LA
IPU05N03LA
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as
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We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
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For further information on technology, delivery terms and conditions and prices, please contact your
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Due to technical requirements, components may contain dangerous substances.
For information on the types in question, please contact your nearest Infineon Technologies office.
Infineon Technologies' components may only be used in life-support devices or systems with the
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Rev. 1.7
page 11
2004-05-19
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