Cypress CY2210PVC-3 133-mhz spread spectrum clock synthesizer/driver with agp, usb, and drcg support Datasheet

0
CY2210
133-MHz Spread Spectrum Clock Synthesizer/Driver
with AGP, USB, and DRCG Support
Features
Benefits
• Mixed 2.5V and 3.3V Operation
• Compliant to Intel® CK133 (CY2210-3) & CK133W
(CY2210-2) synthesizer and driver specification
Usable with Pentium® II and Pentium® III processors
• Multiple output clocks at different frequencies
— Four CPU clocks, up to 133 MHz
— Eight synchronous PCI clocks, 1 free-running
— Two CPU/2 clocks, at one-half the CPU frequency
— Four AGP clocks at 66 MHz
— Three synchronous APIC clocks, at 16.67 MHz
— One USB clock at 48 MHz
— Two reference clocks at 14.318 MHz
Single-chip main motherboard clock generator
— Driven together, support 4 CPUs and a chipset
— Support for 4 PCI slots and chipset
— Drives up to two main memory clock generators, including DRCG (CPUCLK/2)
— Support for multiple AGP slots
— Support multiprocessing systems
— Supports USB frequencies and I/O chip
• Spread Spectrum clocking
— 32.5-kHz modulation frequency @ 133 MHz
— 33.1-kHz modulation frequency @ 100 MHz for
CY2210-02/03
— 33.4-kHz modulation frequency @ 100 MHz for
CY2210-04
— EPROM programmable percentage of spreading.
Default is –0.6%, which is recommended by Intel
Enables reduction of EMI in some systems
• Power-down features
Supports mobile systems
• Three Select inputs
Supports up to eight CPU clock frequencies
• Low-skew and low-jitter outputs
Meets tight system timing requirements at high frequency
• OE and Test Mode support
Enables ATE and “bed of nails” testing
• 56-pin SSOP package
Widely available, standard package enables lower cost
Pin Configuration
Logic Block Diagram
SSOP
Top View
VSSREF
REFCLK0
1
56
VDDAPIC
2
55
APICCLK2
REFCLK1
3
54
APICCLK1
VDDREF
4
53
APICCLK0
XTALIN
5
52
VSSAPIC
XTALOUT
VSSPCI
6
51
VDDCPU/2
7
50
PCICLK_F
8
49
PCICLK1
VDDPCI
9
48
47
CPUCLK/2
(DRCG)
CPUCLK/2
(DRCG)
VSSCPU/2
VDDCPU
PCICLK2
11
46
CPUCLK3
PCICLK3
45
CPUCLK2
VSSPCI
12
13
44
VSSCPU
PCICLK4
14
43
VDDCPU
PCICLK5
15
42
CPUCLK1
VDDPCI
16
41
PCICLK6
PCICLK7
17
40
CPUCLK0
VSSCPU
18
39
AVDD
VSSPCI
VSSAGP
19
38
20
37
AVSS
PCI_STOP
AGPCLK0
21
36
CPU_STOP
AGPCLK1
VDDAGP
22
35
23
34
PWR_DWN
SPREAD
VSSAGP
24
25
33
SEL1
32
SEL0
26
31
VDDUSB
27
30
28
29
USBCLK
VSSUSB
CPUCLK [0–3]
CPU_STOP
XTALIN
XTALOUT
SEL1
SEL0
SEL133
SPREAD
14.318
MHz
OSC.
Divider,
EPROMProgDelay
and
Stop Logic
CPU
PLL
CPUCLK/2 [0–1] (DRCG)
PCICLK_F (33.33 MHz)
PCICLK [1–7] (33.33 MHz)
EPROM
APICCLK [0–2] (16.67 MHz)
PCI_STOP
AGPCLK [0–3] (66.67 MHz)
PWR_DWN
SYS
PLL
USBCLK (48 MHz)
AGPCLK2
AGPCLK3
VDDAGP
SEL133
10
CY2210-2/-3/-4
REFCLK [0–1] (14.318 MHz)
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-07204 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 14, 2002
CY2210
Pin Summary
Name
Pins
Description
VSSREF
1
3.3V Reference ground
VDDREF
4
3.3V Reference voltage supply
VSSPCI
7, 13, 19
3.3V PCI ground
VDDPCI
10, 16
3.3V PCI voltage supply
VSSAGP
20, 24
3.3V AGP ground
VDDAGP
23, 27
3.3V AGP voltage supply
VSSUSB
29
3.3V USB ground
VDDUSB
31
3.3V USB voltage supply
VSSCPU
40, 44
2.5V CPU ground
VDDCPU
43, 47
2.5V CPU voltage supply
VSSCPU/2
48
2.5V CPU/2 ground
VDDCPU/2
51
2.5V CPU/2 voltage supply
VSSAPIC
52
2.5V APIC ground
VDDAPIC
56
2.5V APIC voltage supply
AVSS
38
Analog ground to PLL and Core
39
Analog voltage supply to PLL and Core
XTALIN
5
Reference crystal input
XTALOUT[1]
6
Reference crystal feedback
CPUCLK [0–3]
41, 42, 45, 46
CPU clock outputs
PCICLK [1–7]
9, 11, 12, 14, 15, 17, 18
PCI clock outputs, synchronously running at 33.33 MHz
PCICLK_F
8
Free running PCI clock
CPUCLK/2
49, 50
CPU/2 clock outputs, drive memory clock generator
AGPCLK [0–3]
21, 22, 25, 26
AGP clock outputs, running at 66.66 MHz
APICCLK [0–2]
53, 54, 55
APIC clock outputs, running at 16.67 MHz
REFCLK [0–1]
2, 3
Reference clock outputs, 14.318 MHz
USBCLK
30
48-MHz USB clock output
CPU_STOP
36
Active LOW input, disables CPU and AGP clocks when asserted
PCI_STOP
37
Active LOW input, disables PCI clocks when asserted
PWR_DWN
35
Active LOW input, powers down part when asserted
SPREAD
34
Active LOW input, enables spread spectrum when asserted
SEL1
33
CPU frequency select input (See Function Table)
SEL0
32
CPU frequency select input (See Function Table)
SEL133
28
CPU frequency select input (See Function Table)
AVDD
[1]
Note:
1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator
Topics.”
Document #: 38-07204 Rev. *A
Page 2 of 10
CY2210
Function Table[2]
SEL133
0
SEL1
CPUCLK
(MHz)
SEL0
0
0
Hi-Z
CPUCLK/2
(MHz)
Hi-Z
0
0
1
100.227
0
1
0
0
1
1
0
1
[3]
AGPCLK
(MHz)
PCICLK
(MHz)
Hi-Z
[3]
USBCLK
(MHz)
Hi-Z
[3]
Hi-Z
[3]
REFCLK
(MHz)
Hi-Z
48.008
[3]
APICCLK
(MHz)
Hi-Z
14.318
[3]
16.705[3]
50.114
66.818
33.409
100
50
66.67
33.33
OFF
14.318
16.67
1
100
50
66.67
33.33
48
14.318
16.67
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
0
133.33
66.67
66.67
33.33
OFF
14.318
16.67
1
1
1
133.33
66.67
66.67
33.33
48
14.318
16.67
Actual Clock Frequency Values
Clock
Output
Target
Frequency
(MHz)
-2
Actual
Frequency
(MHz)
-3
-4
-2
PPM
-3
-4
-2
-3
-4
CPUCLK
100.0
100.0
100.0
99.126
99.126
100.227
–8740
–8740
+2714
CPUCLK
133.33
133.33
133.33
132.769
132.769
132.769
–4208
–4208
–4208
USBCLK
48.0
48.0
48.0
48.008
48.008
48.008
167
167
167
Clock Enable Configuration
CPU_STOP
PWR_DWN
PCI_STOP
CPUCLK
CPUCLK/2
AGP
PCI
PCI_F
REF
APIC
OSC.
VCOs
X
0
X
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
0
1
0
LOW
ON
LOW
LOW
ON
ON
ON
ON
0
1
1
LOW
ON
LOW
ON
ON
ON
ON
ON
1
1
0
ON
ON
ON
LOW
ON
ON
ON
ON
1
1
1
ON
ON
ON
ON
ON
ON
ON
ON
Clock Driver Impedances
Impedance
VDD Range
Buffer Type
Minimum
Ω
Typical
Ω
Maximum
Ω
2.375–2.625
Type 1
13.5
29
45
USB, REF
3.135–3.465
Type 3
20
40
60
PCI, AGP
3.135–3.465
Type 5
12
30
55
Buffer Name
CPU, CPU/2, APIC
Notes:
2. TCLK is a test clock driven in on the XTALIN input in test mode.
3. Only CY2210-2 supports this option. In CY2210-3, this selection is defined as “N/A” or “Reserved”.
Document #: 38-07204 Rev. *A
Page 3 of 10
CY2210
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature (Non-Condensing) ... –65°C to +150°C
Junction Temperature............................................... +150°C
Supply Voltage ..................................................–0.5 to +7.0V
Package Power Dissipation.............................................. 1W
Input Voltage .............................................. –0.5V to VDD+0.5
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions Over which Electrical Parameters are Guaranteed
Min.
Max.
Unit
VDDREF, VDDPCI, AVDD,
VDDAGP, VDDUSB
Parameter
3.3V Supply Voltages
Description
3.135
3.465
V
VDDCPU, VDDCPU/2
CPU and CPU/2 Supply Voltage
2.375
2.625
V
VDDAPIC
APIC Supply Voltage
2.375
2.625
V
TA
Operating Temperature, Ambient
0
70
°C
CL
Max. Capacitive Load on
CPUCLK, CPUCLK/2, USBCLK, REF, APIC
PCICLK, AGP
f(REF)
Reference Frequency, Oscillator Nominal Value
tPU
Power-up time for all VDD's to reach minimum
specified voltage (power ramps must be monotonic)
pF
20
30
14.318
14.318
MHz
0.05
50
ms
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
VIH
High-level Input Voltage
Except Crystal Pads. Threshold voltage for crystal pads = VDD/2
VIL
Low-level Input Voltage
Except Crystal Pads
VOH
High-level Output Voltage[4] CPU, CPU/2, APIC
VOL
[4]
Low-level Output Voltage
2.0
V
0.8
IOH = –1 mA
2.0
USB, REF, PCI, AGP
IOH = –1 mA
2.4
CPU, CPU/2, APIC
IOL = 1 mA
0.4
USB, REF, PCI, AGP
IOL = 1 mA
0.4
V
V
V
µA
IIH
Input High Current
IIL
Input Low Current
0 < VIN < VDD
10
µA
IOH
High-level Output Current[4]
CPU, CPU/2
VOH = 2.0V
–16
–60
mA
APIC
VOH = 2.0V
–20
–72
USB, REF
VOH = 2.4V
–15
–51
AGP, PCI
VOH = 2.4V
–30 –100
IOL
Low-level Output
Current[4]
0 < VIN < VDD
10
CPU, CPU/2
VOL = 0.4V
19
49
APIC
VOL = 0.4V
25
58
USB, REF
VOL = 0.4V
10
24
AGP, PCI
VOL = 0.4V
20
49
mA
10
µA
2.5V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz
90
mA
3.3V Power Supply Current AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz
160
mA
IDDPD2
2.5V Shutdown Current
AVDD/VDD33 = 3.465V, VDD25 = 2.625V
100
µA
IDDPD3
3.3V Shutdown Current
AVDD/VDDQ3 = 3.465V, VDD25 = 2.625V
200
µA
IOZ
Output Leakage Current
IDD2
IDD3
Three-state
Note:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07204 Rev. *A
Page 4 of 10
CY2210
Switching Characteristics[4, 5] Over the Operating Range
Parameter
Output
Description
Cycle[6]
Test Conditions
Min.
Max.
Unit
t1
All
Output Duty
t1A/t1B
45
55
%
t2
CPU, CPU/2,
APIC
Rising Edge Rate
Between 0.4V and 2.0V
1.0
4.0
V/ns
t2
USB, REF
Rising Edge Rate
Between 0.4V and 2.4V
0.5
2.0
V/ns
t2
PCI, AGP
Rising Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t3
CPU, CPU/2,
APIC
Falling Edge Rate
Between 2.0V and 0.4V
1.0
4.0
V/ns
t3
USB, REF
Falling Edge Rate
Between 2.4V and 0.4V
0.5
2.0
V/ns
t3
PCI, AGP
Falling Edge Rate
Between 2.4V and 0.4V
1.0
4.0
V/ns
t6
CPU
CPU-CPU Skew
Measured at 1.25V
175
ps
t7
CPU/2
CPU/2-CPU/2 Skew
Measured at 1.25V
175
ps
t8
APIC
APIC-APIC Skew
Measured at 1.25V
250
ps
t9
AGP
AGP-AGP Skew
Measured at 1.5V
250
ps
t10
PCI
PCI-PCI Skew
Measured at 1.5V
500
ps
t11
CPU, AGP
CPU-AGP Clock Skew
CPU leads. Measured at 1.25V for
2.5V clocks and 1.5V for 3.3V clocks
0
1.5
ns
t12
AGP, PCI
AGP-PCI Clock Skew
AGP leads. Measured at 1.5V
1.5
4.0
ns
t13
CPU, APIC
CPU-APIC Clock Skew
CPU leads. Measured at 1.25V
1.5
4
ns
t14
CPU, PCI
CPU-PCI Clock Skew
CPU leads. Measured at 1.25V clocks
and 1.5V for 3.3V clocks
1.5
4
ns
CPU
Cycle-Cycle Clock Jitter
With all outputs running (CY2210-2)
150
ps
CPU
Cycle-Cycle Clock Jitter
With all outputs running
(CY2210-3/-4)
250
ps
CPU
Cycle-Cycle Clock Jitter
With the USB output turned off
(CY2210-3/-4)
200
ps
CPU/2
Cycle-Cycle Clock Jitter
250
ps
APIC
Cycle-Cycle Clock Jitter
500
ps
USB
Cycle-Cycle Clock Jitter
500
ps
AGP
Cycle-Cycle Clock Jitter
500
ps
REF
Cycle-Cycle Clock Jitter
1000
ps
CPU, PCI
Settle Time
3
ms
CPU and PCI clock stabilization from
power-up
Notes:
5. All parameters specified with loaded outputs.
6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V.
Document #: 38-07204 Rev. *A
Page 5 of 10
CY2210
Switching Waveforms
Duty Cycle Timing
t1A
t1B
All Outputs Rise/Fall Time
VDD
OUTPUT
0V
t3
t2
CPU-CPU Clock Skew
CPUCLK
CPUCLK
t6
CPU/2 - CPU/2 Clock Skew
CPU/2
CPU/2
t7
APIC-APIC Clock Skew
APIC
APIC
t8
Document #: 38-07204 Rev. *A
Page 6 of 10
CY2210
Switching Waveforms (continued)
AGP-AGP Clock Skew
AGP
AGP
t9
PCI-PCI Clock Skew
PCI
PCI
t10
CPU-AGP Clock Skew
CPU
AGP
t11
AGP - PCI Clock Skew
AGP
PCI
t12
CPU-APIC Clock Skew
CPU
t13
APIC
Document #: 38-07204 Rev. *A
Page 7 of 10
CY2210
Switching Waveforms (continued)
CPU-PCI Clock Skew
CPU
t14
PCI
CPU_STOP Timing
[7, 8]
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPU, CPU/2, AGP
(External)
PCI_STOP
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
PCI_STOP
PCICLK
(External)
PWR_DOWN
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Notes:
7. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
8. CPU_STOP may be applied asynchronously. It is synchronized internally.
Document #: 38-07204 Rev. *A
Page 8 of 10
CY2210
Test Circuit
VDDPCI, VDDAGP,
VDDUSB, VDDREF,
AVDD
1, 7, 13, 19, 20, 24, 29, 38, 40, 44, 48, 52
4, 10, 16, 23, 27, 31
CY2210
VDDCPU, VDDCPU/2,
VDDAPIC
OUTPUTS
CLOAD
43, 47, 51, 56
Note: Each supply pin must have an individual decoupling capacitor.
Note: All capacitors must be placed as close to the pins as is physically possible.
Ordering Information
Ordering Code
CY2210PVC-2/-3/-4
Package
Name
O56
Package Type
56-Pin SSOP
Operating
Range
Commercial
Package Diagram
56-Lead Shrunk Small Outline Package O56
51-85062-*C
Document #: 38-07204 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2210
Document Title: CY2210 133-MHz Spread Spectrum Clock Synthesizer/Driver with AGP, USB, and DRCG Support
Document Number: 38-07204
ECN NO.
Issue
Date
Orig. of
Change
**
111724
01/10/02
DSG
Change from Spec number: 38-00888 to 38-07204
*A
121839
12/14/02
RBI
Power up requirements added to Operating Conditions Information
REV.
Document #: 38-07204 Rev. *A
Description of Change
Page 10 of 10
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