FAIRCHILD SPT7852SIT

SPT7852
DUAL 10-BIT, 20 MSPS, 160 mW A/D CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
Dual 10-Bit/20 MSPS Analog-to-Digital Converter
Monolithic CMOS
Internal Track-and-Hold
Low Power Dissipation: 160 mW
4 Vp-p Analog Input Range for Each ADC
Single +5 Volt Power Supply
with Option for 3.3 V Digital Outputs
• Tri-State, TTL-Compatible Outputs
• Overrange Bit
• Selectable Two’s Complement or Straight Binary Output
Video Set-Top Boxes
Cellular Base Stations
QPSK/QAM RF Demodulation
S-Video Digitizers
Composite Video Digitizers
Portable and Handheld Instrumentation
GENERAL DESCRIPTION
The SPT7852 has two 10-Bit CMOS analog-to-digital converters that can sample data at speeds up to 20 MSPS. It
has excellent low noise performance with a very low typical
power dissipation of only 160 mW—that’s the total power
for both converters. The SPT7852 uses a dual configuration
of the proprietary circuit design found in our 10-bit CMOS
single converter family, to achieve its high performance in a
CMOS process.
The SPT7852 is specifically designed for video decoding
applications and is ideal for S-video decoding and decoding
of multiple composite video sources. It also has excellent
application in the area of coherent I/Q demodulation in such
applications as QAM demodulation and TV set-top box converters.
Inputs and outputs are TTL/CMOS-compatible to interface
with TTL/CMOS-logic systems. Output data format is selectable for either straight binary or two’s complement. The
SPT7852 is available in a 44L TQFP package in commercial
and industrial temperature ranges. It is also available in die
form. For availability of extended temperature ranges,
please contact the factory.
BLOCK DIAGRAM
MSB
Invert
10
VINA
T/H
Clock
Reset
Output
Enable
Overrange
DA0-9
Reference
Ladder
Reference In
VINB
Output
Buffer
ADCA
T/H
ADCB
Timing
Generation
10
Output
Buffer
Overrange
DB0-9
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ......................................................................... +6 V
DVDD ......................................................................... +6 V
Output
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ................................... 0 to 70 °C
Junction Temperature ........................................... 175 °C
Lead Temperature, (soldering 10 seconds) .......... 300 °C
Storage Temperature ............................... –65 to +150 °C
Input Voltages
Analog Input ................................. –0.5 V to AVDD +0.5 V
VRef .............................................. –1.5 V to AVDD +0.8 V
CLK Input ................................................................... VDD
AVDD – DVDD ...................................................... ±100 mV
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS FOR EACH CHANNEL
TA = TMIN to TMAX, AVDD = DVDD = +5.0 V, VIN =0 to 4 V, ƒS =20 MSPS, ƒCLK =40 MHz, VRHS =4.0 V, VRLS =0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
Resolution
MIN
TYP
MAX
10
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
IV
IV
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
Gain Error
V
V
V
V
VI
VI
VRLS
50
VI
350
425
500
IV
IV
V
V
V
0
3.0
1.0
4.0
150
150
2.0
AVDD
5.0
Conversion Characteristics
Maximum Conversion Rate1
Minimum Conversion Rate1
Pipeline Delay (Latency)
Aperture Delay Time
Aperture Jitter Time
VI
IV
IV
V
V
20
Dynamic Performance
Effective Number of Bits
ƒIN=3.58 MHz
ƒIN= 10 MHz
VI
VI
8.4
7.9
Reference Input
Resistance
Voltage Range
VRLS
VRHS
VRHS – VRLS
∆(VRHF – VRHS)
∆(VRLS – VRLF)
12X
Full Power
VRHS – VRLS
UNITS
±1.0
±1.0
LSB
LSB
VRHS
5.0
35
±2.0
±2.0
V
kΩ
pF
MHz
LSB
LSB
Ω
V
V
V
mV
mV
5
15
MHz
kHz
Clock Cycles
ns
ps
8.9
8.4
Bits
Bits
100
12
Clock required.
SPT7852
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ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD = DVDD = +5.0 V, VIN =0 to 4 V, ƒS =20 MSPS, ƒCLK =40 MHz, VRHS = 4.0 V, VRLS =0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
VI
VI
53
52
57
56
dB
dB
dB
dB
Dynamic Performance
Signal-to-Noise Ratio
(without Harmonics)
ƒIN=3.58 MHz
ƒIN=10 MHz
Harmonic Distortion
ƒIN=3.58 MHz
ƒIN=10 MHz
Signal-to-Noise and Distortion
(SINAD)
ƒIN=3.58 MHz
ƒIN=10 MHz
Channel-to-Channel Crosstalk
ƒIN=3.58 MHz
Channel-to-Channel Gain Matching Full Scale
Spurious Free Dynamic Range
ƒIN=3.58 MHz @ –3 dB FS
Differential Phase
Differential Gain
VI
VI
56
52
59
54
VI
VI
IV
IV
V
V
V
52
49
55
52
70
0.04
66
0.2
0.3
Digital Inputs
Logic "1" Voltage
Logic "0" Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
V
2.0
Digital Outputs
Logic "1" Voltage
Logic "0" Voltage
tRISE/tFALL
Output Enable to Data Output Delay
Power Supply Requirements
Voltages DVDD
AVDD
OVDD
Currents AIDD
DIDD
Power Dissipation
VIL=0 V
VIH=5 V
IOH=0.5 mA
IOS=1.6 mA
15 pF Load
20 pF Load, TA=+25 °C
50 pF Load Over Temp.
Total for Both Converter
Channels
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection. Any
blank section in the data column indicates that the
specification is not tested at the specified condition.
TEST LEVEL
MAX
dB
dB
dB
dB
dB
Degree
%
0.8
+10
+10
–10
–10
5
VI
VI
V
V
V
OVDD–0.5
IV
IV
IV
VI
VI
VI
4.75
4.75
2.7
0.4
10
10
22
5.0
5.0
5.0
15
17
160
UNITS
5.25
5.25
5.25
18
20
190
V
V
µA
µA
pF
V
V
ns
ns
ns
V
V
V
mA
mA
mW
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA=+25 °C, and sample tested at
the specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characterization data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range.
SPT7852
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Figure 1 –Typical Interface Circuit
+A5
+A5
Ref In
(+4 V)
MSBINV
3-st EN
EN
Reset
VRHF
11
Digital
Output A
VRHS
VRLS
VRLF
DAV
SPT7852
Interfacing
Logic
VCAL
VIN1
VINA
VIN2
VINB
Clock
CLK
11
Digital
Output B
AVDD DVDD
GND
.1 µF
OVDD
.1 µF
FB
*
4.7 µF
4.7 µF
+A5
1.
2.
3.
4.
FB
*
3.3 V/5 V
Place the ferrite bead (*) as close to the ADC as possible.
Place 0.1 µF decoupling capacitors as close to the ADC as possible.
All capacitors are 0.1 µF surface-mount unless otherwise specified.
All analog input pins (references, analog input, clock input) must
be protected. (See absolute maximum ratings.)
TYPICAL INTERFACE CIRCUIT
POWER SUPPLIES AND GROUNDING
Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical interface requirements when using the SPT7852 in normal
circuit operation. The following sections provide descriptions of the major functions and outline critical performance
criteria to consider for achieving the optimal device performance.
Fairchild suggests that both the digital and the analog supply voltages on the SPT7852 be derived from a single analog supply as shown in figure 1. A separate digital supply
must be used for all interface circuitry. Fairchild suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
SPT7852
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The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by two clock cycles so that the
analog input is sampled on every other cycle of the input
clock by exactly one ADC section. After 16 clock periods,
the timing cycle repeats. The sample rate for the configuration is one-half of the clock rate, e.g., for a 40 MHz clock
rate, the input sample rate is 20 MHz. The latency from analog input sample to the corresponding digital output is 12
clock cycles.
OPERATING DESCRIPTION
The general architecture for the CMOS ADC is shown in the
block diagram. The design contains two sets of eight identical
successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 8:1 digital output
multiplexer, correction logic, and a voltage reference generator which provides common reference levels for each ADC
section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
follows:
• Since only sixteen comparators are used, a huge power
savings is realized.
• The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator's response to a reference zero.
Table I – Clock Cycles
Clock
Operation
1
Reference zero sampling
2
Auto-zero comparison
3
Auto-calibrate comparison
4
Input sample
5–15
11-bit SAR conversion
16
Data transfer
• The auto-calibrate operation, which calibrates the gain of
the MSB reference and the LSB reference, is also done
with a closed loop system. Multiple samples of the gain
error are integrated to produce a calibration voltage for
each ADC section.
• Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator per
VIN input samples the input during a clock cycle.
• The total input capacitance is very low since sections of
the converter which are not sampling the signal are isolated from the input by transmission gates.
SPT7852
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Figure 2 – Timing Diagram 1
tC
tCLK
2
Clock
Reset
td
1
Data
Valid (DAV)
Data
Output
(Channel A)
Data
Output
(Channel B)
tSet
3
tHold
tOD
Invalid
4
Invalid
Invalid
Invalid
Invalid
tOD
Invalid
Notes:
1) Data Valid is forced low on Reset = High.
2) Data updated on first rising edge of clock after Reset goes low.
3) Data Valid rising edge will occur on the second rising edge of Clock
after Reset goes low. Use the rising edge of Data Valid to latch the ADC output data.
4) Analog Input Data is sampled during the first clock cycle after Reset goes low.
Valid data output from this sample will be available 12 clock cycles
later (6 Data Valid cycles). All data during the 12 clock cycle latency is invalid.
The reset pin is low for normal device operation. When reset
is brought high, Data Valid (DAV) is immediately forced low
and data output updates are suspended. Operation will resume on the first rising edge of the clock after the reset pin
has been brought low. The first Data Valid rising edge will
occur on the second edge of the clock after the reset goes
low.
CLOCK INPUT
The SPT7852 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over a
wide range of input clock duty cycles without degrading the
dynamic performance. The device's sample rate is 1/2 of
the input clock frequency. (See timing diagram.)
The first analog input sample will be taken during the first
clock cycle after reset goes low. Valid data from this
sample will be available 12 clock cycles later. All data during this 12 cycle latency will be invalid (Refer to figure 3,
Timing Diagram 2.)
TIMING AND RESET FUNCTION
The two on-board ADCs in the SPT7852 are driven off of a
single external TTL clock. This external clock must be 2X
the desired sample rate. In applications that require a
known phase relationship between the clock, analog input
sampling and valid data output, a reset function is provided
to establish a known phase relationship. (Because of the 2X
clock, an exact phase relationship will not be known otherwise.) Refer to figure 2, Timing Diagram 1.
SPT7852
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Figure 3 – Timing Diagram 2
1
Analog In
(Channel A)
5
2
3
6
7
4
8
11
10
9
Analog In
(Channel B)
Clock In
Reset
Sampling Clock
(Internal)
Invalid
Data Out
(Channel A)
Valid
1
Invalid
Data Out
(Channel B)
2
3
4
3
4
Valid
1
2
Data Valid
Table II – Timing Parameters Table
DESCRIPTION
PARAMETERS
Conversion Time
Clock Period
Clock Duty Cycle
Output Delay
(15 pF Load)
DAV Pulse Width
Clock to DAV
Data Set Up Time
Data Hold Time
tc
tCLK
tOD
tDAV
td
tSet
tHold
MIN
2*tCLK
25
40
TYP
50
11
tCLK
15
MAX UNITS
60
ns
ns
%
ns
ns
ns
22
28
SPT7852
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Figure 5 – Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
Figure 4 – Ladder Force/Sense Circuit
+
-
1
2
+4.0 V
External
Reference
VRHF
150 mV
VRHS
(+3.85 V)
VRHS
R/2
R
R
3
VRLS
R
R=30 Ω (typ)
All capacitors are 0.01 µF
R
+
4
R
VRLF
R
5
VRLS
AGND
(0.150 V)
150 mV
R/2
VRLF (AGND)
0.0 V
All capacitors are 0.01 µF
tied to AGND. A 150 mV drop is seen at VRHS (= 3.85 V) and
a 150 mV increase is seen at VRLS (= 0.150 V).
VOLTAGE REFERENCE
The SPT7852 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. Both ADCs share the
same reference ladder. The lower side of the ladder is typically tied to AGND (0.0 V), but can be run up to 2.0 V with a
second reference. The analog input voltage range will track
the total voltage difference measured between the ladder
sense lines, VRHS and VRLS.
ANALOG INPUT
VINA and VINB are the analog inputs for channel A and channel B, respectively. Both channels share the same reference ladder. The input voltage range is from VRLS to VRHS
(typically 4.0 V) and will scale proportionally with respect to
the voltage reference. (See voltage reference section.)
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in figure 4, offset and gain errors of less than ±2 LSB can be obtained.
The drive requirements for the analog inputs are very minimal when compared to most other converters due to the
SPT7852’s extremely low input capacitance of only 5 pF
and very high input resistance of 50 kΩ.
The analog input should be protected through a series resistor and diode clamping circuit as shown in figure 6.
In cases where wider variations in offset and gain can be
tolerated, VRef can be tied directly to VRHF and AGND can
be tied directly to VRLF as shown in figure 5. Decouple force
and sense lines to AGND with a .01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
Figure 6 – Recommended Input Protection Circuit
+V
The reference ladder circuit shown in figure 5 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Typically, the top side voltage drop for
VRHF to VRHS will equal:
AVDD
D1
Buffer
VRHF – VRHS = 3.75% of (VRHF – VRLF) (typical),
ADC
47 Ω
D2
and the bottom side voltage drop for VRLS to VRLF will equal:
VRLS – VRLF = 3.75% of (VRHF – VRLF) (typical).
-V
Figure 5 shows an example of expected voltage drops for a
specific case. VRef of 4.0 V is applied to VRHF and VRLF is
D1 = D2 = Hewlett Packard HP5712 or equivalent
SPT7852
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CALIBRATION
POWER SUPPLY SEQUENCING
CONSIDERATIONS
The SPT7852 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and offset
errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the
user.
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decoupling networks with large time constants which could delay
VDD power to the device.
Upon powerup, the SPT7852 begins its calibration algorithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 10bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10k clock cycles are required. This
results in a minimum calibration time upon powerup of 250
µsec (for a 20 MHz sample rate). Once calibrated, the
SPT7852 remains calibrated over time and temperature.
DIGITAL OUTPUTS, DATA VALID,
AND MSB INVERT
The output data for both channels can be latched using the
rising edge of Data Valid (DAV). Refer to table II for minimum data setup and hold times. The format of the data is
straight binary when the MSB Invert pin (MSBINV) is held
low and Two’s Complement format when MSB Invert is
high.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7852 to remain in calibration.
OVERRANGE OUTPUT
An OVERRANGE OUTPUT from D10A or D10B is an indication that the analog input signal has exceeded the positive full-scale input voltage by 1 LSB. When this condition
occurs, D10A/B will switch to logic 1. All other data outputs
(D0A/B to D9A/B) will remain at logic 1 as long as D10A/B
remains at logic 1. This feature makes it possible to include
the SPT7852 in higher resolution systems.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 7. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge conditions without degrading analog transition times.
Figure 7 – On-Chip Protection Circuit
Table III – Output Data Information (Binary Code)
VDD
120 Ω
Output Code
Output Code
Overrange (MSBINV=0)
(MSBINV=1)
Analog Input D10A/B
D9A/B–D0A/B
D9A/B–D0A/B
+FS + 1/2 LSB
1
11 1 1 1 1 1111
01 1 1 1 1 1 1 1 1
+FS – 1/2 LSB
0
1 1 1 1 1 1 1 1 1 Ø 01 1 1 1 1 1 1 1 Ø
[+FS –(–FS)]/2
0
ØØ ØØØØ ØØØØ ØØ ØØØØ ØØØØ
–FS + 1/2 LSB
0
00 0000 000Ø
10 0000 000Ø
–FS
0
00 0000 0000
10 0000 0000
Ø indicates the flickering bit between logic 0 and 1.
+FS = VRHS; –FS = VRLS
Analog
120 Ω
Pad
SPT7852
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PACKAGE OUTLINE
44-LEAD TQFP
A
INCHES
B
SYMBOL
Pin 1
Index
C
E
D
MIN
MILLIMETERS
MAX
MIN
MAX
A
0.472 Typ
12.00 Typ
B
0.394 Typ
10.00 Typ
C
0.394 Typ
10.00 Typ
D
0.472 Typ
12.00 Typ
E
0.031 Typ
F
0.012
0.017
0.300
0.45
G
0.035
0.040
0.85
1.05
H
0.002
0.006
0.05
0.15
0.030
0.450
0.750
0.80 Typ
I
0.018
J
0.039 Typ
1.00 Typ
K
0-7°
0-7°
F
G
K
I
H
J
SPT7852
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1/12/00
PIN FUNCTIONS
PIN ASSIGNMENTS
37
36
35
D7A
38
34
D8A
39
D5A
D9A
40
D6A
EN
D10A
41
43
42
44
GND
DVDD
OVDD
AVDD
VRHF
1
33
D4A
VRHS
2
32
D3A
VRLS
3
31
D2A
VRLF
4
30
D1A
GND
5
29
D0A
28
DAV
NAME
VRHF
VRHS
VRLS
VRLF
VCAL
VINA
VINB
AVDD
DVDD
OVDD
GND
CLK
VINA
6
GND
7
27
D0B
VINB
8
26
D1B
MSBINV
9
25
D2B
Reset
10
24
D3B
EN
VCAL
11
23
D4B
D0A – D9A
TOP VIEW
21
22
20
19
18
17
16
15
14
13
12
D0B – D9B
D5B
D7B
D6B
D8B
D9B
CLK
D10B
GND
OVDD
DVDD
AVDD
D10A
D10B
DAV
MSBINV
Reset
FUNCTION
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Channel A Analog Input
Channel B Analog Input
Analog Power Supply
Digital Power Supply
Digital Output Supply (3.3 V/5 V)
Common Device Ground
Input Clock (ƒCLK = 2 * ƒS)
Output Enable (Low = Data)
Channel A Tri-State Data Output
(D0A = LSB)
Channel B Tri-State Data Output
(D0B = LSB)
Channel A Overrange Bit
Channel B Overrange Bit
Data Valid Output
MSB Invert (High = 2’s complement)
(Low = binary)
Reset (Low = Normal) (High = Reset)
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
SPT7852SCT
0 to +70 °C
SPT7852SIT
–40 to +85 °C
SPT7852SCU
+25 °C
*Please see the die specification for guaranteed electrical performance.
PACKAGE TYPE
44L TQFP
44L TQFP
Die*
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
© Copyright 2002 Fairchild Semiconductor Corporation
SPT7852
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