Cypress CY7C187-15PXC 64k x 1 static ram Datasheet

CY7C187
64K x 1 Static RAM
Features
Functional Description
• High speed
The CY7C187 is a high-performance CMOS static RAM
organized as 65,536 words x 1 bit. Easy memory expansion is
provided by an active LOW Chip Enable (CE) and tri-state
drivers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
— 15 ns
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
— 495 mW
• Low standby power
— 110 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 22-pin (300-Mil)
Molded DIP and 24-pin (300-Mil) Molded SOJ
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location
specified on the address pin will appear on the data output
(DOUT) pin.
The output pin stays in high-impedance state when Chip
Enable (CE) is HIGH or Write Enable (WE) is LOW.
The CY7C187 utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
SOJ
Top View
DI
A0
A1
A2
A3
A4
A5
NC
A6
A7
SENSE AMPS
A12
A13
A14
A15
A0
A1
A2
A3
ROW DECODER
INPUT BUFFER
16K x 1
ARRAY
DO
CE
COLUMN DECODER
POWER
DOWN
DOUT
WE
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A15
A14
A13
A12
NC
A11
A10
A9
A8
DIN
CE
C187–3
WE
A4
A5
A6
A7
A8
A9
A10
A11
1
2
3
4
5
6
7
8
9
10
11
12
DIP
Top View
A0
A1
A2
A3
A4
A5
A6
A7
DOUT
WE
GND
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
A15
A14
A13
A12
A11
A10
A9
A8
DIN
CE
C187–2
C187–1
Selection Guide
-15
15
90
20
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05044 Rev. *A
•
198 Champion Court
•
-25
25
70
20
-35
35
70
20
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2006
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CY7C187
DC Input Voltage[1] .........................................–0.5V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 22 to Pin 11) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ............................................ –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0°C to +70°C
5V ± 10%
Electrical Characteristics Over the Operating Range
-15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0mA
VOL
Output LOW Voltage
VCC = Min., IOL =12.0 mA
VIH
Input HIGH Voltage
Voltage[1]
Min.
-25 and -35
Max.
2.4
Min.
Max.
Unit
2.4
0.4
V
0.4
V
2.2
VCC
2.2
VCC
V
–0.5
0.8
–0.5
0.8
V
VIL
Input LOW
IIX
Input Leakage Current
GND < VI < VCC
–5
+5
–5
+5
µA
IOZ
Output Leakage
Current
GND < VO < VCC,
Output Disabled
–5
+5
–5
+5
µA
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT = 0 mA
90
70
mA
ISB1
Automatic CE PowerDown Current[3]
Max. VCC, CE ≥ VIH
40
20
mA
ISB2
Automatic CE
Power-Down Current
Max. VCC, CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V
or VIN ≤ 0.3V
20
20
mA
Capacitance[4]
Parameter
Description
Input Capacitance
Output Capacitance
CIN
COUT
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
10
10
Unit
pF
pF
AC Test Loads and Waveforms
R1 329 Ω
ALL INPUT PULSES
R1 329 Ω
5V
OUTPUT
3.0V
5V
OUTPUT
R2 202 Ω
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2 202 Ω
5 pF
INCLUDING
JIG AND
SCOPE
GND
10%
90%
90%
10%
≤ 5 ns
≤ 5 ns
C187–5
(b)
C187–4
Equivalent to:
THÉ VENIN EQUIVALENT
125Ω
OUTPUT
1.90V
Notes:
1. VIL (min.) = –3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05044 Rev. *A
Page 2 of 9
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CY7C187
Switching Characteristics Over the Operating Range[5]
-15
Parameter
Description
Min.
-25
Max.
Min.
-35
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Output Hold from Address Change
tACE
CE LOW to Data Valid
3
3
CE HIGH to High Z
CE LOW to Power Up
tPD
25
CE HIGH to Power Down
35
25
8
0
35
10
ns
ns
15
0
20
ns
ns
5
0
15
ns
5
5
[6, 7]
tPU
35
5
15
CE LOW to Low Z
tHZCE
WRITE
15
[6]
tLZCE
25
ns
ns
20
ns
CYCLE[8]
tWC
Write Cycle Time
15
20
25
ns
tSCE
CE LOW to Write End
12
20
25
ns
tAW
Address Set-Up to Write End
12
20
25
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
12
15
20
ns
tSD
Data Set-Up to Write End
10
10
15
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z
5
tHZWE
WE LOW to High Z[7]
5
7
5
7
ns
10
ns
Switching Waveforms
Read Cycle No. 1[9, 10]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
C187–6
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device.
7. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = VIL.
Document #: 38-05044 Rev. *A
Page 3 of 9
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CY7C187
Switching Waveforms
Read Cycle No. 2[9, 11]
tRC
CE
tACE
tHZCE
tLZCE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
ICC
50%
50%
ISB
C187–7
Write Cycle No. 1(WE Controlled)[11]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tSD
DATA IN
DATA VALID
tHZWE
DATA OUT
tHD
tLZWE
HIGH IMPEDANCE
DATA UNDEFINED
C187–8
Note:
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05044 Rev. *A
Page 4 of 9
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CY7C187
Switching Waveforms
Write Cycle No. 2(CE Controlled)[11,13]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tHD
tSD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
C187–9
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
NORMALIZED I CC, I SB
1.2
I CC
1.0
0.8
0.6
0.4
0.0
4.0
4.5
5.0
I CC
0.8
0.6
0.4
VCC =5.0V
VIN =5.0V
0.2
ISB
0.2
1.0
5.5
ISB
0.0
–55
6.0
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.6
1.4
1.3
NORMALIZED t AA
NORMALIZED t AA
125
1.2
1.1
TA =25°C
1.0
1.4
1.2
1.0
VCC =5.0V
0.8
0.9
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE(V)
0.8
4.0
25
6.0
0.6
–55
25
125
AMBIENT TEMPERATURE (°C)
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT (mA)
NORMALIZED I CC, ISB
1.4
OUTPUT SOURCE CURRENT (mA)
Typical DC and AC Characteristics
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
VCC =5.0V
TA =25°C
80
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Note:
12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05044 Rev. *A
Page 5 of 9
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CY7C187
Typical DC and AC Characteristics (Continued)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
2.5
2.0
1.5
1.0
1.25
25.0
20.0
15.0
10.0
VCC =4.5V
TA =25°C
5.0
0.5
0.0
0.0
1.0
2.0
3.0
4.0
5.0
NORMALIZED I CC vs.CYCLE TIME
30.0
0.0
0
200
SUPPLY VOLTAGE(V)
400
600
NORMALIZED I CC
NORMALIZED t AA (ns)
NORMALIZED I
PO
3.0
800 1000
CAPACITANCE (pF)
VCC =5.0V
TA =25°C
VCC =0.5V
1.00
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Address Designators
Address
Name
Address
Function
Pin
Number
A0
X3
1
A1
X4
2
A2
X5
3
A3
X6
4
A4
X7
5
A5
Y7
6
A6
Y6
7
A7
Y2
8
A8
Y3
14
A9
Y1
15
A10
Y0
16
A11
Y4
17
A12
Y5
18
A13
X0
19
A14
X1
20
A15
X2
21
Truth Table
CE
WE
H
X
High Z
Deselect/Power-Down
L
H
Data Out
Read
L
L
Data In
Write
Document #: 38-05044 Rev. *A
Input/Output
Mode
Page 6 of 9
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CY7C187
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
Package
Type
Operating
Range
15
CY7C187-15PXC
51-85012
22-pin (300-Mil) Molded DIP (Pb-free)
Commercial
25
CY7C187-25PC
51-85012
22-pin (300-Mil) Molded DIP
Commercial
CY7C187-25VC
51-85030
24-pin (300-Mil) Molded SOJ
CY7C187-25VXC
35
24-pin (300-Mil) Molded SOJ (Pb-free)
CY7C187-35VXC
51-85030
24-pin (300-Mil) Molded SOJ (Pb-free)
Commercial
Package Diagrams
22-pin (300-Mil) PDIP (51-85012)
11
1
DIMENSIONS IN INCHES MIN.
MAX.
0.250
0.270
12
22
0.030
0.065
1.070
1.120
SEATING PLANE
0.120
0.140
0.140
0.190
0.115
0.160
0.015
0.060
0.090
0.110
0.280
0.325
0.055
0.065
0.015
0.020
0.009
0.012
3° MIN.
0.310
0.385
51-85012-*A
Document #: 38-05044 Rev. *A
Page 7 of 9
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CY7C187
Package Diagrams (Continued)
24-pin (300-mil) SOJ (51-85030)
PIN 1 ID
12
1
MIN.
DIMENSIONS IN INCHES[MM]
MAX.
REFERENCE JEDEC MO-088
0.291[7.39]
0.300[7.62]
0.330[8.38]
0.350[8.89]
PACKAGE WEIGHT 0.75gms
PART #
13
24
0.597[15.16]
0.613[15.57]
V24.3
STANDARD PKG.
VZ24.3
LEAD FREE PKG.
SEATING PLANE
0.120[3.05]
0.140[3.55]
0.007[0.17]
0.013[0.33]
0.004[0.10]
0.050[1.27]
TYP.
0.025[0.63] MIN.
0.262[6.65]
0.272[6.91]
0.013[0.33]
0.019[0.48]
51-85030-*B
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05044 Rev. *A
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C187
Document History Page
Document Title: CY7C187 64K x 1 Static RAM
Document Number: 38-05044
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107146
09/10/01
SZV
Change from Spec number: 38-00038 to 38-05044
*A
486744
See ECN
NXR
Removed 20 ns speed bin
Changed Low standby power from 220mW to 110mW
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Updated the Ordering Information Table
Document #: 38-05044 Rev. *A
Page 9 of 9
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