Cypress CY7C197BN-25PC 256-kb (256 k x 1) static ram fast access time: 15 n Datasheet

CY7C197BN
256-Kb (256 K × 1) Static RAM
256-Kb (256 K × 1) Static RAM
Features
General Description [1]
■
Fast access time: 15 ns
■
Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V)
■
CMOS for optimum speed and power
■
TTL compatible inputs and outputs
■
Available in 24-pin DIP and 24-pin SOJ
The CY7C197BN is a high performance CMOS Asynchronous
SRAM organized as 256 K × 1 bits that supports an
asynchronous memory interface. The device features an
automatic power down feature that significantly reduces power
consumption when deselected.
See the Truth Table on page 8 for a complete description of Read
and Write modes.
The CY7C197BN is available in 24-pin DIP and 24-pin SOJ
package(s).
Logic Block Diagram
Din
RAM Array
Sense Amps
Row Decoder
Input
Buffer
Dout
CE
Column
Decoder
WE
Power
Down
Circuit
x
A x
Product Portfolio
-15
-25
Unit
Maximum Access Time
Description
15
25
ns
Maximum Operating Current
150
95
mA
Maximum CMOS Standby Current
10
10
mA
Note
1. For best practice recommendations, refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06447 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 6, 2011
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CY7C197BN
Contents
Pin Layout and Specification ......................................... 3
Pin Description ................................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics .......................................... 4
Capacitance ...................................................................... 4
Thermal Resistance .......................................................... 4
AC Test Loads .................................................................. 5
AC Test Conditions .......................................................... 5
AC Electrical Characteristics .......................................... 6
Timing Waveforms ........................................................... 6
Read Cycle No. 1 ........................................................ 6
Read Cycle No. 2 ........................................................ 7
Write Cycle No. 1 (WE Controlled) .............................. 7
Write Cycle No. 2 (CE Controlled) ............................... 8
Document #: 001-06447 Rev. *C
Truth Table ........................................................................ 8
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagrams .......................................................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
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CY7C197BN
Pin Layout and Specification
24-pin DIP (6.6 × 31.8 × 3.5 mm)
A0
1
24
VCC
A1
2
23
A17
A2
3
22
A16
A3
4
21
A15
A4
5
20
A14
A5
6
19
A13
A6
7
18
A12
A7
8
17
A11
A8
9
16
A10
Dout
10
15
A9
WE
11
14
Din
GND
12
13
CE
24-pin SOJ (8 × 15 × 3.5 mm)
A0
1
24
VCC
A1
2
23
A17
A2
3
22
A16
A3
4
21
A15
A4
5
20
A14
A5
6
19
A13
A6
7
18
A12
A7
8
17
A11
A8
9
16
A10
Dout
10
15
A9
WE
11
14
Din
GND
12
13
CE
Pin Description
Pin
Type
Description
DIP
SOJ
AX
Input
Address Inputs
1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17,
18, 19, 20, 21, 22, 23
18, 19, 20, 21, 22, 23
CE
Control
Chip Enable
13
13
Din
Input
Data Input Pins
14
14
Dout
Output
Data Output Pins
10
10
VCC
Supply
Power (5.0 V)
24
24
WE
Control
Write Enable
11
11
Document #: 001-06447 Rev. *C
Page 3 of 13
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CY7C197BN
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
Exceeding the maximum rating may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage...............................................2001 V
(per MIL-STD-883, Method 3015)
Storage Temperature ............................... –65 °C to +150 °C
Latch Up Current .................................................... > 200 mA
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Operating Range
Range
Ambient
Temperature[3]
VCC
Commercial
0 °C to 70 °C
5.0 V ± 10%
Supply Voltage on VCC to Relative GND ......–0.5 V to +7.0 V
DC Voltage Applied to Outputs
in High Z State[2] .................................. –0.5 V to VCC + 0.5 V
DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics[2]
Parameter
Description
Condition
15 ns
25 ns
Min
Max
Min
Max
Unit
VIH
Input HIGH Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VIL
Input LOW Voltage
–0.3
0.8
–0.3
0.8
V
VOH
Output HIGH Voltage
VCC = Min, IOH = –4.0 mA
2.4
–
2.4
–
V
VOL
Output LOW Voltage
VCC = Min, lOL = 8.0 mA
–
0.4
–
0.4
V
IOZ
Output Leakage Current
GND  Vi  VCC, Output Disabled
–5
+5
–5
+5
µA
IIX
Input Leakage Current
GND  Vi  VCC
–5
+5
–5
+5
µA
ICC
VCC Operating Supply
Current
VCC = Max, IOUT = 0 mA,
f = FMAX = 1/tRC
–
150
–
95
mA
ISB1
Automatic CE Power Down
Current TTL Inputs
VCC = Max, CE  VIH, VIN  VIH or
VIN  VIL, f = FMAX
–
30
–
30
mA
ISB2
Automatic CE Power Down
Current CMOS Inputs
VCC = Max, CE  VCC – 0.3 V,
VIN  VCC – 0.3 V or VIN < 0.3 V,
f=0
–
10
–
10
mA
Capacitance[4]
Parameter
Description
Conditions
Max (ALL – PACKAGES)
Unit
CIN
Input Capacitance
8
pF
COUT
Output Capacitance
TA = 25 °C, f = 1 MHz,
VCC = 5.0 V
10
Thermal Resistance[4]
Parameter
Description
Conditions
24-pin DIP
24-pin SOJ
Unit
JA
Thermal Resistance
(Junction to Ambient)
75.69
84.15
°C/W
JC
Thermal Resistance
(Junction to Case)
Still Air, soldered on a 3 × 4.5
square inches, two-layer
printed circuit board
33.80
37.56
Notes
2. VIL(min) = –2.0 V for pulse durations of less than 20 ns.
3. TA is the “instant on” case temperature.
4. Tested initially and after any design or process change that may affect these parameters.
Document #: 001-06447 Rev. *C
Page 4 of 13
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CY7C197BN
AC Test Loads[5]
Output Loads
Output Loads
for tHZCE & tHZWE
R1
R3
VCC
VCC
Output
C1
R2
C2
(B)*
(A)*
All Input Pulses
Thevenin Equivalent
Output
RTH
R4
VCC
VTH
VSS
90%
90%
10%
10%
Rise Time
1 V/ns
Fall Time
1 V/ns
* including scope and jig capacitance
AC Test Conditions
Parameter
Description
Nom.
Unit
C1
Capacitor 1
30
pF
C2
Capacitor 2
5
R1
Resistor 1
480
R2
Resistor 2
255
R3
Resistor 3
480
R4
Resistor 4
255
RTH
Resistor Thevenin
167
VTH
Voltage Thevenin
1.73

V
Note
5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
Document #: 001-06447 Rev. *C
Page 5 of 13
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CY7C197BN
AC Electrical Characteristics[4, 6, 7, 8]
Parameter
15 ns
Description
25 ns
Min
Max
Min
Max
Unit
tRC
Read Cycle Time
15
–
25
–
ns
tAA
Address to Data Valid
–
15
–
25
ns
tOHA
Data Hold from Address Change
3
–
3
–
ns
tACE
CE to Data Valid
–
15
–
25
ns
tLZCE
CE to Low Z
3
–
3
–
ns
tHZCE
CE to High Z
–
5
–
11
ns
tPU
CE to Power-up
0
–
0
–
ns
tPD
CE to Power-down
–
15
–
20
ns
tWC
Write Cycle Time
15
–
25
–
ns
tSCE
CE to Write End
9
–
20
–
ns
tAW
Address Set-up to Write End
10
–
20
–
ns
tHA
Address Hold from Write End
0
–
0
–
ns
tSA
Address Set-up to Write Start
0
–
0
–
ns
tPWE
WE Pulse Width
9
–
20
–
ns
tSD
Data Set-Up to Write End
9
–
15
–
ns
tHD
Data Hold from Write End
0
–
0
–
ns
tHZWE
WE LOW to High Z
–
7
–
11
ns
tLZWE
WE HIGH to Low Z
2
–
3
–
ns
Timing Waveforms
Read Cycle No. 1 [9, 10]
tRC
Address
tAA
tOHA
Data Out
Previous Data Valid
Data Valid
Notes
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE for any given device.
7. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of
these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. tHZCE, tHZWE are specified as in part (b) of the AC Test Loads[5] on page 5. Transitions are measured ±200 mV from steady state voltage.
9. Device is continuously selected. CE = VIL.
10. WE is HIGH for Read Cycle.
Document #: 001-06447 Rev. *C
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CY7C197BN
Timing Waveforms (continued)
Read Cycle No. 2 [11, 12, 13]
tRC
Address
CE
tHZCE
tACE
tLZCE
High Z
Data Out
tPU
ICC
Vcc Supply Current
High Z
Data Valid
tPD
50%
50%
ISB
Write Cycle No. 1 (WE Controlled) [11, 14]
tWC
Address
tSCE
CE
tAW
tHA
tPWE
tSA
WE
tHD
tSD
Data
Valid
Data In
tLZWE
tHZWE
Data Out
Data
Undefined
High Impedance
Notes
11. Tested initially and after any design or process change that may affect these parameters.
12. WE is HIGH in read cycle.
13. Address valid prior to or coincident with CE transition LOW.
14. The minimum write cycle time is the sum of tHZWE and tSD.
Document #: 001-06447 Rev. *C
Page 7 of 13
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CY7C197BN
Timing Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[15, 16]
tWC
Address
tSCE
tSA
CE
tHA
tAW
tPWE
WE
tHD
tSD
Data In
Data Valid
High Z
Data Out
Truth Table
CE
WE
I/Ox
Mode
Power
H
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
Data Out
Read
Active (ICC)
L
L
Data In
Write
Active (ICC)
Notes
15. This cycle is CE controlled.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document #: 001-06447 Rev. *C
Page 8 of 13
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CY7C197BN
Ordering Information
Speed (ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
15
CY7C197BN-15VC
51-85030
24-pin SOJ (8 × 15 × 3.5 mm)
Commercial
25
CY7C197BN-25PC
51-85013
24-pin DIP (6.6 × 31.8 × 3.5 mm)
Commercial
Ordering Code Definitions
CY 7 C 1 97 BN - XX
X
C
Temperature Range:
C = Commercial
Package Type: XX = V or P
V = 24-pin SOJ
P = 24-pin DIP
Speed: XX = 15 ns or 25 ns
BN = 0.25 µm Technology
97 = 256-Kbit density with datawidth × 1 bit
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Please contact local sales representative regarding availability of these parts.
Document #: 001-06447 Rev. *C
Page 9 of 13
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CY7C197BN
Package Diagrams
Figure 1. 24-pin (300-mil) SOJ, 51-85030
51-85030 *C
Figure 2. 24-pin DIP (6.6 × 31.8 × 3.5 mm), 51-85013
51-85013 *C
Document #: 001-06447 Rev. *C
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CY7C197BN
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
CE
chip enable

ohms
DIP
dual in-line package
ns
nano seconds
SOJ
small outline J-lead
V
Volts
SRAM
static random access memory
µA
micro Amperes
TTL
transistor-transistor logic
mA
milli Amperes
WE
write enable
mm
milli meter
ms
milli seconds
MHz
Mega Hertz
pF
pico Farad
W
Watts
%
percent
°C
degree Celcius
Document #: 001-06447 Rev. *C
Symbol
Unit of Measure
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CY7C197BN
Document History Page
Document Title: CY7C197BN 256-Kb (256 K × 1) Static RAM
Document Number: 001-06447
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
901742
See ECN
NXR
New Data Sheet
*A
2892510
03/18/2010
VKN
Removed 12ns speed bin
Updated Ordering Information table
Updated Package Diagrams
Added Sales, Solutions, and Legal Information
*B
3108898
12/13/2010
AJU
Added Ordering Code Definitions.
*C
3217480
04/06/2011
PRAS
Document #: 001-06447 Rev. *C
Added Acronyms and Units of Measure.
Updated in new template.
Page 12 of 13
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-06447 Rev. *C
Revised April 6, 2011
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