Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage start-up circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, SG6741 is manufactured using the BiCMOS process, which allows operating current as low as 4mA. FEATURES High-voltage start-up Low operating current (4mA) Linearly decreasing PWM frequency to 22kHz Frequency hopping to reduce EMI emission Peak-current-mode control Cycle-by-cycle current limiting Leading-edge blanking Synchronized slope compensation Gate output maximum voltage clamp (18V) VDD over-voltage protection (auto restart) VDD under-voltage lockout (UVLO) Internal open-loop protection Constant power limit (full AC input range) APPLICATIONS General-purpose switch-mode power flyback power converters, including: supplies and Power adapters Open-frame SMPS DESCRIPTION The highly integrated SG6741 series of PWM controllers provides several features to enhance the performance of flyback converters. SG6741 integrates a frequency-hopping function that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal line compensation ensures constant output power limit over a wide range of AC input voltages, from 90VAC to 264VAC. SG6741 provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. PWM output is disabled until VDD drops below the UVLO lower limit; then the controller starts again. As long as VDD exceeds about 26V, the internal OVP circuit is triggered. SG6741 is available in an 8-pin DIP or SOP package. To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to TYPICAL APPLICATION © System General Corp. Version 1.2.1 (IAO33.0047.B2) -1- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller MARKING INFORMATION SG6741TP XXXXXXXXYWWV PIN CONFIGURATION T: S = SOP P: Z =Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location GND GATE FB VDD NC SENSE HV RI ORDERING INFORMATION Part Number Pb-Free SG6741SZ Package SOP-8 PIN DESCRIPTIONS Pin No. Symbol Function Description 1 GND Ground Ground. 2 FB Feedback The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin. 3 NC NA NC pin. 4 HV Start-up Input For start-up, this pin is pulled high to the line input or bulk capacitor via resistors. 5 RI Reference Setting A resistor connected from the RI pin to GND pin provides the SG6741 with a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor (RI) results in a 65kHz center PWM frequency. 6 SENSE Current Sense Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 7 VDD Power Supply Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the OVP trigger point. 8 GATE Driver Output The totem-pole output driver. Soft driving waveform is implemented for improved EMI. © System General Corp. Version 1.2.1 (IAO33.0047.B2) -2- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller BLOCK DIAGRAM © System General Corp. Version 1.2.1 (IAO33.0047.B2) -3- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VDD Supply Voltage 30 V VHV Input Voltage to HV Pin 500 V VL Input Voltage to FB, SENSE, Pin -0.3 to 7 PD Power Dissipation, TA < 50°C V DIP 800 mW SOP 400 mW DIP 82.5 °C/W SOP 141 °C/W RΘJA Thermal Resistance, Junction-to-Air TJ Operating Junction Temperature -40 to +125 °C TSTG Storage Temperature Range -55 to +150 °C TL Lead Temperature (Wave soldering or IR, 10 seconds) 260 °C ESD Electrostatic Discharge Capability, Human Body Model (All pins except HV pin) 3 KV Electrostatic Discharge Capability, Machine Model (All pins except HV pin) V 250 *All voltage values, except differential voltages, are given with respect to the GND pin. *Stresses above those listed may cause permanent damage to the device. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit TA Operating Ambient Temperature -20 to +85 °C *For proper operation ELECTRICAL CHARACTERISTICS 12V ≤ VDD ≤ 25V; -20°C ≤ TA ≤ 85°C, unless otherwise noted. VDD Section Symbol Parameter VDD-OP Continuously Operating Voltage Test Condition Min. Typ. Max. Unit 22 V VDD-ON Start Threshold Voltage 15.5 16.5 17.5 V VDD-OFF Minimum Operating Voltage 9.5 10.5 11.5 V IDD-ST Start-up Current VDD-ON – 0.16V 30 µA IDD-OP Operating Supply Current VDD = 15V, GATE open 4 5 mA IDD-OLP Internal Sink Current VDD-OLP +0.1V µA VDD-OLP IDD-OLP Off Voltage VDD-OVP VDD Over-Voltage Protection tD-VDDOVP VDD Over-Voltage-protection Debounce Time (Auto Restart) (Auto Restart) 50 70 90 6.5 7.5 8.0 V 25 26 27 V 100 180 260 µs Min. Typ. Max. Unit HV Section Symbol Parameter IHV Supply Current Drawn from Pin HV IHV-LC Leakage Current After Start-up © System General Corp. Version 1.2.1 (IAO33.0047.B2) Test Condition VAC=90V(VDC=120V)； VDD=0V With Auxiliary Supply HV = 500V, VDD = 15V -4- 2 1 mA 20 µA www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller Oscillator Section Symbol FOSC Parameter Frequency in Nominal Mode tHOP Hopping Period FOSC-G Green-Mode Frequency FDV Frequency Variation vs. VDD Deviation FDT Frequency Variation vs. Temp. Deviation Test Condition Min. Typ. Max. Center Frequency 62 65 68 Hopping Range ±3.7 ±4.2 ±4.7 4.4 18 22 Unit kHz ms 25 kHz VDD=11V to 22V 5 % TA=-20 to 85℃ 5 % Feedback Input Section Symbol Parameter Min. Typ. Max. Unit AV Input Voltage to Current-Sense Attenuation Test Condition 1/3.75 1/3.20 1/2.75 V/V ZFB Input Impedance 4 VFB-OPEN FB Output High Voltage FB Pin Open VFB-OLP FB Open-Loop Trigger Level tD-OLP Delay Time, FB Pin Open-Loop Protection VFB-N Green-Mode Entry FB Voltage VFB-G Green-Mode Ending FB Voltage RI=26kΩ 7 5.5 kΩ V 3.7 4.0 4.3 V 50 56 62 ms 2.1 2.3 V 1.9 VFB-N -0.5 V PWM Frequency FOSC FOSC-G VFB-G VFB VFB-N Current-Sense Section Symbol Parameter ZSENSE Input Impedance VSTHFL Current Limit Flatten Threshold Voltage VSTHVA Current Limit Valley Threshold Voltage tPD Delay to Output tLEB Leading-Edge Blanking Time VS-SCP Threshold Voltage for SENSE Short-Circuit Protection tD-SSCP Delay Time for SENSE Short-Circuit Protection © System General Corp. Version 1.2.1 (IAO33.0047.B2) Test Condition Min. Typ. 0.87 0.90 Max. Unit 0.93 V 12 VSTHFL–VSTHVA 0.18 275 VSENSE<0.15V, RI=26kΩ -5- KΩ 0.22 0.26 V 100 200 ns 350 425 ns 0.15 V 180 µs www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller Gate Section Symbol Parameter DCYMAX Maximum Duty Cycle VGATE-L Gate Low Voltage VDD=15V, IO=50mA VGATE-H Gate High Voltage VDD=12.5V, IO=50mA 8 tr Gate Rising Time VDD=15V, CL=1nF 150 tf Gate Falling Time VDD=15V, CL=1nF 30 IGATE-SOURCE Gate Source Current VDD=15V, GATE=6V 250 VGATE-CLAMP Gate Output Clamping Voltage VDD=22V © System General Corp. Version 1.2.1 (IAO33.0047.B2) Test Condition -6- Min. Typ. Max. 60 65 70 Unit % 1.5 V 250 350 ns 50 90 ns 18 V V mA www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller TYPICAL CHARACTERISTIC Operating Supply Current (IDD-OP) vs Temperature 5.0 20 4.0 IDD-OP (mA) IDD-ST (uA) Start-up Current (IDD-ST) vs Temperature 25 15 10 5 3.0 2.0 1.0 0 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (℃) 50 65 80 95 110 125 Minimum Operating Voltage (VDD-OFF) vs Temperature 13.0 20.0 12.0 VDD-OFF (V) 19.0 18.0 17.0 11.0 10.0 9.0 16.0 8.0 15.0 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 110 125 Temperature (℃) Temperature (℃) HV pin Leakage Current after Start-up (IHV-LC) vs Temperature Supply current drawn from pin HV (IHV) vs Temperature 5.0 10 4.0 8 3.0 6 IHV-LC (uA) IHV (mA) 35 Temperature (℃) Start Threshold Voltage (VDD-ON) vs Temperature VDD-ON (V) 20 2.0 1.0 4 2 0.0 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 © System General Corp. Version 1.2.1 (IAO33.0047.B2) -40 -25 -10 5 20 35 50 65 80 95 Tem perature (℃ ) Temperature (℃) -7- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product Specification SG6741 Highly-Integrated Green-Mode PWM Controller Maximum Duty Cycle (DCYMAX) vs Temperature 70.0 68 68.0 DCYMAX (%) FOSC (kHz) Frequency in nominal mode (FOSC) vs Temperature 70 66 64 66.0 64.0 62.0 62 60.0 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (℃) Temperature (℃) . © System General Corp. Version 1.2.1 (IAO33.0047.B2) -8- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product specification SG6741 Highly-Integrated Green-Mode PWM Controller Operation Description Current Sensing / PWM Current Limiting Start-up Current Peak-current-mode control is utilized in SG6741 to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and VFB, the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB–1.2)/3.2, the switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit. For start-up, the HV pin is connected to the line input or bulk capacitor through an external resistor, RHV, which is recommended as 100KΩ. Typical start-up current drawn from pin HV is 2mA and it charges the hold-up capacitor through the resistor RHV. When the VDD capacitor level reaches VDD-ON, the start-up current switches off. At that moment, the VDD capacitor only supplies the SG6741 to maintain the VDD before the auxiliary winding of the main transformer to carry on provide the operating current. Operating Current Operating current is around 4mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. Green-Mode Operation The patented green-mode function provides an off-time modulation to reduce switching frequency in light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. VFB, which is derived from the voltage feedback loop, is used as the reference. Once VFB is lower than the threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency, around 22KHz (RI=26KΩ). Oscillator Operation A resistor connected from the RI pin to GND generates a constant current source for the SG6741 controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor, RI, results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is: fPWM = 1690 RI (KΩ ) (KHz) --------------------- (1) Leading-Edge Blanking Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Under-Voltage Lockout (UVLO) The turn-on and turn-off thresholds are fixed internally at 16.5V/10.5V. During start-up, the hold-up capacitor must be charged to 16.5V through the start-up resistor so that IC is enabled. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10.5V during this start-up process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during start-up. Gate Output / Soft Driving The SG6741 BiCMOS output stage is a fast totem pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over-voltage. A soft driving waveform is implemented to minimize EMI. The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz. © System General Corp. Version 1.2.1 (IAO33.0047.B2) -9- www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product specification SG6741 Highly-Integrated Green-Mode PWM Controller Built-in Slope Compensation Limited Power Control The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6741 inserts a synchronized positive-going ramp at every switching cycle. The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. Constant Output Power Limit When the SENSE voltage, across the sense resistor RS, reaches the threshold voltage around 0.9V, the output GATE drive is turned off after a small delay, tPD. This delay introduces an additional current, proportional to tPD • VIN / LP. The delay is nearly constant, regardless of the input voltage VIN. Higher input voltage results in a larger additional current and the output power limit is also higher than that under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal and is fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. When VDD goes below the turn-off threshold (eg, 10.5V) the controller totally shuts down. VDD is charged up to the turn-on threshold voltage of 16V through the start-up resistor until PWM output is restarted. This protection is activated as long as the overloading condition persists. This prevents the power supply from overheating. Noise Immunity Noise on the current sense or control signal may cause significant pulse width jitter, particularly in the continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near to the SG6741, and increasing the power MO gate resistance improves performance. VDD Over-Voltage Protection VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. Once the VDD voltage is over the VDD over-voltage protection voltage (VDD-OVP), and lasts for tD-VDDOVP, the PWM pulses is disabled until the VDD voltage drops below the UVLO, then starts up again. Over-voltage conditions are usually caused by open feedback loops. © System General Corp. Version 1.2.1 (IAO33.0047.B2) - 10 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product specification SG6741 Highly-Integrated Green-Mode PWM Controller REFERENCE CIRCUIT 2 CIRCUIT (12V/5A) R2 1 2 3 4 T1 C6 1 VZ1 C1 4 C2 1 4 T2 8 2 Q1 L4 VO+ 2 VO+ + C7 L2 D1 C8 2 3 1 7 1 3 D2 1 1 + 4 1 1 2 6 2 1 C3 C4 5 R1 C5 2 3 + 2 3 1 3 2 3 1 CN1 2 L1 4 2 BD1 CN1 2 VO- 2 R3 R4 Q2 3 1 D3 2 2 1 2 3 GATE FB VDD NC SENSE HV RI 8 7 R5 6 5 R6 C10 R7 4 4 GND C9 U2 R8 1 1 C12 SG6741 1 U1 + K 2 3 R9 VO+ R10 C11 R A U3 R11 BOM Reference Component Reference Component BD1 BD 4A/600V Q2 MOS 7A/600V C1 XC 0.68µF/300V R1 R 100Kohm 1/2W C2 XC 0.1µF/300V R2 R 47ohm 1/4W C3 YC 222pF/Y1 R3 R 100Kohm 1/2W C4 EC 120µF/400V R4 R 20ohm 1/8W C5 CC 0.01µF/500V R5 R 100ohm 1/8W C6 CC 102pF/100V R6 R 33Kohm 1/8W C7 EC 1000µF/25V R7 R 0.3ohm 2W C8 EC 470µF/25V R8 R 680ohm 1/8W C9 EC 22µF/50V R9 R 4.7Kohm 1/8W C10 CC 470pF/50V R10 R 150Kohm 1/8W C11 CC 222pF/50V R11 R 39Kohm 1/8W C12 CC 103pF/50V T1 10mH D1 Zener Diode 15V 1/2W (option) T2 600µH(PQ2620) D2 BYV95C U1 IC SG6741 D3 FR103 U2 IC PC817 F1 FUSE 4A/250V U3 IC TL431 L1 900µH VZ1 VZ 9G Q1 STP20-100CT © System General Corp. Version 1.2.1 (IAO33.0047.B2) - 11 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product specification SG6741 Highly-Integrated Green-Mode PWM Controller PACKAGE INFORMATION 8PINS-SOP(S) 8 C 5 H E F 1 4 b e D Θ A1 L A Dimensions Symbol Millimeter Min. Typ. Max. Inch Min. A A1 b c D E e F H L θ˚ 1.346 0.101 1.752 0.254 0.053 0.004 0.406 0.203 4.648 3.810 1.016 5.791 0.406 0° © System General Corp. Version 1.2.1 (IAO33.0047.B2) 1.270 0.381X45° Typ. Max. 0.069 0.010 0.016 0.008 4.978 3.987 1.524 0.183 0.150 0.040 6.197 1.270 8° 0.228 0.016 0° - 12 - 0.050 0.015X45° 0.196 0.157 0.060 0.244 0.050 8° www.sg.com.tw • www.fairchildsemi.com September 19, 2007 Product specification SG6741 Highly-Integrated Green-Mode PWM Controller © System General Corp. Version 1.2.1 (IAO33.0047.B2) - 13 - www.sg.com.tw • www.fairchildsemi.com September 19, 2007