Renesas HD74LS259 8-bit address latch Datasheet

HD74LS259
8-bit Address Latch
REJ03D0471–0200
Rev.2.00
Feb.18.2005
This 8-bit addressable latch is designed for general purpose storage applications in digital systems. Specific uses
include working registers, serial-holding registers, and active-high decoders or demultiplexers. This is multifunctional
device capable of storing single-line data in eight addressable latches, and being a 1-to-8 decoder or demultiplexer with
active-high outputs.
Four distinct modes of operation are selectable by controlling the clear and enable inputs as enumerated in the function
table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch.
The addressed latch will follow the data input with all unaddressed latches remaining in their previous states. In the
memory mode, latch remains in their previous states and is unaffected by the data or address inputs.
To eliminate the possibility of entering erroneous data in the latch, the enable should be held high (inactive) while the
address lines are changing.
In the clear mode, all outputs are low and unaffected by the address and data inputs.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS259P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
—
—
HD74LS259FPEL
SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
EL (2,000 pcs/reel)
PRSP0016DG-A
RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
HD74LS259RPEL
SOP-16 pin (JEDEC)
Rev.2.00, Feb.18.2005, page 1 of 7
EL (2,500 pcs/reel)
HD74LS259
Pin Arrangement
A
1
16
VCC
A
Latch
Select
B
2
B
CLR
15
Clear
C
3
C
G
14
Enable
Q0
4
Q0
D
13
Data Input
Q1
5
Q1
Q7
12
Q7
Q2
6
Q2
Q6
11
Q6
Q3
7
Q3
Q5
10
Q5
GND
8
9
Q4
Outputs
Outputs
Q4
(Top view)
Function Table
Input
CLR
H
H
L
L
G
L
H
L
H
Output of
addressed latch
Each other output
Function
D
Qio
D
L
Qio
Qio
L
L
Addressable latch
Memory
8-line demultiplexer
Clear
Select inputs
Latch addressed
C
B
A
L
L
L
0
L
L
H
1
L
H
L
2
L
H
H
3
H
L
L
4
H
L
H
5
H
H
L
6
H
H
H
7
Notes: 1. H; high level, L; low level
2. D; the level at the data input
3. Oio; the level of Qi (i = 0, 1, … 7, as appropriate) before the indicated steady state input conditions were
established.
Rev.2.00, Feb.18.2005, page 2 of 7
HD74LS259
Block Diagram
G
D
A
Q1
Q0
B
C
Q2
Clear
Q3
Q4
Q5
Q6
Q7
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage
Item
VCC
7
V
Input voltage
VIN
7
V
PT
400
mW
Tstg
–65 to +150
°C
Power dissipation
Storage temperature
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Pulse width
Setup time
Hold time
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.00
5.25
V
IOH
—
—
–400
µA
IOL
—
—
8
mA
Topr
–20
25
75
°C
tw
15
—
—
ns
Data
tsu
20↑
—
—
ns
Address
tsu
20↑
—
—
ns
Data
th
0↑
—
—
ns
Address
th
0↑
—
—
ns
Rev.2.00, Feb.18.2005, page 3 of 7
HD74LS259
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
VIH
VIL
min.
2.0
—
typ.*
—
—
max.
—
0.8
Unit
V
V
VOH
2.7
—
—
V
—
—
—
—
—
–20
—
—
—
—
0.4
0.5
20
–0.4
0.1
–100
36
–1.5
Output voltage
VOL
IIH
IIL
Input current
II
Short-circuit output current
IOS
—
Supply current**
ICC
22
Input clamp voltage
VIK
—
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with all outputs open and all inputs grounded.
V
µA
mA
mA
mA
mA
V
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
IOL = 4 mA VCC = 4.75 V, VIH = 2 V,
IOL = 8 mA VIL = 0.8 V
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 7 V
VCC = 5.25 V
VCC = 5.25 V
VCC = 4.75 V, IIN = –18 mA
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Propagation delay time
Symbol
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Rev.2.00, Feb.18.2005, page 4 of 7
Inputs
Clear
Output
Q0 to Q7
Data
Q0 to Q7
Address
Q0 to Q7
Enable
Q0 to Q7
min.
—
—
—
—
—
—
—
typ.
17
20
13
24
18
22
15
max.
27
32
21
38
29
35
24
Unit
ns
Condition
ns
ns
ns
CL = 15 pF,
RL = 2 kΩ
HD74LS259
Testing Method
Test Circuit
VCC
Output
4.5V
RL
Load circuit 1
Q0
CL
G
P.G.
Zout = 50Ω
Input
P.G.
Zout = 50Ω
See Function Table
Input
Output
Q1
A
Same as Load Circuit 1.
Output
B
Q2
C
D
Same as Load Circuit 1.
Output
Q3
Same as Load Circuit 1.
Output
Clear
Q4
Same as Load Circuit 1.
Output
Q5
Same as Load Circuit 1.
Output
Q6
Same as Load Circuit 1.
Output
Q7
Notes:
Same as Load Circuit 1.
1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Waveform
tTLH
tTHL
90%
1.3 V
Input
3V
90%
1.3 V
10%
10%
0V
tPHL
tPLH
VOH
In phase output
1.3 V
1.3 V
VOL
tPHL
tPLH
VOH
Out of phase output
1.3 V
1.3 V
VOL
Note:
Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
Rev.2.00, Feb.18.2005, page 5 of 7
HD74LS259
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
θ
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
bp
e
Dimension in Millimeters
Min
9
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
bp
Nom
D
10.06
E
5.50
Max
10.5
A2
8
e
Dimension in Millimeters
Min
x
A1
M
0.00
0.10
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
0.20
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
0.80
Z
L
L
Rev.2.00, Feb.18.2005, page 6 of 7
8°
0.50
1
0.70
1.15
0.90
HD74LS259
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
16
9
c
*2
Index mark
HE
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
9.90
10.30
E
3.95
A2
8
1
Z
e
*3
bp
x
A1
0.10
0.14
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
A
M
L1
0.25
1.75
bp
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
5.80
e
1.27
x
0.25
y
0.15
0.635
Z
L
L
Rev.2.00, Feb.18.2005, page 7 of 7
8°
0.40
1
0.60
1.08
1.27
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