Dallas DS4402 Two/four-channel, i2c adjustable current dac Datasheet

Rev 0; 4/06
Two/Four-Channel, I2C Adjustable Current DAC
The DS4402 and DS4404 contain two and four I2C*
adjustable current DACs, respectively, that are each
capable of sinking or sourcing current. Each output has
31 sink and 31 source settings that are programmed by
the I2C interface. External resistors set the full-scale
range and step size of each output.
Applications
Power-Supply Adjustment
Power-Supply Margining
Adjustable Current Sink or Source
Pin Configuration
Features
♦ Two (DS4402) or Four (DS4404) Current DACs
♦ Full-Scale Range for Each DAC Determined by
External Resistors
♦ 31 Settings Each for Sink and Source Modes
♦ I2C-Compatible Serial Interface
♦ Two Three-Level Address Pins Allow Nine
Devices on Same I2C Bus
♦ Low Cost
♦ Small Package (14-Pin TDFN)
♦ -40°C to +85°C Temperature Range
♦ 1.7V to 5.5V Operation
Ordering Information
TOP VIEW
1
SCL
2
+
SDA
14
OUT3
(N.C.)
13
VCC
OUT2
(N.C.)
GND
FS3
(N.C.)
FS2
(N.C.)
3
12
4
11
A1
10
OUT1
FS1
6
9
A0
FS0
7
8
OUT0
DS4404/
DS4402
5
PART
TEMP RANGE
PIN-PACKAGE
DS4402N+
-40°C to +85°C
14 TDFN (3mm x 3mm)
DS4402N+T&R
-40°C to +85°C
14 TDFN (3mm x 3mm)
DS4404N+
-40°C to +85°C
14 TDFN (3mm x 3mm)
DS4404N+T&R
-40°C to +85°C
14 TDFN (3mm x 3mm)
+Denotes lead-free package.
T&R denotes tape-and-reel package.
TDFN
(3mm x 3mm x 0.8mm)
( ) INDICATES FOR DS4402 ONLY.
Typical Operating Circuit
VCC
VOUT0
VOUT1
4.7kΩ
4.7kΩ
OUT
VCC
SDA
SCL
DC/DC
CONVERTER
DS4402
A1
OUT0
A0
GND
R0A
FB
DC/DC
CONVERTER
R1A
FB
OUT1
R0B
FS0
RFS0
OUT
R1B
FS1
RFS1
*Purchase of I2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C
Standard Specification as defined by Philips.
______________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS4402/DS4404
General Description
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VCC, SDA, and SCL
Relative to Ground.............................................-0.5V to +6.0V
Voltage Range on A0, A1, FS0, FS1, FS2, FS3,
OUT0, OUT1, OUT2, and OUT3 Relative to
Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.)
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature .....................................Refer to IPC/JEDEC
J-STD-020 Specification
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
(Note 1)
MIN
TYP
MAX
UNITS
2.7
5.5
V
Supply Voltage
VCC
Input Logic 1 (SDA, SCL, A0, A1)
VIH
0.7 x
VCC
VCC +
0.3
V
Input Logic 0 (SDA, SCL, A0, A1)
VIL
-0.3
0.3 x
VCC
V
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
Supply Current
ICC
VCC = 5.5V
(Note 2)
Input Leakage (SDA, SCL)
IIL
VCC = 5.5V
Output Leakage (SDA)
IL
Output Current Low (SDA)
Address Input Resistors
Reference Voltage
IOL
MIN
TYP
DS4402
500
DS4404
500
VOL = 0.4V
3
VOL = 0.6V
6
µA
1
µA
1
µA
mA
RIN
240
kΩ
VREF
1.23
V
OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
MAX
UNITS
Output Voltage for Sinking Current
VOUT:SINK
(Note 3)
0.5
VCC
V
VOUT:SOURCE
(Note 3)
0
VCC 0.5
V
IOUT:SINK
(Note 3)
0.5
2.0
mA
IOUT:SOURCE
(Note 3)
-2.0
-0.5
mA
5.0
%
Output Voltage for Sourcing
Current
Full-Scale Sink Output Current
Full-Scale Source Output Current
CONDITIONS
MIN
TYP
Output-Current Full-Scale
Accuracy
IOUT:FS
+25°C, VCC = 4.0V; using ideal RFS resistor
2.5
Output-Current Temperature Drift
IOUT:TC
(Note 4)
70
2
______________________________________________________________________
ppm/°C
Two/Four-Channel, I2C Adjustable Current DAC
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
Output-Current Power-Supply
Rejection Ratio
Output Leakage Current at Zero
Current Setting
CONDITIONS
MIN
DC
TYP
MAX
0.33
IZERO
-1
UNITS
%/V
+1
µA
Output-Current Differential
Linearity
DNL
(Note 5)
0.5
LSB
Output-Current Integral Linearity
INL
(Note 6)
1
LSB
MAX
UNITS
400
kHz
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER
SYMBOL
CONDITIONS
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD:STA
0.6
µs
tLOW
1.3
µs
High Period of SCL
0
TYP
fSCL
Low Period of SCL
(Note 7)
MIN
SCL Clock Frequency
tHIGH
0.6
Data Hold Time
tDH:DAT
0
Data Setup Time
tSU:DAT
100
ns
START Setup Time
tSU:STA
0.6
µs
SDA and SCL Rise Time
tR
(Note 8)
20 +
0.1CB
300
ns
SDA and SCL Fall Time
tF
(Note 8)
20 +
0.1CB
300
ns
STOP Setup Time
SDA and SCL Capacitive Loading
tSU:STO
CB
µs
0.9
0.6
(Note 8)
µs
µs
400
pF
Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs (except A1 and A0, which can be open) driven
to well-defined logic levels. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current
including IRFS is ICC + (2 x IRFS).
Note 3: The output-voltage full-scale current ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Temperature drift excludes drift caused by external resistor.
Note 5: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 31.
Note 6: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 7: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 8: CB—total capacitance of one bus line in pF.
_____________________________________________________________________
3
DS4402/DS4404
OUTPUT CURRENT CHARACTERISTICS (continued)
Two/Four-Channel, I2C Adjustable Current DAC
DS4402/DS4404
Pin Description
PIN
NAME
FUNCTION
DS4404
DS4402
1
1
SDA
I2C Serial Data. Input/output for I2C data.
2
2
SCL
I2C Serial Clock. Input for I2C clock.
3
3
GND
Ground
4
—
FS3
5
—
FS2
6
6
FS1
7
7
FS0
Full-Scale Calibration Input. A resistor to ground on these pins determines the full-scale
current for each output. FS0 controls OUT0, FS1 controls OUT1, etc. (DS4402 has only
two inputs: FS0 and FS1.)
8
8
OUT0
10
10
OUT1
12
—
OUT2
14
—
OUT3
9, 11
9, 11
A0, A1
13
13
VCC
—
4, 5, 12, 14
N.C.
—
—
EP
Current Output. Sinks or sources the current determined by the I2C interface and the
resistance connected to FSx. (DS4402 has only two outputs: OUT0 and OUT1.)
Address Select Inputs. Tri-level inputs (VCC, GND, N.C.) determine the I2C slave address.
See the Detailed Description section for the nine available device addresses.
Power Supply
No Connection
Exposed Pad. Leave floating or connect to GND.
SDA SCL
VCC
A1
A0
I2C-COMPATIBLE
SERIAL INTERFACE
DS4402/DS4404
VCC
F8h
F9h
SOURCE OR
SINK MODE
CURRENT
DAC0
GND
FS0
RFS0
OUT0
FBh
FAh
31-POSITIONS
EACH FOR SINK
AND SOURCE
MODE
CURRENT
DAC1
FS1
RFS1
CURRENT
DAC3
CURRENT
DAC2
OUT1
FS2
OUT2
RFS2
FS3
OUT3
RFS3
DS4404
Figure 1. Functional Diagram
4
______________________________________________________________________
Two/Four-Channel, I2C Adjustable Current DAC
The DS4402/DS4404 contain two/four I2C adjustable
current sources (Figure 1) that are each capable of
sinking and sourcing current. Each output has 31 sink
and 31 source settings that are programmed through
the I 2C interface. The full-scale ranges (and corresponding step sizes) of the outputs are determined by
external resistors that adjust the output currents over a
4:1 range. The formula to determine the external resistor values (RFS) for each of the outputs is given by:
Equation 1:
RFS = (VREF / IFS) x (31 / 4)
where IFS = desired full-scale current
On power-up, the DS4402/DS4404 output zero current.
This is done to prevent it from sinking or sourcing an
incorrect current before the system host controller has
had a chance to modify the device’s setting.
As a source for biasing instrumentation or other circuits, the DS4402/DS4404 provide a simple and inexpensive current source with an I2C interface for control.
The adjustable full-scale range allows the application to
get the most out of its 5-bit sink or source resolution.
When used in adjustable power-supply applications
(see the Typical Operating Circuit), the DS4402/DS4404
do not affect the initial power-up supply voltage because
it defaults to providing zero output current on power-up.
As it sources or sinks current into the feedback voltage
node, it changes the amount of output voltage required
by the regulator to reach its steady state operating point.
By using the external resistor to set the output current
range, the devices provide flexibility for adjusting the
impedances of the feedback network or the range over
which the power supply can be controlled or margined.
I2C Slave Address
The DS4402/DS4404 respond to one of nine I2C slave
addresses determined by the two tri-level address
inputs. The three input states are connected to V CC,
connected to ground, or disconnected. To sense the
disconnected state (Figure 2), the address inputs have
weak internal resistors that pull the pins to mid-supply.
DS4402/DS4404
Detailed Description
VCC
RIN
RIN
I2C
ADDRESS
DECODE
A1
A0
RIN
RIN
Figure 2. I2C Address Inputs
Table 1 lists the slave address determined by the
address input combinations.
Table 1. Slave Addresses
SLAVE ADDRESS
(HEXADECIMAL)
A1
A0
GND
GND
90h
GND
VCC
92h
VCC
GND
94h
VCC
VCC
96h
N.C.
GND
98h
N.C.
VCC
9Ah
GND
N.C.
9Ch
VCC
N.C.
9Eh
N.C.
N.C.
A0h
_____________________________________________________________________
5
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
Memory Organization
To control the DS4402/DS4404’s current sources, write
to the memory addresses listed in Table 2.
Table 2. Memory Addresses
MEMORY ADDRESS
(HEXADECIMAL)
CURRENT SOURCE
F8h
OUT0
F9h
OUT1
FAh*
OUT2*
FBh*
OUT3*
*Only for DS4404.
The format of each output control register is given by:
MSB
LSB
S
X
X
D4
D3
D2
D1
D0
Where:
BIT
NAME
S
Sign Bit
X
Reserved
DX
Data
FUNCTION
POWER-ON
DEFAULT
Determines if DAC sources
or sinks current. For sink
S = 0, for source S = 1.
0b
Reserved. Both bits read
zero.
00b
5-Bit Data Word Controlling
DAC Output. Setting 00000b
outputs zero current
regardless of the state of the
sign bit.
00000b
Example: IFS0 = 800µA, and register F8h is written to a
value of 92h. Calculate the value of external resistance
required, and the magnitude of the output current with
this register setting.
RFS = (VREF / 800µA) x (31 / 4) = 11.9kΩ
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 12h (18
decimal). The magnitude of the output current is equal to:
800µA x (18 / 31) = 465µA
6
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers:
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition. See Figure 3 for
applicable timing.
STOP Condition: A STOP condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high generates
a STOP condition. See Figure 3 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal
START condition. See Figure 3 for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL, plus the
setup and hold time requirements (Figure 3). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time (Figure 3) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses, including when it is reading bits from
the slave.
______________________________________________________________________
Two/Four-Channel, I2C Adjustable Current DAC
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to terminated communication so the slave will return control
of SDA to the master.
Slave Address Byte: Each slave on the I 2 C bus
responds to a slave address byte sent immediately following a START condition. The slave address byte contains
the slave address in the most significant 7 bits and the
R/W bit in the least significant bit. The DS4402/DS4404s’
slave address is determined by the state of the A0 and A1
address pins. Table 1 describes the addresses corresponding to the state of A0 and A1.
When the R/W bit is 0 (such as in A0h), the master is
indicating it will write data to the slave. If R/W = 1 (A1h
in this case), the master is indicating it wants to read
from the slave. If an incorrect slave address is written,
the DS4402/DS4404 assume the master is communicating with another I2C device and ignore the communication until the next START condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte transmitted during a write operation following the slave
address byte.
I2C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and generate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tSU:STO
tHD:DAT
NOTE: TIMING IS REFERENCE TO VIL(MAX) AND VIH(MIN).
Figure 3. I2C Timing Diagram
_____________________________________________________________________
7
DS4402/DS4404
Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a
NACK by transmitting a one during the ninth bit. Timing
for the ACK and NACK is identical to all other bit writes
(Figure 4). An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of information
transferred from the master to the slave (most significant
bit first) plus a 1-bit acknowledgement from the slave to
the master. The 8 bits transmitted by the master are
done according to the bit-write definition, and the
acknowledgement is read using the bit-read definition.
DS4402/DS4404
Two/Four-Channel, I2C Adjustable Current DAC
Changing the address select inputs resets the I2C interface. This function aborts the current transaction and puts
the SDA driver into a high-impedance state. This hardware reset function should never be required because it
is achievable through software, but it does provide an
alternative way of resetting the I2C interface, if needed.
Application Information
Example Calculations
for an Adjustable Power Supply
Using the typical circuit, assuming a typical output voltage of 2.0V, a feedback voltage of 0.8V, R1 = 500Ω,
and R2 = 333Ω, to adjust or margin the supply 20%
requires a full-scale current equal to [(0.2 x 2.0V) /
500Ω = 800µA]. Using Equation 1, RFS can be calculated [RFS = (VREF / 800µA) x (31 / 4) = 11.9kΩ]. The current DAC in this configuration allows the output voltage
to be stepped linearly from 1.6V to 2.4V using 63 settings. This corresponds to a resolution of 12.7mV/step.
VCC Decoupling
To achieve the best results when using the DS4402/
DS4404, decouple the power supply with a 0.01µF or
0.1µF capacitor. Use a high-quality ceramic surfacemount capacitor if possible. Surface-mount components minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.
Power-Supply Feedback Voltage
The feedback voltage for adjustable power supplies
must be between 0.5V and VCC - 0.5V for the DS4402/
DS4404 to properly sink/source currents for adjusting
the voltage.
Layout Considerations
Care should be taken to ensure that traces underneath
the DS4402/DS4404 do not short with the exposed pad.
The exposed pad should be connected to the signal
ground, or can be left floating.
I2C Reset on Address Change
In addition to defining the I2C slave address, the DS4402/
DS4404 address select inputs have an alternate function.
TYPICAL I2C WRITE TRANSACTION
MSB
START
a7
LSB
a6
a5
a4
a3
a2
a1
R/W
MSB
SLAVE
ACK
b7
READ/
WRITE
SLAVE
ADDRESS*
LSB
b6
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
REGISTER/MEMORY ADDRESS
b4
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1 (SEE TABLE 1).
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE N.C.)
A0h
A) SINGLE BYTE WRITE
-WRITE RESISTOR
F9h TO 00h
A0h
B) SINGLE BYTE READ
-READ RESISTOR F8h
F9h
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1
ACK
SLAVE 0 0 0 0 0 0 0 0
ACK
SLAVE
ACK
F8h
START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE
ACK
ACK
STOP
A1h
REPEATED
START
1 0 1 0 0 0 0 1 SLAVE
ACK
DATA
MASTER
NACK
STOP
Figure 4. I2C Communication Examples
Package Information
Chip Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
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