Revised October 2000 74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs General Description Features The AC/ACT253 is a dual 4-input multiplexer with 3-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems. ■ ICC and IOZ reduced by 50% ■ Multifunction capability ■ Non inverting 3-STATE outputs ■ Outputs source/sink 24 mA ■ ACT253 has TTL-compatible inputs Ordering Code: Order Number Package Number 74AC253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74AC253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74AC253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74ACT253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT253MTC 74ACT253PC MTC16 N16E Package Description 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Diagrams Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description I0a–I3a Side A Data Inputs I0b–I3b Side B Data Inputs S0, S1 Common Select Inputs OEa Side A Output Enable Input OEb Side B Output Enable Input Za, Zb 3-STATE Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009946 www.fairchildsemi.com 74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs November 1988 74AC253 • 74ACT253 Functional Description Truth Table The AC/ACT253 contains two identical 4-input multiplexers with 3-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The 4-input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown: Za = OEa • Zb = OEb • Select Output Data Inputs Outputs Inputs Enable S0 S1 I0 I1 I2 I3 OE Z X X X X X X H Z L L L X X X L L L L H X X X L H (I0a • S1 • S0 + I1a • S1 • S0 + H L X L X X L L I2a • S1 • S0 + I3a • S1 • S0) H L X H X X L H (I0b • S1 • S0 + I1b • S1 • S0 + L H X X L X L L I2b • S1 • S0 + I3b • S1 • S0) L H X X H X L H H H X X X L L L H H X X X H L H If the outputs of 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to 3STATE devices whose outputs are tied together are designed so that there is no overlap. Address Inputs S0 and S1 are common to both sections. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Input Voltage (VI) VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V 140°C PDIP 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH VIL VOH Parameter VCC TA = +25°C (V) Typ Minimum HIGH Level 3.0 1.5 Input Voltage 4.5 5.5 TA = −40°C to +85°C Guaranteed Limits 2.1 2.1 2.25 3.15 3.15 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 0.1 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level Output Voltage 3.0 0.002 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA Current 5.5 ±0.25 ±2.5 µA VI = VCC, GND Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min 40.0 µA VIN = VCC or GND VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VI (OE) = VIL, VIH VO = VCC, GND IOLD IOHD Output Current (Note 3) 5.5 ICC (Note 4) Maximum Quiescent Supply Current 5.5 4.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC253 • 74ACT253 Absolute Maximum Ratings(Note 1) 74AC253 • 74ACT253 DC Electrical Characteristics for ACT Symbol Parameter Minimum HIGH Level VIH VIL VOH TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.25 ±2.5 µA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current ICCT Maximum IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA ICC Maximum Quiescent 5.5 ICC/Input Supply Current 0.6 5.5 4.0 µA 40.0 VOHD = 3.85V Min VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Max Min Max Propagation Delay 3.3 2.0 8.5 15.5 2.0 17.5 Sn to Zn 5.0 2.0 6.5 11.0 1.5 12.5 Propagation Delay 3.3 2.5 9.5 16.0 2.0 18.0 Sn to Zn 5.0 2.0 7.0 11.5 1.5 13.0 Propagation Delay 3.3 1.5 7.0 14.5 1.5 17.0 In to Zn 5.0 1.5 5.5 10.0 1.5 11.5 Propagation Delay 3.3 2.0 7.5 13.0 1.5 15.0 In to Zn 5.0 1.5 5.5 9.5 1.5 11.0 Output Enable Time 3.3 1.5 4.5 8.0 1.0 8.5 5.0 1.5 3.5 6.0 1.0 6.5 3.3 1.5 5.0 8.0 1.0 9.0 5.0 1.5 3.5 6.0 1.0 7.0 3.3 2.0 5.5 9.5 1.5 10.0 5.0 2.0 5.0 8.0 1.5 8.5 Output Enable Time Output Disable Time Output Disable Time 3.3 1.5 5.0 8.0 1.0 9.0 5.0 1.5 4.0 7.0 1.0 7.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units ns ns ns ns ns ns ns ns Symbol tPLH Parameter Propagation Delay Sn to Zn tPHL Propagation Delay Sn to Zn tPLH Propagation Delay In to Zn tPHL Propagation Delay In to Zn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 8) Min Typ Max Min Max 5.0 2.0 7.0 11.5 2.0 13.0 ns 5.0 3.0 7.5 13.0 2.5 14.5 ns 5.0 2.5 5.5 10.0 2.0 11.0 ns 5.0 3.5 6.5 11.0 3.0 12.5 ns ns tPZH Output Enable Time 5.0 2.0 4.5 7.5 1.5 8.5 tPZL Output Enable Time 5.0 2.0 5.0 8.0 1.5 9.0 ns tPHZ Output Disable Time 5.0 3.0 6.0 9.5 2.5 10.0 ns tPLZ Output Disable Time 5.0 2.5 4.5 7.5 2.0 8.5 ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 50.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC253 • 74ACT253 AC Electrical Characteristics for ACT 74AC253 • 74ACT253 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 74AC253 • 74ACT253 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC253 • 74ACT253 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC253 • 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com