MITSUBISHI M30201F6

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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or
56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
The M30201 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Basic machine instructions .................. Compatible with the M16C/60 series
• Memory capacity .................................. ROM/RAM (See figure 1.4. ROM expansion.)
• Shortest instruction execution time ...... 100ns (f(XIN)=10MHz)
• Supply voltage ..................................... 4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM
version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
• Interrupts .............................................. 9 internal and 3 external interrupt sources, 4 software
(including key input interrupt)
• Multifunction 16-bit timer ...................... Timer A x 1, timer B x 2, timer X x 3
• Clock output
• Serial I/O .............................................. 1 channel for UART or clock synchronous, 1 for UART
• A-D converter ....................................... 10 bits X 8 channels (Expandable up to 13 channels)
• Watchdog timer .................................... 1 line
• Programmable I/O ............................... 43 lines
• LED drive ports .................................... 8 ports
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Home appliances, Audio, office equipment, Automobiles
Specifications written in this manual are believed to
be accurate, but are not guaranteed to be entirely
free of error.
Specifications in this manual may be changed for
functional or performance improvements. Please
make sure your manual is the latest edition.
------Table of Contents-----Central Processing Unit (CPU) ..................... 12
Reset ............................................................. 15
Clock Generating Circuit ............................... 19
Protection ...................................................... 26
Interrupts ....................................................... 27
Watchdog Timer ............................................ 35
Timer ............................................................. 37
Serial I/O ....................................................... 64
A-D Converter ............................................... 78
Programmable I/O Ports ............................... 88
Electric Characteristics ................................. 95
Flash Memory version ................................. 126
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1 to 1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
1
52
P60/AN0
VREF
AVCC
P54/CKOUT/AN54
2
3
4
51
50
49
5
6
7
48
47
46
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
8
9
10
45
44
43
RESET
XOUT
VSS
13
14
15
XIN
VCC
16
17
18
P53/CLKS/AN53
P52/CLK0/AN52
P45/TX2INOUT
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
P42/RXD1
P41/TA0OUT
P40/TA0IN/TXD1
P35
P34
P33
11
12
M30201MX-XXXSP
M30201MXT-XXXSP
M30201F6SP
M30201F6TSP
AVSS
42
41
40
39
38
37
36
35
19
20
21
34
33
32
22
23
24
31
30
29
25
26
28
27
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P00/KI0
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P14(LED4)
P15(LED5)
P16(LED6)
P17(LED7)
P30
P31
P32
Package: 52P4B
Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
P66/AN6
P60/AN0
AVSS
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
N.C.
AVCC
VREF
54
53
52
51
50
49
48
47
46
45
44
43
P52/CLK0/AN52
56
55
P53/CLKS/AN53
P54/CKOUT/AN54
PIN CONFIGURATION (top view)
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
1
2
3
42
41
40
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
4
5
6
39
38
37
RESET
N.C.
XOUT
7
8
VSS
XIN
VCC
9
10
11
P45/TX2INOUT
12
13
14
36
35
34
33
32
31
30
29
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P33
P32
P31
P30
P17(LED7)
P16(LED6)
P15(LED5)
P14(LED4)
P42/RXD1
P41/TA0OUT
P40/TA0IN/TXD1
N.C.
P35
P34
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
M30201MX-XXXFP
M30201MXT-XXXFP
M30201F6FP
M30201F6TFP
P67/AN7
N.C.
P00/KI0
P01/KI1
Package: 56P6S-A
Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.3 is a block diagram of the M30201 group.
8
I/O ports
Port P0
8
6
Port P1
6
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
A-D converter
System clock generator
Timer
(10 bits X 8 channels
XIN-XOUT
XCIN-XCOUT
Timer TA0 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TX0 (16 bits)
Timer TX1 (16 bits)
Timer TX2 (16 bits)
Expandable up to 13 channels)
(15 bits)
Port P7
(8 bits X 1 channel)
UART
(8 bits X 1 channel)
Registers
Watchdog timer
2
UART/clock synchronous SI/O
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAA
AAAAA
M16C/60 series16-bit CPU core
R0H
R0L
R0H
R0L
R1H
R1L
R1H
R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.3. Block diagram for the M30201 group
4
8
5
Program counter
PC
Vector table
INTB
Stack pointer
ISP
USP
FLG
Memory
ROM
(Note 1)
RAM
(Note 2)
Multiplier
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1 is performance outline of M30201 group.
Table 1.1. Performance outline of M30201 group
Item
Number of basic instructions
Shortest instruction execution time
Memory
ROM
capacity
RAM
I/O port
P0 to P7
Multifunction TA0
timer
TB0, TB1
TX0, TX1, TX2
Serial I/O
UART0
UART1
A-D converter
Performance
91 instructions
100ns (f(XIN)=10MHz
(See figure 4. ROM expansion.)
(See figure 4. ROM expansion.)
43 lines
16 bits x 1
16 bits x 2
16 bits x 3
(UART or clock synchronous) x 1
UART x 1
10 bits x 8 channels (Expandable up to 13 channels)
Watchdog timer
Interrupt
Clock generating circuit
15 bits x 1 (with prescaler)
9 internal and 3 external sources, 4 software sources
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or
quartz oscillator)
4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=7MHz with software one-wait) :mask
ROM version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
18mW (f(XIN)=7MHz with software one-wait, Vcc=3V)
:mask ROM version
95mW (f(XIN)=10MHz no wait, Vcc=5V) :flash memory version
5V
5mA (15mA:LED drive port)
CMOS silicon gate
52-pin plastic mold SDIP
56-pin plastic mold QFP
Supply voltage
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M30201 group:
(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
52P4B
: Plastic molded SDIP (mask ROM version and flash memory version)
56P6S-A
: Plastic molded QFP (mask ROM version and flash memory version)
July 1998
RAM Size
(Byte)
M30201F6SP/FP
M30201F6TSP/FP
2K
Under development
M30201M4-XXXSP/FP
M30201M4T-XXXSP/FP
1K
Under development
512
M30201M2-XXXSP/FP
M30201M2T-XXXSP/FP
Under planning
16K
48K
32K
ROM Size
(Byte)
Figure 1.4. ROM expansion
Type No.
M30201 M 4 T – XXX SP
Package type:
SP : Package
FP : Package
52P4B
56P6S-A
ROM No.
Omitted for flash memory version
Shows difference of characteristics
and usage etc:
Nothing : Common
T
: Automobiles
ROM capacity:
2 : 16K bytes
4 : 32K bytes
6 : 48K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows pin count, etc
(The value itself has no specific meaning)
M16C/20 Group
M16C Family
Figure 1.5. Type No., memory size, and package
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
Signal name
I/O type
Function
VCC, VSS
Power supply
input
CNVSS
CNVSS
Input
Connect it to the VSS pin.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
Clock input
Input
XOUT
Clock output
Output
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the XIN and the
XOUT pins. To use an externally derived clock, input it to the
XIN pin and leave the XOUT pin open.
AVCC
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect
it to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect
it to VSS.
VREF
Reference
voltage input
Input
This pin is a reference voltage input for the A-D converter.
P00 to P07
I/O port P0
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor.
P10 to P17
I/O port P1
Input/output
This is an 8-bit I/O port equivalent to P0.
P30 to P35
I/O port P3
Input/output
This is a 6-bit I/O port equivalent to P0.
P40 to P45
I/O port P4
Input/output
This is a 6-bit I/O port equivalent to P0. The P40 pin is shared
with timer A0 input and serial I/O output TxD1. The P41 pin is
shared with timer A0 output. The P42 pin is shared with serial
I/O input RxD1. The P43 pin is shared with external interrupt
INT0 and timer X0 input/output TX0INOUT. The P44 pin is
shared with external interrupt INT1 and timer X1 input/output
TX1INOUT. The P45 pin is shared with timer X2 input/output
TX2INOUT.
I/O port P5
Input/output
This is a 5-bit I/O port equivalent to P0. The P50, P51, P52, and
P53 pins are shared with serial I/O pins TxD0, RxD0, CLK0,
and CLKS. The P54 pin is shared with clock output CLKOUT.
Also, these pins are shared with analog input pins AN50
through AN54.
P60 to P67
I/O port P6
Input/output
This is an 8-bit I/O port equivalent to P0. These pins are shared
with analog input pins AN0 through AN7.
P70 to P71
I/O port P7
Input/output
This is a 2-bit I/O port equivalent to P0 . These pins are used
for input/output to and from the oscillator circuit for the clock.
Connect a crystal oscillator between the XCIN and the XCOUT
pins.
P50 to P54
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store
instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also
included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address
0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXFP, there is 32K
bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
From 0040016 up is RAM. For example, in the M30201M4-XXXFP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see
Figures 1.7 to 1.8
FFE0016
0040016
Internal RAM area
Special page
vector table
YYYYY16
FFFDC16
Address
YYYYY16
Type No.
Address
XXXXX16
M30201M4
F800016
007FF16
M30201M2
FC00016
005FF16
M30201F6
F400016
00BFF16
Overflow
BRK instruction
Address match
Single step
Watchdog timer
DBC
XXXXX16
Internal ROM area
FFFFF16
Figure 1.6. Memory map
8
Undefined instruction
FFFFF16
Reset
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
000016
004016
000116
004116
000216
004216
004316
000316
000416
000516
000616
000716
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
000A16
004516
004616
004716
004816
000816
000916
004416
Address match interrupt enable register (AIER)
Protect register (PRCR)
004916
000B16
004A16
000C16
004B16
000D16
000E16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
004D16
004E16
001016
001116
004C16
Address match interrupt register 0 (RMAD0)
004F16
001216
005016
001316
005116
001416
005216
001516
Address match interrupt register 1 (RMAD1)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
005316
001616
005416
001716
005516
001816
005616
001916
005716
001A16
005816
001B16
005916
001C16
005A16
001D16
005B16
001E16
005C16
001F16
005D16
002016
005E16
002116
005F16
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer X0 interrupt control register (TX0IC)
Timer X1 interrupt control register (TX1IC)
Timer X2 interrupt control register (TX2IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Figure 1.7. Location of peripheral unit control registers (1)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
038016
038116
038216
038316
038416
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
03C016
03C116
03C216
03C316
03C416
038516
03C516
038616
03C616
038716
038816
038916
038A16
038B16
038C16
Timer A0 (TA0)
Timer X0 (TX0)
Timer X1 (TX1)
038D16
Timer X2 (TX2)
038E16
Clock divided counter (CDC)
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
038F16
03CF16
039016
03D016
039116
039216
039316
Timer B0 (TB0)
Timer B1 (TB1)
03D516
039816
039916
039A16
039B16
039C16
03D616
03D716
UART0 transmit/receive mode register (U0MR)
03DF16
03E016
03A116
UART0 bit rate generator (U0BRG)
03E116
03A716
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
03E216
03E316
03E416
03E516
03E616
03E716
03A816
UART1 transmit/receive mode register (U1MR)
03E816
03A916
UART1 bit rate generator (U1BRG)
03E916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F116
03B216
03F216
03B316
03B516
03B616
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2) (Reserved)
Port P3 (P3)
Port P2 direction register (PD2) (Reserved)
Port P3 direction register (PD3)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
03F016
03B116
03B416
A-D control register 2 (ADCON2)
03DC16
03A016
03A616
A-D register 7 (AD7)
03DB16
03DE16
039F16
03A516
A-D register 6 (AD6)
03DA16
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
03DD16
03A416
A-D register 5 (AD5)
03D916
039E16
03A316
A-D register 4 (AD4)
03D816
039D16
03A216
A-D register 3 (AD3)
03D316
03D416
Timer A0 mode register (TA0MR)
Timer X0 mode register (TX0MR)
Timer X1 mode register (TX1MR)
Timer X2 mode register (TX2MR)
A-D register 2 (AD2)
03D216
039516
039716
A-D register 1 (AD1)
03D116
039416
039616
A-D register 0 (AD0)
03F316
Flash memory control register 0 (FCON0) (Note)
Flash memory control register 1 (FCON1) (Note)
Flash command register (FCMD) (Note)
03F416
03F516
03F616
03B716
03F716
03B816
03F816
03B916
03F916
03BA16
03FA16
03BB16
03FB16
03BC16
03FC16
03BD16
03FD16
03BE16
03FE16
03BF16
03FF16
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Port P1 drive control register (DRR)
Note: This register is only exist in flash memory version.
Figure 1.8. Location of peripheral unit control registers (2)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
b15
R0(Note)
b8 b7
b15
R1(Note)
b15
R3(Note)
b15
A0(Note)
b15
A1(Note)
b15
FB(Note)
b8 b7
H
b15
R2(Note)
b0
L
H
b19
b0
L
Program counter
Data
registers
b0
b19
INTB
b0
Interrupt table
register
L
H
b15
b0
b0
User stack pointer
USP
b15
b0
b0
b0
PC
b0
Interrupt stack
pointer
ISP
Address
registers
b15
b0
Static base
register
SB
b15
b0
Frame base
registers
b0
FLG
Flag register
AA
AAAAAA
AA
AA
A
AA
AA
A
AA
AA
AA
AAAAAAAAAAAAAAAAA
AAA
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.9. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
AAAAAAA
b15
R0(Note)
b8 b7
b15
R1(Note)
b8 b7
H
b15
b0
L
H
b19
b0
L
b19
R2(Note)
INTB
b15
b15
Address
registers
b0
Interrupt stack
pointer
b15
b0
Static base
register
SB
b15
b0
Frame base
registers
b0
FLG
Flag register
AA
AAAAAA
AA
AA
AA
A
AA
AA
AA
AA
AA
AAAAAA
AA
AA
AA
AAA
AA
AA
AA
IPL
Figure 1.10. Flag register (FLG)
User stack po
ISP
A1(Note)
FB(Note)
b0
b15
b0
b0
Interrupt table
register
USP
A0(Note)
b15
b0
L
H
b0
R3(Note)
b15
Program coun
Data
registers
b0
b15
b0
PC
U
I
O B S
Z
D C
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.11 shows the example reset circuit. Figure 1.12 shows the reset sequence.
5V
4.0V
VCC
RESET
VCC
0V
5V
RESET
0.8V
0V
Example when VCC = 5V.
Figure 1.11. Example reset circuit
XIN
More than 20 cycles are needed
RESET
BCLK
24cycles
BCLK
(Internal clock)
Content of reset vector
Address
(Internal address
signal)
Figure 1.12. Reset sequence
14
FFFFC16
FFFFE16
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1) Processor mode register 0
(000416)···
(2) Processor mode register 1
(000516)··· 0
(3) System clock control register 0
0 0 0 0
(33) Timer B0 mode register
(039B16)··· 0 0 ?
0 0 0 0
0 0
(34) Timer B1 mode register
(039C16)··· 0 0 ?
0 0 0 0
(35) UART0 transmit/receive mode
register
(36) UART0 transmit/receive control
register 0
(37) UART0 transmit/receive control
register 1
(38) UART1 transmit/receive mode
register
(39) UART1 transmit/receive control
register 0
(03A016)···
(000616)··· 0 1 0 0 1 0 0 0
(4) System clock control register 1
(000716)··· 0 0 1 0 0 0 0 0
(5) Address match interrupt
enable register
(000916)···
0 0
(6) Protect register
(000A16)···
0 0 0
(7) Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(8) Address match interrupt
register 0
(001016)···
0016
(001116)···
0016
(001216)···
(9) Address match interrupt
register 1
0 0 0 0
(11) A-D conversion interrupt
control register
(12) UART0 transmit interrupt control
register
(13) UART0 receive interrupt control
register
(03A516)··· 0 0 0 0 0 0 1 0
(03A816)···
0016
(03AC16)··· 0 0 0 0 1 0 0 0
(03AD16)··· 0 0 0 0 0 0 1 0
(03B016)···
0 0 0 0 0 0 0
(42) Flash memory control register 0
(Note )
(03B416)··· 0 0 1 0 0 0 0 0
(001416)···
0016
(43) Flash memory control register 1
(Note)
(03B516)···
(001516)···
0016
(44) Flash command register
(03B616)···
0 0 0 0
(45) A-D control register 2
(03D416)···
? 0 0 0
(46) A-D control register 0
(03D616)··· 0 0 0 0 0 ? ? ?
? 0 0 0
(47) A-D control register 1
(03D716)···
0016
? 0 0 0
(48) Port P0 direction register
(03E216)···
0016
? 0 0 0
(49) Port P1 direction register
(03E316)···
0016
(03E616)···
0 0 0 0 0 0 0
(001616)···
(10) Key input interrupt control register
(40) UART1 transmit/receive control
register 1
(41) UART transmit/receive control
register 2
0016
(03A416)··· 0 0 0 0 1 0 0 0
(004D16)···
(004E16)···
(005116)···
(005216)···
0 0
0016
0 0 0 0
(14) UART1 transmit interrupt control
register
(005316)···
? 0 0 0
(50) Port P2 direction register
(15) UART1 receive interrupt control
register
(005416)···
? 0 0 0
(51) Port P3 direction register
(03E716)···
0 0 0 0 0 0
(16) Timer A0 interrupt control register
(005516)···
? 0 0 0
(52) Port P4 direction register
(03EA16)···
0 0 0 0 0 0
(17) Timer X0 interrupt control register
(005616)···
? 0 0 0
(53) Port P5 direction register
(03EB16)···
0 0 0 0 0
(18) Timer X1 interrupt control register
(005716)···
? 0 0 0
(54) Port P6 direction register
(03EE16)···
0016
(19)Timer X2 interrupt control register
(005816)···
? 0 0 0
(55) Port P7 direction register
(03EF16)···
(20)Timer B0 interrupt control register
(005A16)···
? 0 0 0
(56) Pull-up control register 0
(03FC16)···
0016
(21)Timer B1 interrupt control register
(005B16)···
? 0 0 0
(57) Pull-up control register 1
(03FD16)···
0016
(22)INT0 interrupt control register
(005D16)···
0 0 ? 0 0 0
(58) Port P1 drive capacity control
register
(03FE16)···
0016
(23)INT1 interrupt control register
(005E16)···
0 0 ? 0 0 0
(59) Data registers (R0/R1/R2/R3)
000016
(24)Count start flag
(038016)··· 0 0 0
(60) Address registers (A0/A1)
000016
(25)Clock prescaler reset flag
(038116)··· 0
(61) Frame base register (FB)
000016
(26)One-shot start flag
(038216)···
(62) Interrupt table register (INTB)
0000016
(27)Trigger select flag
(038316)···
0016
(63) User stack pointer (USP)
000016
(64) Interrupt stack pointer (ISP)
000016
0 0 0 0
0 0 0 0
0 0
(28) Up-down flag
(038416)···
0
(29)Timer A0 mode register
(039616)···
0016
(65) Static base register (SB)
000016
(30)Timer X0 mode register
(039716)···
0016
(66) Flag register (FLG)
000016
(31)Timer X1 mode register
(039816)···
0016
(32)Timer X2 mode register
(039916)···
0016
0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: This register is only exist in flash memory version.
Figure 1.13. Device's internal status after a reset is cleared
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software
Reset
Bus Control
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 1.14 shows the processor mode register 0 and 1.
Processor mode register 0 (Note)
Symbol
PM0
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0
Address
000416
Bit symbol
Bit name
Reserved bit
PM03
When reset
XXXX00002
Function
Must always be set to “0”
Software reset bit
The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
A
A
R W
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
When reset
00XXXXX02
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
PM17
Wait bit
0 : No wait state
1 : Wait state inserted
A
A
R W
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values
to this register.
Figure 1.14. Processor mode register 0 and 1.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Wait
Software wait
The wait bit (bit 7) of the processor mode register 1 (address 000516)(note) allows you to insert software
wait states for the internal ROM/RAM areas. If this bit is 0, the bus cycle is executed in one BCLK (internal
clock) period; if the bit is 1, the bus cycle is executed in two BCLK periods. This bit is cleared to 0 after a
reset.
The SFR area is unaffected by this control bit; it is always accessed in two BCLK periods.
Table 1.2 shows the relationship between software wait states and bus cycles.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.2. Software waits and bus cycles
Bus cycle
Area
Wait bit
SFR
Invalid
2 BCLK cycles
0
1 BCLK cycle
1
2 BCLK cycles
Internal
ROM/RAM
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.3. Main clock and sub-clock generating circuits
Use of clock
Usable oscillator
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Main clock generating circuit
Sub clock generating circuit
• CPU’s operating clock source
• CPU’s operating clock source
• Internal peripheral units’
• Timer A/B/X’s count clock
operating clock source
source
Ceramic or crystal oscillator
Crystal oscillator
XIN, XOUT
XCIN, XCOUT
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 1.16 shows some examples of subclock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived
clock for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values
recommended by the manufacturer of your oscillator.
M30201
M30201
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
Vcc
Vss
Note: Insert a damping resistor if
required. The resistance will
vary depending on the
oscillator and the oscillation
drive capacity setting. Use the
value recommended by the
maker of the oscillator.
When the oscillation drive
capacity is set to low, check
that oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between XIN
and XOUT following the
instruction.
Figure 1.15. Examples of main clock
M30201
M30201
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Figure 1.16. Examples of sub-clock
18
Vcc
Vss
Note: Insert a damping resistor if
required. The resistance will
vary depending on the oscillator
and the oscillation drive
capacity setting. Use the value
recommended by the maker of
the oscillator.
When the oscillation drive
capacity is set to low, check that
oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between
XCIN and XCOUT following the
instruction.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.17 shows the block diagram of the clock generating circuit.
XCIN
XCOUT
fC32
1/32
f1
CM04
fAD
fC
f8
Sub clock
CM10 “1”
Write signal
f32
S Q
XIN
AAA
AAA
XOUT
b
R
a
RESET
Software reset
CM05
Main clock
CM02
c
Divider
d
CM07=0
fC
CM07=1
BCLK
Interrupt request
level judgment output
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
Details of divider
Figure 1.17. Clock generating circuit
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the
sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
Bit symbol
CM00
When reset
4816
Bit name
Clock output function
select bit
CM01
Function
b1 b0
0 0 : I/O port P54
0 1 : fC output
1 0 : f8 output
1 1 : Clock divide counter output
AA
A
A
A
A
AA
A
A
AA
A
A
A
A
A
A
AA
R W
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
CM02
WAIT peripheral function
clock stop bit
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
CM04
Port XC select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM05
Main clock (XIN-XOUT)
stop bit (Note 3,4,5)
0 : On
1 : Off
CM06
Main clock division select
bit 0 (Note 7)
0 : CM16 and CM17 valid
1 : Division by 8 mode
CM07
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN
after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock
select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to
XOUT (“H”) via the feedback resistor.
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock
oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note 4)
Function
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM15
XIN-XOUT drive capacity
select bit (Note 2)
CM16
Main clock division
select bit 1 (Note 3)
0 : LOW
1 : HIGH
b7 b6
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
AA
AA
AA
AA
AA
AA
AA
RW
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.
Figure 1.18. Clock control registers 0 and 1
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is
output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and
its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output.
Clock source
selection
P54
f8
fC
P54/CKOUT
1/2
f32
Clock divided couter (8)
Division n+1 n=0016 to FF16
Reload register (8)
Low-order 8 bits
Data bus low-order bits
Figure 1.19. Block diagram of clock output
22
Address 038E16
Example:
When f(XIN)=10MHz
n=0716 : approx. 16.5kHz
n=2616 : approx. 4.0kHz
n=4D16 : approx. 2.0kHz
n=9B16 : approx. 1.0kHz
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ClockMode
Generating Circuit
Wait
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate
provided that the event counter mode is set to an external pulse, and UART0 functions provided an external
clock is selected. Table 1.4 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.4. Port status during stop mode
Pin
Port
CLKOUT
When fC selected
States
Retains status before stop mode
“H”
When f8, clock devided Retains status before stop mode
counter output selected
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table 1.5 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.5. Port status during wait mode
Pin
Port
CLKOUT
When fC selected
States
Retains status before wait mode
Does not stop
When f8, clock devided Does not stop when the WAIT
counter output selected peripheral function clock stop bit is “0”.
When the WAIT peripheral function
clock stop bit is “1”,the status immediately prior to entering wait mode is
maintained.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating
Circuit
Status
Transition of
BCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.6 shows the operating modes corresponding to the settings of system clock control registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.6. Operating modes dictated by settings of system clock control registers 0 and 1
24
CM17
CM16
CM07
CM06
CM05
CM04
Operating mode of BCLK
0
1
Invalid
1
0
Invalid
Invalid
1
0
Invalid
1
0
Invalid
Invalid
0
0
0
0
0
1
1
0
0
1
0
0
Invalid
Invalid
0
0
0
0
0
0
1
Invalid
Invalid
Invalid
Invalid
Invalid
1
1
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Low-speed mode
Low power dissipation mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power
Saving
Clock Generating
Circuit
Power Saving
There are three power save modes.
(1) Normal operating mode
• High-speed mode
In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral
functions operate on the clocks specified for each respective function.
• Medium-speed mode
In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the
BCLK. The peripheral functions operated on the clocks specified for each respective function.
• Low-speed mode
In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the
subclock. The peripheral functions operate on the clocks specified for each respective function.
• Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on
the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the
subclock was selected as the count source continue to run.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving
modes, power savings are greatest in this mode.
Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3).
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating
Power
Saving
Circuit
Transition of stop mode, wait mode
Reset
All oscillators stopped
CM10 = “1”
Stop mode
Interrupt
All oscillators stopped
CM10 = “1”
CM10 = “1”
Interrupt
CPU operation stopped
WAIT
instruction
High-speed/mediumspeed mode
Wait mode
Interrupt
All oscillators stopped
Stop mode
Wait mode
Interrupt
Interrupt
Stop mode
CPU operation stopped
WAIT
instruction
Medium-speed mode
(divided-by-8 mode)
CPU operation stopped
WAIT
instruction
Low-speed/low power
dissipation mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
Main clock is oscillating CM04 = “0”
Sub clock is oscillating
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XCIN)
CM07 = “1”
CM07 = “1”
(Note 2)
CM05 = “0”
CM04 = “0”
CM06 = “0”
(Notes 1,3)
Main clock is oscillating
Sub clock is stopped
CM04 = “1”
High-speed mode
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
CM07 = “1” (Note 2)
CM05 = “1”
26
BCLK : f(XCIN)
CM07 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.20. Clock transition
CM05 = “1”
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register
(address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P4.
If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Bit symbol
Address
000A16
When reset
XXXXX0002
Bit name
Function
PRC0
Enables writing to system clock
control registers 0 and 1 (addresses 0 : Write-inhibited
1 : Write-enabled
000616 and 000716)
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 000416
1 : Write-enabled
and 000516)
PRC2
Enables writing to port P4 direction
register (address 03EA16) (Note)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
R W
AA
AA
AA
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.21. Protect register
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Overview of Interrupt
Type of Interrupts
Figure 1.22 lists the types of interrupts.










Hardware
Special














Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
DBC
Watchdog timer
Single step
Address matched
________
Peripheral I/O*1
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.22. Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I
flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”.
The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so
executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt
does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select
the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the
interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So
far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt
This is an interrupts that timer A0 generates.
• Timer B0 and timer B2 interrupt
These are interrupts that timer B generates.
• Timer X0 to timer X2 interrupt
These are interrupts that timer X generates.
________
________
• INT0 and INT1 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
MSB
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
LSB
Low address
Mid address
0000
High address
0000
0000
Figure 1.23. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 1.7. Interrupt and fixed vector address
Interrupt source
Undefined instruction
Overflow
BRK instruction
Address match
Single step (Note)
Watchdog timer
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
________
DBC (Note)
FFFF416 to FFFF716
Do not use
Reset
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
-
Note: Interrupts used for debugging purposes only.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 1.8 shows the interrupts assigned
to the variable vector tables and addresses of vector tables.
Table 1.8. Interrupt causes (variable interrupt vector addresses)
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note)
BRK instruction
Software interrupt number 11
+44 to +47 (Note)
Software interrupt number 12
+48 to +51 (Note)
Software interrupt number 13
+52 to +55 (Note)
Key input interrupt
Software interrupt number 14
+56 to +59 (Note)
A-D
Software interrupt number 17
+68 to +71 (Note)
UART0 transmit
Software interrupt number 18
+72 to +75 (Note)
UART0 receive
Software interrupt number 19
+76 to +79 (Note)
UART1 transmit
Software interrupt number 20
+80 to +83 (Note)
UART1 receive
Software interrupt number 21
+84 to +87 (Note)
Timer A0
Software interrupt number 22
+88 to +91 (Note)
Timer X0
Software interrupt number 23
+92 to +95 (Note)
Timer X1
Software interrupt number 24
+96 to +99 (Note)
Timer X2
Software interrupt number 25
+100 to +103 (Note)
Software interrupt number 26
+104 to +107 (Note)
Timer B0
Software interrupt number 27
+108 to +111 (Note)
Timer B1
Software interrupt number 28
+112 to +115 (Note)
Software interrupt number 29
+116 to +119 (Note)
INT0
Software interrupt number 30
+120 to +123 (Note)
INT1
Software interrupt number 31
+124 to +127 (Note)
Software interrupt number 32
+128 to +131 (Note)
to
Software interrupt number 63
to
+252 to +255 (Note)
Software interrupt
Note : Address relative to address in interrupt table register (INTB).
32
Remarks
Cannot be masked by I flag
Cannot be masked by I flag
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select
bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are
located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL
are located in the flag register (FLG).
Figure 1.24 shows the interrupt control registers.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt control register
AAA
AA
A
AAA
AA
A
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KUPIC
ADIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0)
TXiIC(i=0 to 2)
TBiIC(i=0, 1)
Bit symbol
ILVL0
Address
004D16
004E16
005116, 005316
005216, 005416
005516
005616 to 005816
005A16, 005B16
Bit name
Interrupt priority level
select bit
ILVL2
IR
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
ILVL1
Interrupt request bit
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
AAAA
AA
A
A
AAAA
AA
AA
AAAA
R
W
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
(Note)
Note: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
AAA
A
AA
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INTiIC(i=0, 1)
Bit symbol
ILVL0
Address
005D16, 005E16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
When reset
XX00X0002
Interrupt request bit
Polarity select bit
Reserved bit
Function
b2 b1 b0
R
AA
A
A
AAAA
AAAA
AA
A
A
AAAA
AA
A
A
AAAA
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Note: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Figure 1.24. Interrupt control register
34
W
(Note)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.9 shows the settings of interrupt priority levels and Table 1.10 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.9. Settings of interrupt priority levels
Interrupt priority
level select bit
b2 b1 b0
Interrupt priority
level
0
0
0
Level 0
(interrupt disabled)
0
0
1
Level 1
0
1
0
0
1
1
Table 1.10. Interrupt levels enabled according
to the contents of the IPL
Priority
order
IPL
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Interrupt levels 2 and above are enabled
Level 2
0
1
0
Interrupt levels 3 and above are enabled
1
Level 3
0
1
1 Interrupt levels 4 and above are enabled
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
Low
High
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Changing the Interrupt Control Register
< Program examples >
The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B
#00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B
#00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B
#00h, 0055h
POPC
FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and
2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten
due to effects of the instruction queue.
If changing the interrupt control register using an instruction other than the instructions listed hear, and
if an interrupt occurs associated with this register during execution of the instruction, there can be
instances in which the interrupt request bit is not set. To avoid this problem, use one of the instructions given below to change the register.
Following instructions: AND, OR, BCLR or BSET
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U
flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
Instruction in
interrupt routine
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.25. Interrupt response time
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.
Table 1.11. Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-bit bus, without wait
8-bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
000016
Address bus
Interrupt
information
Data bus
R
Indeterminate
Indeterminate
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.26. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.12 is set in the IPL.
Table 1.12. Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Watchdog timer
7
Reset
0
Other
38
Value set in the IPL
Not changed
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 loworder bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the
program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
Stack status before interrupt request
is acknowledged
[SP]
Stack pointer
value before
interrupt occurs
Flag register
(FLGH)
[SP]
New stack
pointer value
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Figure 1.27. State of stack before and after acceptance of interrupt request
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.28 shows the operation of the saving registers.
Note: Stack pointer indicated by U flag.
(1) Stack pointer (SP) contains even number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Odd)
[SP] – 4 (Even)
Program counter (PCL)
[SP] – 3(Odd)
Program counter (PCM)
[SP] – 2 (Even)
Flag register (FLGL)
[SP] – 1(Odd)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
Program counter (PCL)
(3)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2(Odd)
Flag register (FLGL)
[SP] – 1 (Even)
[SP]
Flag register
(FLGH)
Program
counter (PCH)
Saved simultaneously,
all 8 bits
(1)
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.28. Operation of saving registers
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.29 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are generated
simultaneously.
Figure 1.30 shows the interrupt resolution circuit.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
________
Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.29. Hardware interrupts priorities
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B0
High
Timer X2
Timer X0
INT0
Timer B1
Timer X1
UART1 reception
UART0 reception
A-D conversion
Timer A0
UART1 transmission
Priority of peripheral I/O
interrupts
(if priority levels are same)
UART0 transmission
Key input interrupt
Processor interrupt priority level
(IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
Reset
Figure 1.30. Interrupt resolution circuit
42
Low
Interrupt request level judgment output
Interrupt
request
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key
Input Interrupt
Interrupts
Key Input Interrupt
If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input
interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the
wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Port P04-P07 pull-up select
bit
Pull-up
transistor
Key input interrupt control register
Port P07 direction
register
(address 004D16)
Port P07 direction register
P07/KI7
Pull-up
transistor
Port P06 direction
register
Interrupt control
circuit
P06/KI6
Pull-up
transistor
Key input interrupt
request
Port P01 direction
register
P01/KI1
Pull-up
transistor
Port P00 direction
register
P00/KI0
Figure 1.31. Block diagram of key input interrupt
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
InterruptsMatch Interrupt
Address
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL).
Figure 1.32 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Bit symbol
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
44
AA
A
AAA
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Figure 1.32. Address match interrupt-related registers
When reset
X0000016
X0000016
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset,
generating any interrupts is prohibited.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
and INT1 regardless of the CPU operation clock.
________
________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the
______
interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT interrupt request.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 1.33. Switching condition of INT interrupt request
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16).
When XIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
BCLK
When XCIN is selected in BCLK
Watchdog timer cycle =
Prescaler division ratio (2) x watchdog timer count (32768)
BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related
registers.
Prescaler
1/16
BCLK
1/128
“CM07 = 0”
“WDC7 = 0”
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
“CM07 = 1”
1/2
Write to the watchdog timer
start register
(address 000E16)
RESET
Figure 1.34. Block diagram of watchdog timer
46
Set to
“7FFF16”
Watchdog timer
interrupt request
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
WDC
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
A
R W
Figure 1.35. Watchdog timer control and start registers
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer
There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and
timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers.
Clock prescaler
f1
XIN
f8
1/8
1/4
f32
1/32
XCIN
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
fC32
Reset
f1 f8 f32 fc32
• Timer mode
• One-shot mode
• PWM mode
TA0IN
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
TX0INOUT
Noise
filter
TX1INOUT
• Event counter mode
TX2INOUT
• Event counter mode
Noise
filter
Timer X2
Timer X2
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB0IN
Timer X1
Timer X1
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
Noise
filter
Timer X0
Timer X0
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
Noise
filter
Timer A0
Timer A0
Timer B0
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
TB1IN
Noise
filter
Timer B1
Timer B1
• Event counter mode
Figure 1.36. Timer block diagram
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.37 shows the block diagram of timer A. Figures 1.38 to 1.40 show the timer A-related registers.
Use the timer A0 mode register bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
f1
f8
f32
A
A
High-order
8 bits
Low-order
8 bits
• Timer
(gate function)
fC32
AAA
Data bus low-order bits
• Timer
• One shot
• PWM
Reload register (16)
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Always down count except
in event counter mode
Clock selection
TA0IN
Count start flag
Down count
TB1 overflow
External
trigger
TX0 overflow
Up/down flag
TX2 overflow
Pulse output
TA0OUT
Toggle flip-flop
Figure 1.37. Block diagram of timer A
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR
Address
039616
Bit symbol
TMOD0
Bit name
Operation mode select bit
TMOD1
MR0
MR1
When reset
0016
Function
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Figure 1.38. Timer A-related registers (1)
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
Address
038716,038616
When reset
Indeterminate
AA
A
AA
A
AA
A
A
A
A
A
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF16
RW
• Event counter mode
000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FF16
(High-order
addresses)
0016 to FE16 (Loworder addresses)
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
000X00002
AA
A
AA
A
AA
A
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TX0S
Timer X0 count start flag
TX1S
Timer X1 count start flag
TX2S
Timer X2 count start flag
R W
Function
0 : Stops counting
1 : Starts counting
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Up/down flag
b7 b6 b5 b4 b3 b2 b1 b0
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
CDCS
Clock devided count start flag
Symbol
UDF
Address
038416
Bit symbol
TA0UD
Bit name
Timer A0 up/down flag
0 : Stops counting
1 : Starts counting
When reset
XXX0XXX02
RW
Function
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
AA
A
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TA0P
Timer A0 two-phase
pulse signal processing
select bit
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
Figure 1.39. Timer A-related registers (2)
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
Symbol
ONSF
b7 b6 b5 b4 b3 b2 b1 b0
Address
038216
When reset
XXXX00002
Bit symbol
Bit name
Function
TA0OS
Timer A0 one-shot start flag
TX0OS
Timer X0 one-shot start flag
TX1OS
Timer X1 one-shot start flag
TX2OS
Timer X2 one-shot start flag
1 : Timer start
When read, the value is “0”
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
AA
A
RW
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Bit symbol
TA0TGL
Address
038316
Bit name
Timer A0 event/trigger
select bit
TA0TGH
TX0TGL
Timer X0 event/trigger
select bit
TX0TGH
TX1TGL
Timer X1 event/trigger
select bit
TX1TGH
TX2TGL
Timer X2 event/trigger
select bit
TX2TGH
When reset
0016
Function
b1 b0
0 0 : Input on TA0IN is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
b3 b2
0 0 : Input on TX0INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
b5 b4
0 0 : Input on TX1INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
b7 b6
0 0 : Input on TX2INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
AA
AA
AA
AA
R W
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
RW
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
A
AAAAAAAAAAAAAAA
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
Figure 1.40. Timer A-related registers (3)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.) Figure 1.41 shows
the timer A0 mode register in timer mode.
Table 1.13. Specifications of timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Select function
f1, f8, f32, fc32
• Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
When the timer underflows
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer A0 register
• When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Counting can be started and stopped by the TA0IN pin’s input signal
• Pulse output function
Each time the timer underflows, the TA0OUT pin’s polarity is reversed
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
TA0MR
Bit symbol
TMOD0
TMOD1
Address
039616
When reset
0016
Bit name
Operation mode
select bit
MR0
Pulse output function
select bit
MR1
Gate function select bit
Function
b1 b0
0 0 : Timer mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
b4 b3
0 X (Note 2): Gate function not available
(TA0IN pin is a normal port pin)
1 0 : Timer counts only when TA0IN pin
is held “L” (Note 3)
1 1 : Timer counts only when TA0IN pin
is held “H” (Note 3)
MR2
MR3
0 (Must always be fixed to “0” in timer mode)
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.41. Timer A0 mode register in timer mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a
single-phase and a two-phase external signal. Table 1.14 lists timer specifications when counting a
single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode.
Table 1.15 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the
timer A0 mode register in event counter mode.
Table 1.14. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TA0IN pin (effective edge can be selected by software)
• TB1 overflow, TX0 overflow, TX2 overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TA0IN pin function
Programmable I/O port or count source input
TA0OUT pin function
Programmable I/O port, pulse output, or up/down count select input
Read from timer
Count value can be read out by reading timer A0 register
Write to timer
• When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TA0OUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer A0 mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
TA0MR
0 1
Bit symbol
TMOD0
Address
039616
When reset
0016
Bit name
Operation mode select bit
Function
b1 b0
0 1 : Event counter mode
TMOD1
MR0
Pulse output function
select bit
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
TCK1
Two-phase pulse operation 0 : Normal processing operation
select bit (Note 4)
1 : Multiply-by-4 processing operation
0 : Reload type
1 : Free-run type
AAA
AAA
A
AA
AAAA
AA
AAAA
R
RW
W
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 038416) is set to “1” and
event/trigger select bits (addresses 038316) to “00”.
Figure 1.42. Timer A0 mode register in event counter mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.15. Timer specifications in event counter mode (when processing two-phase pulse signal)
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Select function
Specification
• Two-phase pulse signals input to TA0IN or TA0OUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
• 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count
n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
Timer overflows or underflows
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A0 register
• When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register. (Transferred to counter at next reload time.)
• Normal processing operation
The timer counts up rising edges or counts down falling edges on the TA0IN
pin when input signal on the TA0OUT pin is “H”
TA0OUT
TA0IN
Up
count
Up
count
Up
count
Down
count
Down
count
Down
count
• Multiply-by-4 processing operation
If the phase relationship is such that the TA0IN pin goes “H” when the input
signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges
on the TA0OUT and TA0IN pins. If the phase relationship is such that the
TA0IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer
counts down rising and falling edges on the TA0OUT and TA0IN pins.
TA0OUT
Count up all edges
Count down all edges
Count up all edges
Count down all edges
TA0IN
Note: This does not apply when the free-run function is selected.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 mode register
(When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 1
Symbol
TA0MR
Address
039616
When reset
0016
Bit name
TMOD0
TMOD1
Operation mode select bit
Function
b1 b0
0 1 : Event counter mode
AAA
A
A
AA
A
AA
AA
AA
AA
A
A
AA
MR0
0 (Must always be “0” when using two-phase pulse signal
processing)
MR1
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
MR3
0 (Must always be “0” when using two-phase pulse signal
processing)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Two-phase pulse
processing operation
select bit (Note)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
Note: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 038416) is set to “1”. Also,
always be sure to set the event/trigger select bit (addresses 038316) to “00”.
Figure 1.43. Timer A0 mode register in event counter mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.16.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot
timer mode.
Table 1.16. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : Set value
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
The count reaches 000016
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer A0 register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer A0 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
TA0MR
Bit symbol
TMOD0
Address
039616
When reset
0016
Bit name
Function
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TA0IN pin's input signal (Note 3)
1 : Rising edge of TA0IN pin's input signal (Note 3)
MR2
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TMOD1
TCK1
1 0 : One-shot timer mode
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: Valid only when the TA0IN pin is selected by the event/trigger select bit
(addresses 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.44. Timer A0 mode register in one-shot timer mode
56
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A
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer
A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates.
Table 1.17. Timer specifications in pulse width modulation mode
Item
Specification
Count source
f1, f8, f32, fc32
Count operation
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
n / fi n : Set value
• Cycle time
(216-1) / fi fixed
8-bit PWM
• High level width n (m+1) / fi n : values set to timer A0 register’s high-order address
• Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
Count stop condition
• The count start flag is reset (= 0)
8
bits
PWM
•
Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
Interrupt
•
Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
request
generation 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
timing
• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116
TA0IN pin function
Programmable I/O port or trigger input
TA0OUT pin function
Pulse output
Read from timer
When timer A0 register is read, it indicates an indeterminate value
Write to timer
• When counting stopped :When a value is written to timer A0 register, it is
written to both reload register and counter
• When counting in progress : When a value is written to timer A0 register, it is
written to only reload register (Transferred to counter at next reload time)
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
1
Symbol
TA0MR
Bit symbol
TMOD0
TMOD1
Address
039616
When reset
0016
Bit name
Operation mode
select bit
Function
b1 b0
1 1 : PWM mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
MR0
1 (Must always be “1” in PWM mode)
MR1
External trigger select
bit (Note 1)
0: Falling edge of TA0IN pin's input signal (Note 2)
1: Rising edge of TA0IN pin's input signal (Note 2)
MR2
Trigger select bit
0: Count start flag is valid
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
b7 b6
TCK1
R W
Note 1: Valid only when the TA0IN pin is selected by the event/trigger select bit
(addresses 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output.
Figure 1.45. Timer A0 mode register in pulse width modulation mode
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TA0IN pin input signal) is selected
1 / fi X (2 16 – 1)
Count source
“H”
TA0IN pin
input signal
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output
from TA0OUT pin
“H”
Timer A0 interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFF16.
Figure 1.46. Example of how a 16-bit pulse width modulator operates
Condition :
Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TA0IN pin input signal) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
TA0IN pin input signal
“H”
“L”
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TA0OUT pin
“H”
Timer A0 interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 1.47. Example of how an 8-bit pulse width modulator operates
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.48 shows the block diagram of timer B. Figures 1.49 and 1.50 show the timer B-related registers.
Use the timer Bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode
: The timer counts an internal count source.
• Event counter mode
: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
Low-order 8 bits
f1
• Timer
• Pulse period/pulse width measurement
f8
f32
fC32
TBiIN
(i = 0, 1)
High-order 8 bits
Reload register (16)
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
Counter reset circuit
Can be selected in only
event counter mode
TBj overflow
(j = 1 when i = 0,
j = 0 when i = 1)
Figure 1.48. Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBiMR(i = 0, 1)
Bit symbol
TMOD0
When reset
00XX00002
Function
Bit name
Operation mode select bit
TMOD1
MR0
Address
039B16, 039C16
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
AAA
AAA
A
AA
A
AAA
AA
AAA
A
AAA
A
AAA
R
W
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1.
Note 3: Must set “00” to operation mode select bit of M30200.
Figure 1.49. Timer B-related registers (1)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
Address
039116, 039016
039316, 039216
Function
When reset
Indeterminate
Indeterminate
AA
AA
A
A
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF16
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note1: Read and write data in 16-bit units.
RW
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
000X00002
A
A
A
AA
A
AA
AA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAA
AA
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TX0S
Timer X0 count start flag
TX1S
Timer X1 count start flag
TX2S
Timer X2 count start flag
Function
R W
0 : Stops counting
1 : Starts counting
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
CDCS
Clock devided count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
R W
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAA
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
CPSR
Clock prescaler reset flag
Figure 1.50. Timer B-related registers (2)
60
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.18.) Figure 1.51 shows
the timer Bi mode register in timer mode.
Table 1.18. Timer specifications in timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TBiIN pin function
Read from timer
Write to timer
AA
A
AAA
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
The timer underflows
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 0
Symbol
TBiMR(i=0, 1)
Bit symbol
TMOD0
Address
039B16 to 039C16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
When reset
00XX00002
Function
b1 b0
0 0 : Timer mode
Invalid in timer mode
Can be “0” or “1”
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
MR3
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
AA
A
A
AA
AA
AA
A
AA
AA
R
W
Figure 1.51. Timer Bi mode register in timer mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.19.) Figure
1.52 shows the timer Bi mode register in event counter mode.
Table 1.19. Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
AA
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0 1
Symbol
TBiMR(i=0, 1)
Bit symbol
TMOD0
Address
039B16 to 039C16
Bit name
Function
Operation mode select bit
b1 b0
Count polarity select
bit (Note 1)
b3 b2
TMOD1
MR0
When reset
00XX00002
MR1
0 1 : Event counter mode
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
A
AA
A
AA
A
A
AA
R
W
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
MR3
Invalid in event counter mode.
This bit can neither be set nor reset. When read in event
counter mode, its content is indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock select
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow
( j = 1 when i = 0,
j = 0 when i = 1)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Figure 1.52. Timer Bi mode register in event counter mode
62
A
AA
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.20.)
Figure 1.53 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.54 shows the operation timing when measuring a pulse period. Figure 1.55 shows the operation timing
when measuring a pulse width.
Table 1.20. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Measurement pulse input
Read from timer
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 0
Symbol
TBiMR(i=0 , 1)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 , 039C16
When reset
00XX00002
Bit name
Function
Operation mode
select bit
b1 b0
Measurement mode
select bit
b3 b2
MR1
1 0 : Pulse period / pulse width
measurement mode
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
MR3
Timer Bi overflow
flag ( Note)
TCK0
Count source
select bit
TCK1
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
AA
AA
A
A
AA
A
A
AA
A
AA
AA
R
W
Note : The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Figure 1.53. Timer Bi mode register in pulse period/pulse width measurement mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
Timer Bi interrupt
request bit
“1”
Timer Bi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.54. Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.55. Operation timing when measuring a pulse width
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer X
Figure 1.56 shows the block diagram of timer X. Figures 1.57 to 1.59 show the timer X-related registers.
Use the timer Xi mode register bits 0 and 1 to choose the desired mode.
Timer X has the five operation modes listed as follows:
• Timer mode
: The timer counts an internal count source.
• Event counter mode
: The timer counts pulses from an external source or a timer overflow.
• One-shot timer mode
: The timer stops counting when the count reaches “000016”.
• Pulse period/pulse width measuring mode
: The timer measures an external signal's pulse period or
pulse width.
• Pulse width modulation (PWM) mode
: The timer outputs pulses of a given width.
AAA
AAA
A
A
Data bus high-order bits
Clock source
selection
• Timer
• One shot
• PWM
• Pulse period/pulse width measurement
f1
f8
f32
fC32
TXiINOUT
(i=0 to 2)
Data bus low-order bits
Low-order
8 bits
• Timer
(gate function)
High-order
8 bits
Reload register (16)
• Event counter
Counter (16)
Polarity
switching and
edge pulse
Clock selection
Count start flag
Counter reset circuit
TB1 overflow
External
trigger
*1
*1 = TA0, *2 = TX1 when TX0
*1 = TX0, *2 = TX2 when TX1
*1 = TX1, *2 = TA0 when TX2
*2
Pulse output
Toggle flip-flop
Figure 1.56. Block diagram of timer X
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TXiMR(i = 0 to 2) 039716 to 039916
Bit symbol
TMOD0
TMOD1
MR0
Function
Bit name
Operation mode
select bit
When reset
0016
b1 b0
Function varies with each operation mode
MR2
TCK1
W
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode or pulse period/
pulse width measurement mode
1 1 : Pulse width modulation (PWM) mode
MR1
MR3
TCK0
AAA
AAA
AAA
AA
A
AA
AAA
A
AAA
AAA
AAA
AAA
R
Count source select bit
(Function varies with each operation mode)
Figure 1.57. Timer X-related registers (1)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer Xi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TX0
TX1
TX2
Address
038916,038816
038B16,038A16
038D16,038C16
When reset
Indeterminate
Indeterminate
Indeterminate
Function
Values that can be set
• Timer mode
Counts an internal count source
000016 to FFFF16
• Event counter mode
000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
• Pulse period / pulse width measurement mode
Measures a pulse period or width
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FF16
(High-order
addresses)
0016 to FF16 (Loworder addresses)
AA
A
A
AA
AA
AA
A
A
AA
AA
RW
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
000X00002
A
A
A
AA
A
AA
AA
AAAAAAAAAAAAAAAA
A
AA
AA
AA
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
AA
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TX0S
Timer X0 count start flag
TX1S
Timer X1 count start flag
TX2S
Timer X2 count start flag
Function
0 : Stops counting
1 : Starts counting
Nothing is assigned.
When write, set "0" When read, their contents are indeterminate.
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
CDCS
Clock devided count start flag
Figure 1.58. Timer X-related registers (2)
66
0 : Stops counting
1 : Starts counting
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
One-shot start flag
Symbol
ONSF
b7 b6 b5 b4 b3 b2 b1 b0
Address
038216
When reset
XXXX00002
Bit symbol
Bit name
Function
TA0OS
Timer A0 one-shot start flag
TX0OS
Timer X0 one-shot start flag
TX1OS
Timer X1 one-shot start flag
TX2OS
Timer X2 one-shot start flag
1 : Timer start
When read, the value is “0”
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
AA
A
AA
A
A
A
A
AA
RW
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Bit symbol
TA0TGL
Address
038316
Bit name
Timer A0 event/trigger
select bit
TA0TGH
TX0TGL
Timer X0 event/trigger
select bit
TX0TGH
TX1TGL
Timer X1 event/trigger
select bit
TX1TGH
TX2TGL
Timer X2 event/trigger
select bit
TX2TGH
When reset
0016
Function
b1 b0
0 0 : Input on TA0IN is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
b3 b2
0 0 : Input on TX0INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
b5 b4
0 0 : Input on TX1INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
b7 b6
0 0 : Input on TX2INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
AA
A
A
AA
A
A
A
A
A
A
A
A
AA
A
A
AA
R W
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
When reset
0XXXXXXX2
Function
RW
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
AAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAA
A
AA
AAAAAAAAAAAAAAAA
CPSR
Clock prescaler reset flag
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
Figure 1.59. Timer X-related registers (3)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.21.) Figure 1.60 shows
the timer Xi mode register in timer mode.
Table 1.21. Specifications of timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TXiINOUT pin function
Read from timer
Write to timer
Select function
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
When the timer underflows
Programmable I/O port, gate input or pulse output
Count value can be read out by reading timer Xi register
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Counting can be started and stopped by the TXiINOUT pin’s input signal
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
Address
When reset
TXiMR(i = 0 to 2) 039716 to 039916
0016
Bit symbol
TMOD0
TMOD1
Bit name
Operation mode
select bit
Function
b1 b0
0 0 : Timer mode
AA
A
AA
A
AAA
AAA
AA
A
AAA
AA
A
AAA
MR0
Pulse output function
select bit
0 : Pulse is not output
(TXiINOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TXiINOUT pin is a pulse output pin)
MR1
Gate function select bit
b4 b3
RW
0 X (Note 2): Gate function not available
(TXiINOUT pin is a normal port pin)
1 0 : Timer counts only when TXiINOUT
pin is held “L” (Note 3)
1 1 : Timer counts only when TXiINOUT
pin is held “H” (Note 3)
MR2
MR3
0 (Must always be fixed to “0” in timer mode)
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). Gate function
cannot be selected when pulse output function is selected.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output
function cannot be selected when gate function is selected.
Figure 1.60. Timer Xi mode register in timer mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.22.) Figure
1.61 shows the timer Xi mode register in event counter mode.
Table 1.22. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signals input to TXiINOUT pin (effective edge can be selected by software)
• TB1 overflow, TA0 overflow, TXi overflow
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting (Note)
Divide ratio
1/ (n + 1)
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TXiINOUT pin function
Programmable I/O port, count source input or pulse output
Read from timer
Count value can be read out by reading timer Xi register
Write to timer
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
TXiMR(i = 0 to 2) 039716 to 039916
0 1
Bit symbol
Bit name
TMOD0
Operation mode select bit
When reset
0016
Function
b1 b0
0 1 : Event counter mode (Note 1)
TMOD1
A
A
A
A
AA
AA
A
A
A
A
AA
AA
MR0
Pulse output function
select bit
0 : Pulse is not output
(TXiINOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TXiINOUT pin is a pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Invalid in event counter mode.
Can be “0” or “1”.
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
select bit
TCK1
Invalid in event counter mode.
Can be “0” or “1”.
0 : Reload type
1 : Free-run type
R
RW
W
Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode.
Note 2: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not
selected as count source when pulse output function is selected.
Note 3: This bit is valid when only counting an external signal.
Figure 1.61. Timer Xi mode register in event counter mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.23.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode.
Table 1.23. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TXiINOUT pin function
Read from timer
Write to timer
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : Set value
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
The count reaches 000016
Programmable I/O port, trigger input or pulse output
When timer Xi register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Xi register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
1 0
Symbol
Address
When reset
TXiMR(i = 0 to 2) 039716 to 039916
0016
Bit symbol
TMOD0
Bit name
Operation mode
select bit
Function
b1 b0
AA
A
A
A
AA
A
A
A
AA
A
AA
A
A
A
A
A
A
AA
Pulse output function
select bit
1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
0 : Pulse is not output
(TXiINOOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TXiINOOUT pin is a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of TXiINOOUT pin's input signal (Note 3)
1 : Rising edge of TXiINOOUT pin's input signal (Note 3)
MR2
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select register (Note 4)
MR3
0 (Must always be “0” in one-shot timer mode)
TCK0
Count source select bit
TMOD1
MR0
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
RW
Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected
as count start condition when pulse output function is selected.
Note 2: Valid only when the TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). If
timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: Pulse output function cannot be selected when TXiINOUT pin is selected by the event/trigger select bit
(addresses 038316).
Figure 1.62. Timer Xi mode register in one-shot timer mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(4) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.24.)
Figure 1.63 shows the timer Xi mode register in pulse period/pulse width measurement mode. Figure
1.64 shows the operation timing when measuring a pulse period. Figure 1.65 shows the operation timing
when measuring a pulse width.
Table 1.24. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Xi overflow flag
changes to “1”. The timer Xi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Xi mode register.)
TXiINOUT pin function
Measurement pulse input
Read from timer
When timer Xi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
1 0
Symbol
Address
When reset
TXiMR(i = 0 to 2) 039716 to 039916
002
Bit symbol
TMOD0
TMOD1
Bit name
Operation mode
select bit
Function
b1 b0
1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
Measurement mode
select bit
b3 b2
MR
2
Timer Xi overflow
flag (Note)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
1 (Must always be “1” in pulse period / pulse width measurement mode)
TCK0
Count source
select bit
MR0
MR1
TCK1
AA
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
R W
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note: The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to
the timer Xi mode register. This flag cannot be set to “1” by software.
Figure 1.63. Timer Xi mode register in pulse period/pulse width measurement mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
Timer Xi interrupt
request bit
“1”
Timer Xi overflow flag
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.64. Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
Count start flag
“1”
“0”
Timer Xi interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Xi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.65. Operation timing when measuring a pulse width
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(5) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.25.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer
Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates.
Table 1.25. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down counts (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• "H" level width n / fi
n : Set value
• Cycle time
(216-1) / fi fixed
• "H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address
• Cycle time (28-1) (m+1) / fi m : values set to timer Xi register’s low-order address
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
• Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
• Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
• Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116
Pulse output
When timer Xi register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt
8 bits PWM
request
generation 16 bits PWM
timing
TXiINOUT pin function
Read from timer
Write to timer
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
1 1
1
Symbol
Address
When reset
TXiMR(i = 0 to 2) 039716 to 039916
0016
Bit symbol
TMOD0
TMOD1
Bit name
Operation mode
select bit
Function
b1 b0
1 1 : PWM mode
AA
AA
A
AA
A
AA
AA
AA
A
A
AA
AA
MR0
1 (Must always be “1” in PWM mode)
MR1
Invalid in PWM mode. Can be “0” or “1”.
MR2
Trigger select bit
0: Count start flag is valid
(Note 1)
1: Selected by event/trigger select register
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
R W
Note 1: TXiINOUT pin inout cannot be selected by the event/trigger select bit(addresses 038316).
Note 2: Set the corresponding port direction register to “1” (output mode).
Figure 1.66. Timer Xi mode register in pulse width modulation mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Condition : Reload register = 000316, when trigger (timer overflow) is selected
1 / fi X (2 16 – 1)
Count source
“H”
Trigger signal
“L”
Trigger is not generated by this signal
1 / fi X n
PWM pulse output
from TXiINOUT pin
“H”
Timer Xi interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note1: n = 000016 to FFFF16.
Figure 1.67. Example of how a 16-bit pulse width modulator operates
Condition :
Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
Trigger (timer overflow) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
“H”
Trigger signal
AAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAA
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TXiINOUT pin
“H”
Timer Xi interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FF16.
Figure 1.68. Example of how an 8-bit pulse width modulator operates
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1.
UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 1.69 shows the block diagram of UART0 and UART1. Figure 1.70 shows the block diagram of the
transmit/receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016 and
03A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART.
UART1 is used as a UART only.
Figures 1.71 through 1.73 show the registers related to UARTi.
(UART0)
RxD0
TxD0
UART reception
1/16
Clock source selection
f1
f8
f32
fC
Internal
Bit rate generator
1 / (m+1)
Clock synchronous type
1/16
UART transmission
Clock synchronous type
External
Reception
control circuit
Transmission
control circuit
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2
Clock synchronous type
(when internal clock is selected)
CLK0
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLKS
Clock output pin
select switch
(UART1)
RxD1
TxD1
Clock source selection
f1
f8
f32
fC
Bit rate generator
1/16
Reception
control circuit
1/16
Transmission
control circuit
Receive
clock
1 / (n+1)
Transmit/
receive
unit
Transmit
clock
m : Values set to UART0 bit rate generator (BRG0)
n : Values set to UART1 bit rate generator (BRG1)
Figure 1.69. Block diagram of UARTi (i = 0, 1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous
type
Clock
synchronous
PAR
type
disabled
1SP
RxDi
SP
SP
UART (7 bits)
UART (8 bits)
UARTi receive register
UART (7 bits)
PAR
UART
PAR
enabled
2SP
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive
buffer register
D1
D0
UARTi transmit
buffer register
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
UART (8 bits)
UART (9 bits)
UART (9 bits)
PAR
enabled
2SP
SP
SP
UART
Clock
synchronous
type
TxDi
PAR
1SP
Clock
PAR
disabled synchronous
type
“0”
UART (7 bits)
UART (8 bits)
UART (7 bits)
Clock
synchronous
type
Note: UART1 cannot be used in clock synchronous serial I/O.
Figure 1.70. Block diagram of transmit/receive unit
76
UARTi transmit register
SP: Stop bit
PAR: Parity bit
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
b0
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
A
Function
R W
Transmit data
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
UARTi receive buffer register
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
b0
Bit
symbol
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
Function (During clock
synchronous serial I/O
mode)
Bit name
Receive data
A
A
A
A
A
A
Function
(During UART mode)
Receive data
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
OER
Overrun error flag
(Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag
(Note)
Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag
(Note)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag
(Note)
Invalid
0 : No error
1 : Error found
R W
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set
to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is
read out.
UARTi bit rate generator
b7
Symbol
U0BRG
U1BRG
b0
Address
03A116
03A916
Function
Assuming that set value = n, BRGi divides the
count source by n + 1
When reset
Indeterminate
Indeterminate
Values that can be set
0016 to FF16
A
RW
Figure 1.71. Serial I/O-related registers (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Bit
symbol
Address
03A016, 03A816
Bit name
SMD0 Serial I/O mode select bit
(Note 1)
SMD1
SMD2
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
Function
(During UART mode)
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
select bit (Note 2)
0 : Internal clock
1 : External clock
0 : Internal clock
1 : External clock
STPS
Stop bit length select bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity select bit Invalid
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: UART1 can use only internal clock. Must set this bit to “1”.
A
A
A
A
A
A
A
A
A
R W
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
1
0
Symbol
UiC0(i=0,1)
Bit
symbol
CLK0
Address
When reset
0816
03A416, 03AC16
Bit name
BRG count source
select bit
CLK1
Function (Note)
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
b1 b0
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : fc is selected
Set this bit to “0”.
TXEPT
Transmit register empty
flag
0 : Data present in transmit
0 : Data present in transmit register
register (during transmission)
(during transmission)
1 : No data present in transmit
1 : No data present in transmit
register (transmission
register (transmission completed)
completed)
Set this bit to “1”.
NCH
Data output select bit
CKPOL
CLK polarity select bit
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Note: UART1 cannot be used in clock synchronous serial I/O.
Figure 1.72. Serial I/O-related registers (2)
78
Must always be “0”
A
A
A
A
A
AA
A
AA
A
AA
AA
AA
AA
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
Symbol
UiC1(i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
symbol
Address
03A516,03AD16
When reset
0216
Function (Note 1)
(During clock synchronous
serial I/O mode)
Bit name
AA
A
AA
AA
A
AA
A
AA
Function
(During UART mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
(Note 2)
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
RW
Nothing is assigned.
When write, set "0". When read, the value of these bits is “0”.
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when
RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then
receive operation starts immediately.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Bit
symbol
U0IRS
Address
03B016
Bit
name
UART0 transmit
interrupt cause select bit
When reset
XX0000002
Function
(During clock synchronous
serial I/O mode)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS
UART1 transmit
interrupt cause select bit
Set this bit to “0”.
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
Invalid
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note 2)
0 : Normal mode
Must always be “0”
Set this bit to “0”.
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
R W
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
U0RRM UART0 continuous
receive mode enable bit
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
Function
(During UART mode)
Nothing is assigned.
When write, set "0". When read, its content is indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”.
Figure 1.73. Serial I/O-related registers (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table
1.26.) Figure 1.65 shows the UART0 transmit/receive mode register.
Table 1.26. Specifications of clock synchronous serial I/O mode
Specification
Item
Transfer data format
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1)
Transfer clock
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin
• To start transmission, the following requirements must be met:
Transmission start
_ Transmit enable bit (bit 0 at address 03A516) = “1”
condition
_ Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
Reception start
• To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03A516) = “1”
conditio
_ Transmit enable bit (bit 0 at address 03A516) = “1”
_ Transmit buffer empty flag (bit 1 at address 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_ CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
• When transmitting
Interrupt request
_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts regeneration timing
quested when data transfer from UART0 transfer buffer register to UART0 transmit
register is completed
_ Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts requested when data transmission from UART0 transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UART0 receive register to U A R T 0
receive buffer register is completed
• Overrun error (Note 2)
Error detection
This error occurs when the next data is ready before contents of UART0 r e c e i v e
buffer register are read out
• CLK polarity selection
Select function
Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART0 transfer clock can be chosen by software to be output from one of the two
pins set
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the
UART0 receive interrupt request bit is not set to “1”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
UART0 transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
U0MR
0 0 1
Bit symbol
SMD0
Address
03A016
Bit name
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
Internal/external clock
select bit
Function
b2 b1 b0
0 0 1 : Clock synchronous serial
I/O mode
0 : Internal clock
1 : External clock
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
AA
A
A
A
AA
A
AA
AA
A
A
A
AA
A
AA
RW
0 (Must always be “0” in clock synchronous serial I/O mode)
Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode
Table 1.27 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin
outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.27. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxD0
(P50)
Serial data output
Port P50 direction register (bit 0 at address 03EB16)= “1”
(Outputs dummy data when performing reception only)
RxD0
(P51)
Serial data input
Port P51 direction register (bit 1 at address 03EB16)= “0”
(Can be used as an input port when performing transmission only)
CLK0
(P52)
Transfer clock output
Internal/external clock select bit (bit 3 at address 03A016) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016) = “1”
Port P52 direction register (bit 2 at address 03EB16) = “0”
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
“0”
Data is set in UART0 transmit buffer
register
“1”
Transmit buffer
empty flag (Tl)
“0”
Transferred from UART0 transmit buffer register to UART0
transmit register
TCLK
Stopped pulsing because transfer enable bit = “0”
CLK0
D 0 D1 D 2 D 3 D 4 D 5 D 6 D 7 D0 D1 D 2 D3 D4 D5 D6
TxD0
Transmit
register empty
flag (TXEPT)
D7
D0 D1 D2 D3 D4 D5 D6 D7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRG0 count source (f1, f8, f32, fc)
n: value set to BRG0
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
“0”
“1”
Dummy data is set in UART0 transmit buffer register
“1”
Transferred from UART0 transmit buffer register to UART0 transmit register
1 / fEXT
CLK0
Receive data is taken in
D 0 D1 D 2 D 3 D 4 D 5 D 6 D 7
RxD0
Transferred from UART0 receive register
“1”
to UART0 receive buffer register
D0 D1 D2
D3 D4 D 5
Read out from UART0 receive buffer register
Receive complete
flag (Rl)
“0”
Receive interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UART0 transmit buffer register
fEXT: frequency of external clock
Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.76, the CLK polarity select bit (bit 6 at addresses 03A416) allows selection of the
polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLK0 pin level when not
transferring data is “H”.
• When CLK polarity select bit = “1”
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
RXD0
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLK0 pin level when not
transferring data is “L”.
Figure 1.76. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.77, when the transfer format select bit (bit 7 at addresses 03A416) = “0”, the
transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK0
TXD0
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
R XD 0
D0
D1
D2
D3
D4
D5
D6
D7
• When transfer format select bit = “1”
CLK0
TXD0
D7
D6
D5
D4
D3
D2
D1
D0
R XD 0
D7
D6
D5
D4
D3
D2
D1
D0
MSB first
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.77. Transfer format
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The
multiple pins function is valid only when the internal clock is selected for UART0.
Microcomputer
TXD0 (P50)
CLKS (P53)
CLK0 (P52)
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.78. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.28.) Figure 1.79 shows the UARTi transmit/receive mode register.
Table 1.28. Specifications of UART Mode
Item
Transfer data format
Transfer clock
Transmission start
condition
Reception start condition
Interrupt request generation timing
Error detection
Select function
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
• When external clock is selected (bit 3 at addresses 03A016=“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
• Sleep mode selection
This mode is used to transfer data to and from one of multiple slave microcomputers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to “1”.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Bit symbol
SMD0
Address
03A016, 03A816
Bit name
Function
Serial I/O mode select bit
SMD1
SMD2
CKDIR
When reset
0016
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit (Note)
Stop bit length select bit
0 : Internal clock
1 : External clock
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep select bit
0 : Sleep mode deselected
1 : Sleep mode selected
STPS
Note: UART1 can use only internal clock. Must set this bit to “1”.
A
A
A
A
A
A
A
A
RW
Figure 1.79. UARTi transmit/receive mode register in UART mode
Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.)
Table 1.29. Input/output pin functions in UART mode
Pin name
86
Function
Method of selection
TxDi
(P50, P40)
Serial data output
Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at
address 03EA16)= “1”
(Can be used as an input port when performing reception only)
RxDi
(P51, P42)
Serial data input
Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at
address 03EA16)= “0”
(Can be used as an input port when performing transmission only)
CLK0
(P52)
Programmable I/O port
Internal/external clock select bit (bit 3 at address 03A016) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016) = “1”
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register.
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
Stop
bit
SP
Stopped pulsing because transmit enable bit = “0”
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1
SP
Transmit register “1”
empty flag
“0”
(TXEPT)
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32, fc)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UARTi transmit buffer register
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
TxDi
Stop
bit
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit register
empty flag
(TXEPT)
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• Transmit interrupt cause select bit = “0”.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
n : value set to BRGi
Figure 1.80. Typical transmit timings in UART mode
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
Receive enable bit
“1”
“0”
Stop bit
Start bit
RxDi
D1
D0
D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
Receive interrupt
request bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Transferred from UARTi receive register to
UARTi receive buffer register
“0”
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
Figure 1.81. Typical receive timing in UART mode
(a) Sleep mode
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.30 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D
converter, and Figures 1.83 and 1.84 show the A-D converter-related registers.
Table 1.30. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
±3LSB
VCC = 3V • Without sample and hold function (8-bit resolution)
±2LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8 pins (AN0 to AN7) + 5 pins (AN50 to AN54)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the φAD frequency to 250kHz min.
With the sample and hold function, set the φAD frequency to 1MHz min.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
φAD
CKS0=1
fAD
1/2
1/2
CKS0=0
CKS1=0
A-D conversion rate
selection
V REF
VCUT=0
Resistor ladder
AV SS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016)
A-D register 0(16)
(03C316, 03C216)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03C516, 03C416)
(03C716, 03C616)
(03C916, 03C816)
A-D register 4(16)
(03CB16, 03CA16)
(03CD16, 03CC16)
A-D register 5(16)
A-D register 6(16)
(03CF16, 03CE16)
A-D register 7(16)
Vref
Decoder
VIN
Data bus high-order
Data bus low-order
Port P6 group
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
ADGSEL0=0
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Port P5 group
P50/AN50
P51/AN51
P52/AN52
P53/AN53
P54/AN54
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
Figure 1.82. Block diagram of A-D converter
90
ADGSEL0=1
Comparator
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
CH0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
b4 b3
CH1
CH2
MD0
MD1
(Note 2)
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Set this bit to “0”.
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
AA
A
A
AA
A
AA
AA
A
AA
A
A
AA
A
AA
A
AA
A
AA
RW
b2 b1 b0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
RW
When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
(Note 2, 3)
MD2
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
0 : Vref not connected
1 : Vref connected
VCUT
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If the repeat sweep mode is selected for the port P5 group, the contents of A-D
registers 5 to 7 are indeterminate.
Figure 1.83. A-D converter-related registers (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
Address
When reset
ADCON2
03D416
XXXX00002
Bit symbol
SMP
Bit name
A-D conversion method
select bit
Reserved bit
Function
0 : Without sample and hold
1 : With sample and hold
Always set to “0”
Nothing is assigned.
When write, set "0". When read, their content is indeterminate.
A
A
A
A
AA
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
A-D register i
(b15)
b7
(b8)
b0 b7
ADi(i=0 to 7)
Address
When reset
03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
When write, set "0". When read, their content is
indeterminate.
Figure 1.84. A-D converter-related registers (2)
92
A
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A
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. (See Table 1.31.) Figure 1.85 shows the A-D control register in one-shot mode.
Table 1.31. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected (Note)
Reading of result of A-D converter Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
CH0
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
b4 b3
0 0 : One-shot mode
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
CH1
CH2
MD0
MD1
Set this bit to “0”.
AA
A
A
AA
A
AA
A
AA
AA
A
A
AA
A
AA
RW
b2 b1 b0
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin select bit
Invalid in one-shot mode
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
SCAN0
SCAN1
MD2
BITS
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
A
AA
A
AA
A
AA
A
AA
AA
A
AA
A
AA
A
A
AA
A
AA
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.85. A-D conversion register in one-shot mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
(See Table 1.32.) Figure 1.86 shows the A-D control register in repeat mode.
Table 1.32. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected (Note)
Reading of result of A-D converter Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 0 1
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin select bit
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
A-D operation mode
select bit 0
b4 b3
0 1 : Repeat mode
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
CH0
CH1
CH2
MD0
MD1
Set this bit to “0”.
A
A
A
A
A
A
A
RW
b2 b1 b0
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
Function
Invalid in repeat mode
SCAN1
MD2
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
BITS
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
A
A
A
A
A
A
A
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.86. A-D conversion register in repeat mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. (See Table 1.33.) Figure 1.87 shows the A-D control register in single sweep mode.
Table 1.33. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Start condition
Writing “1” to A-D converter start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”.)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note)
Reading of result of A-D converter Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0
Symbol
ADCON0
Address
03D616
Bit symbol
Bit name
CH0
Analog input pin select bit
When reset
00000XXX2
AA
AAAA
AAAA
AA
AAAA
Function
RW
Invalid in single sweep mode
CH1
CH2
MD0
A-D operation mode
select bit 0
MD1
Set this bit to “0”.
b4 b3
1 0 : Single sweep mode
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
VCUT
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
AAAA
AA
AAAA
AAAA
AA
AAAA
RW
When single sweep and repeat sweep
mode 0 are selected
(Note 2, 3)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, do not select 6 pins and 8 pins sweep mode.
Figure 1.87. A-D conversion register in single sweep mode
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. (See Table 1.34.) Figure 1.88 shows the A-D control register in repeat sweep mode 0.
Table 1.34. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
Bit symbol
Bit name
Function
CH0
Analog input pin select bit
Invalid in repeat sweep mode 0
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
RW
CH1
CH2
MD0
b4 b3
MD1
Set this bit to “0”.
AAAA
AAAA
AA
AA
AAAA
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
0
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
VCUT
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
AAAA
AAAAA
AAA
AA
A
AAAA
AA
AA
RW
When single sweep and repeat sweep
mode 0 are selected
(Note 2, 3)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
Figure 1.88. A-D conversion register in repeat sweep mode 0
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using
the A-D sweep pin select bit. (See Table 1.35.) Figure 1.89 shows the A-D control register in repeat sweep mode
1. 1.35. Repeat sweep mode 1 specifications
Table
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note)
Reading of result of A-D converter Read A-D register corresponding to selected pin (at any time)
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0 1 1
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
Bit symbol
Bit name
Function
CH0
Analog input pin select bit
Invalid in repeat sweep mode 1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency select bit 0
0 : fAD/4 is selected
1 : fAD/2 is selected
CH1
CH2
MD0
AA
A
AAA
AA
A
AA
A
AAA
AA
A
AAA
AAA
RW
b4 b3
MD1
Set this bit to “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0 1
1
Symbol
ADCON1
Bit symbol
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
SCAN0
Function
b1 b0
0 0 : AN0 (1 pins)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
A-D operation mode
select bit 1
Set “1” in this mode.
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
VCUT
Vref connect bit
1 : Vref connected
MD2
BITS
Set this bit to “0”.
ADGSEL0
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
AA
A
AA
A
AA
A
AA
A
AA
A
AAA
AA
A
AA
A
AA
A
AAA
RW
When single sweep and repeat sweep
mode 1 are selected
(Note 2, 3)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
Figure 1.89. A-D conversion register in repeat sweep mode 1
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
• Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is
achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output
using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the
drive capacity of its N-channel output transistor to be set as necessary.
Figures 1.90 to 1.92 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs
regardless of the contents of the direction registers. See the descriptions of the respective functions for how
to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.93 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.94 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.95 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
(4) Port P1 drive capacity control register
Figure 1.95 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in
this register corresponds one for one to the port pins.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P30 to P35
Data bus
Port latch
Pull-up selection
P00 to P07, P42, P71
Direction register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P41, P70
Data bus
Port latch
output
Pull-up selection
Direction register
P40, P43, P44
Data bus
Port latch
output
Input to respective peripheral functions
Figure 1.90. Programmable I/O ports (1)
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
P10 to P17
Direction register
Data bus
Port latch
Drive capacity control register
Pull-up selection
P51
Direction register
Data bus
Port latch
Analog input
Serial I/O input
Pull-up selection
Direction register
P50, P53, P54
Data bus
Port latch
output
Analog input
Pull-up selection
Direction register
P52
Data bus
Port latch
output
Analog input
Serial clock input
Figure 1.91. Programmable I/O ports (2)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P60 to P67
Data bus
Port latch
Analog input
Figure 1.92. Programmable I/O ports (3)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PDi (i = 0 to 7)
Bit symbol
Address
03E216, 03E316, 03E716, 03EA16,
03EB16, 03EE16, 03EF16
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
PDi_4
Port Pi3 direction register
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
Function
When reset
0016
0016
AA
AA
A
A
A
AA
A
AA
AA
A
A
AA
RW
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7 except 2)
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the
port P4 direction register.
Note 2: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57,
P72 to P77. These bits can either be set nor reset. When read, its contents
are indeterminate.
Figure 1.93. Direction register
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Pi (i = 0 to 7)
Bit symbol
Address
03E016, 03E116, 03E516, 03E816,
03E916, 03EC16, 03ED16
Bit name
Pi_0
Port Pi0 register
Pi_1
Pi_2
Port Pi1 register
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
When reset
Indeterminate
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
1 : “H” level data
(i = 0 to 7 except 2)
A
AA
AA
RW
Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to
P77. This bit can either be set nor reset. When read, its content is indeterminate.
Figure 1.94. Port register
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
Bit symbol
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU06
P30 to P33 pull-up
PU07
P34 to P35 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
AAA
A
AAA
A
AA
AAAAAA
AA
RW
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
Bit symbol
Bit name
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P53 pull-up
PU13
P54 pull-up
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
PU16
P70 to P71 pull-up
When reset
0016
Function
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
AAA
AAAAAA
AA
AAA
A
AAA
A
A
R W
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRR
Bit symbol
Address
03FE16
Bit name
DRR0
Port P10 drive capacuty
DRR1
Port P11 drive capacuty
DRR2
DRR3
Port P12 drive capacuty
Port P13 drive capacuty
DRR4
Port P14 drive capacuty
DRR5
Port P15 drive capacuty
DRR6
Port P16 drive capacuty
DRR7
Port P17 drive capacuty
When reset
0016
Function
Set P1 N-channel output
transistor drive capacity
0 : LOW
1 : HIGH
AAA
A
AAAA
AAA
AA
A
AAAAAA
R W
Figure 1.95. Pull-up control register
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Example connection of unused pins
Table 1.36. Example connection of unused pins
Pin name
Connection
Ports P0, P1, P3 to P7
After setting for input mode, connect every pin to VSS (pull-down); or
after setting for output mode, leave these pins open.
XOUT (Note)
Open
AVCC
Connect to VCC
AVSS, VREF
Connect to VSS
Note: With external clock input to XIN pin.
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Usage precaution
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage Precaution
Timer A (timer mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading
the timer A0 register after setting a value in the timer A0 register with a count halted but before the
counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by underflow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0
register with a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TA0OUT pin outputs “L” level.
• The interrupt request generated and the timer A0 interrupt request bit goes to “1”.
(2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TA0OUT pin is outputting an “H” level in this instance, the output level goes to “L”,
and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this
instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
Timer X (timer mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the
timer A0 register after setting a value in the timer Xi register with a count halted but before the counter
starts counting gets a proper value.
Timer X (event counter mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer X (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TXiINOUT pin outputs “L” level.
• The interrupt request generated and the timer Xi interrupt request bit goes to “1”.
(2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Usage precaution
Timer X (pulse width modulation mode)
(1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TXiINOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this
instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”.
Timer X (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Xi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT
instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore,
insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits
to “1”.
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Usage precaution
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to
“0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a
value in the stack pointer before accepting an interrupt.
Concerning the first instruction immediately after reset, generating any interrupt is prohibited.
(3) External interrupt
________
________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear
the interrupt request bit after changing the polarity.
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
Electrical characteristics
Table 1.37. Absolute maximum ratings
Symbol
Parameter
Condition
Rated value
Unit
- 0.3 to 7
V
V
Vcc
AVcc
Supply voltage
VI
Input voltage
RESET, CNVss, P00 to P07, P10 to P17, P30 to P35,
P40 to P45, P50 to P54, P60 to P67,
P70, P71, VREF, XIN
- 0.3 to Vcc + 0.3
(Note 1)
V
VO
Output voltage
P00 to P07, P10 to P17, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71, VREF, XIN
- 0.3 to Vcc + 0.3
V
Analog supply voltage
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
Note 1: When writing to frash MCU, CNVss is –0.3 to 13 (V) .
Note 2: Flat package (56P6S-A) is 300 mW.
- 0.3 to 7
Ta = 25 °C
1000 (Note 2)
mW
- 20 to 85 (Note 3)
°C
- 40 to 150 (Note 4)
°C
Note 3: Extended operating temperature version: -40 to 85 °C.
Note 4: Extended operating temperature version: -65 to 150 °C.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.38. Recommended operating conditions (Note 1)
Symbol
Vcc
Parameter
Min
Supply voltage (Note 2)
Standard
Typ.
Max.
Mask ROM version
2.7
5.0
5.5
Flash memory version
4.0
5.0
5.5
Unit
V
AVcc
Vss
Analog supply voltage
Supply voltage
Vcc
0
V
V
AVss
Analog supply voltage
0
V
VIH
HIGH input voltage P00 to P07, P10 to P17, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS,
0.8Vcc
Vcc
V
V IL
LOW input voltage P00 to P07, P10 to P17, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71, XIN, RESET, CNVSS
0
0.2Vcc
V
- 10.0
mA
10.0
mA
I OH (peak) HIGH peak output P00 to P07, P10 to P17, P30 to P35, P40 to P45,
current
P50 to P54, P60 to P67, P70, P71
I OL (peak) LOW peak output
current
P00 to P07, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71
I OL (peak)
LOW peak output
current
P10 to P17
I OH (avg)
HIGH average output
current
I OL (avg)
I OL (avg)
f (XIN)
HIGHPOWER
30.0
LOWPOWER
10.0
mA
P00 to P07, P10 to P17, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71
- 5.0
mA
LOW average output
current
P00 to P07, P30 to P35, P40 to P45,
P50 to P54, P60 to P67, P70, P71
5.0
mA
LOW average output
current
P10 to P17
Main clock input
oscillation
frequency
Mask ROM version
Without
wait
15.0
LOWPOWER
5.0
10
5 x VCC
- 10.000
Vcc=4.0V to 5.5V
0
Vcc=2.7V to 4.0V
0
Flash memory version Vcc=4.0V to 5.5V
0
Vcc=4.0V to 5.5V
0
Vcc=2.7V to 4.0V
0
Flash memory version Vcc=4.0V to 5.5V
0
Mask ROM version
With wait
HIGHPOWER
10
10
mA
MHz
MHz
MHz
MHz
2.31 x VCC MHz
+0.760
10
MHz
AAA
AAA
AAA
Main clock input oscillation frequency
(Without wait)
10.0
5 x Vcc - 10.000MHz
3.5
0.0
2.7
4.0
Power supply voltage [V]
(Main clock : no division)
112
5.5
Highest operation frequency [MHz]
Highest operation frequency [MHz]
f (XcIN) Subclock oscillation frequency
kHz
32.768
50
Note 1: Unless otherwise noted: VCC = 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to
85oC). Flash version: VCC = 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC.)
Note 2: Flash version: VCC = 4.0V to 5.5V
Note 3: The average output current is an average value measured over 100ms.
Note 4: Keep output current as follows:
The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3
and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6
and P7 IOH (peak) is under 80 mA.
AAA
AAA
AAA
Main clock input oscillation frequency
(With wait)
10.0
7.0
0.0
2.31 x VCC + 0.760MHz
2.7
4.0
Power supply voltage [V]
(Main clock : no division)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.39. Electrical characteristics (Note1)
Symbol
Parameter
Measuring condition
Min.
Standard
Unit
Typ. Max.
VOH
HIGH output
voltage
P00 to P07,P10 to P17,P30 to P35,
P40 to P45,P50 to P54,P60 to P67,P70,P71
VOH
HIGH output
voltage
P00 to P07,P10 to P17,P30 to P35,
IOH = - 200 µA
P40 to P45,P50 to P54,P60 to P67, P70,P71
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
VOL
LOW output
voltage
P00 to P07,P30 to P35,P40 to P45
P50 to P54,P60 to P67,P70,P71
IOL = 5 mA
2.0
V
VOL
LOW output
voltage
P00 to P07,P30 to P35,P40 to P45
P50 to P54,P60 to P67,P70,P71
IOL = 200 µA
0.45
V
VOL
LOW output
voltage
P10 to P17
HIGHPOWER
IOL = 15mA
2.0
LOWPOWER
IOL = 5 mA
2.0
HIGHPOWER
LOWPOWER
IOL = 200 µA
0.3
IOL = 200 µA
0.45
HIGHPOWER
IOH = 1 mA
2.0
LOWPOWER
IOH = 0.5 mA
2.0
HIGHPOWER
No load
0
LOWPOWER
No load
0
VOH
VOH
VOL
LOW output
voltage
P10 to P17
VOL
LOW output
voltage
XOUT
VOL
VT+ -VT-
LOW output
voltage
Hysteresis
XOUT
IOH = - 5 mA
3.0
V
4.7
V
HIGHPOWER
IOH = - 1 mA
3.0
LOWPOWER
IOH = - 0.5 mA
3.0
HIGHPOWER
No load
3.0
LOWPOWER
No load
1.6
V
V
V
V
V
V
TA0IN,TX0INOUT,TX1INOUT,TX2INOUT
TB0IN,TB1IN INT0,INT1,CLK0,KI0 to KI7
0.2
0.8
V
0.2
1.8
V
5.0
µA
-5.0
µA
50.0 167.0
kΩ
RxD0, RxD1
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P30 to P35,
P40 to P45,P50 to P54,P60 to P67
P70,P71, RESET, CNVss
LOW input
current
P00 to P07,P10 to P17,P30 to P35,
P40 to P45,P50 to P54,P60 to P67,
P70,P71, RESET, CNVss
RPULLUP
Pull-up
resistor
P00 to P07,P10 to P17,P30 to P35,
VI = 0V
P40 to P45,P50 to P54,P60 to P67,P70,P71
RXIN
Feedback resistor
XIN
RXCIN
Feedback resistor
XCIN
IIL
V RAM
Icc
RAM retention voltage
Power supply current
VI = 5V
VI = 0V
30.0
When clock is stopped
I/O pin
has no
load
1.0
MΩ
6.0
MΩ
2.0
V
f(XIN)=10MHz
Square wave, no division
19.0
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
With wait(Note2)
Ta=25 C when
clock is stopped
90.0
µA
4.0
µA
Ta=85 C when clock
is stopped
38.0
mA
1.0
µA
20.0
Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN) = 10MHz)
Note 2: With one timer operated using fC32.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.40. A-D conversion characteristics
Symbol
–
–
Parameter
Resolution
Absolute Sample & hold function not available
accuracy Sample & hold function available(10bit)
Sample & hold function available(8bit)
RLADDER
Ladder resistance
tCONV
tCONV
tSAMP
VREF
VIA
Conversion time(10bit)
114
Conversion time(8bit)
Sampling time
Reference voltage
Analog input voltage
Measuring condition
Min.
Standard
Typ. Max.
Unit
10
±3
±3
Bits
LSB
LSB
VREF = VCC = 5V
±2
LSB
VREF =VCC
40
kohm
3.3
2.8
0.3
2
VCC
µs
µs
µs
V
0
VREF
V
VREF =VCC
VREF =VCC = 5V
VREF =VCC= 5V
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.41. External clock input
Symbol
Parameter
Standard
Min.
Max.
tc
External clock input cycle time
tw(H)
tw(L)
tr
tf
External clock input HIGH pulse width
100
40
External clock input LOW pulse width
40
External clock rise time
ns
15
15
External clock fall time
Unit
ns
ns
ns
ns
Table 1.42. Timer A input (counter input in event counter mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
TA0IN input HIGH pulse width
100
40
ns
tw(TAH)
tw(TAL)
TA0IN input LOW pulse width
40
ns
ns
Table 1.43. Timer A input (gating input in timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
400
ns
tw(TAH)
tw(TAL)
TA0IN input HIGH pulse width
200
200
ns
ns
TA0IN input LOW pulse width
Table 1.44. Timer A input (external trigger input in one-shot timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
200
ns
tw(TAH)
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
100
100
ns
tw(TAL)
ns
Table 1.45. Timer A input (external trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
Parameter
Standard
Min.
Max.
100
100
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
Unit
ns
ns
Table 1.46. Timer A input (up/down input in event counter mode)
Parameter
Symbol
tc(UP)
TA0OUT input cycle time
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TA0OUT input HIGH pulse width
TA0OUT input LOW pulse width
TA0OUT input setup time
TA0OUT input hold time
Standard
Min.
Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.47. Timer B input (counter input in event counter mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time (counted on one edge)
tw(TBH)
tw(TBL)
Standard
Min.
Max.
Unit
100
ns
TBiIN input HIGH pulse width (counted on one edge)
40
ns
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
40
200
ns
tc(TB)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
80
ns
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
80
ns
Table 1.48. Timer B input (pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
200
ns
200
ns
tw(TBL)
Table 1.49. Timer B input (pulse width measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
tw(TBH)
TBiIN input cycle time
400
TBiIN input HIGH pulse width
200
ns
ns
tw(TBL)
TBiIN input LOW pulse width
200
ns
Table 1.50. Timer X input (counter input in event counter mode)
Symbol
tc(TX)
tw(TXH)
tw(TXL)
Parameter
TXiINOUT input cycle time
Standard
Min.
Max.
Unit
100
ns
40
ns
40
ns
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
Table 1.51. Timer X input (gate input in timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TX)
tw(TXH)
TXiINOUT input HIGH pulse width
400
200
ns
ns
tw(TXL)
TXiINOUT input LOW pulse width
200
ns
TXiINOUT input cycle time
Table 1.52. Timer X input (external trigger input in one-shot timer mode)
Symbol
116
tc(TX)
tw(TXH)
tw(TXL)
Parameter
Standard
Min.
Max.
Unit
TXiINOUT input HIGH pulse width
200
100
ns
ns
TXiINOUT input LOW pulse width
100
ns
TXiINOUT input cycle time
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.53. Timer X input (pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TX)
TXiINOUT input cycle time
400
ns
tw(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
200
ns
200
ns
tw(TXL)
Table 1.54. Timer X input (pulse width measurement mode)
Symbol
tc(TX)
tw(TXH)
tw(TXL)
Parameter
Standard
Min.
Max.
Unit
TXiINOUT input cycle time
400
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
200
ns
ns
200
ns
Table 1.55. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
tw(CKH)
CLK0 input cycle time
CLK0 input HIGH pulse width
200
100
ns
ns
tw(CKL)
CLK0 input LOW pulse width
100
ns
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
TxDi output delay time
80
TxDi hold time
RxDi input setup time
RxDi input hold time
0
30
90
ns
ns
ns
ns
_______
Table 1.56. External interrupt INTi inputs
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
Max.
250
250
Unit
ns
ns
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
tc(TA)
tw(TAH)
TA0IN input
tw(TAL)
tc(UP)
tw(UPH)
TA0OUT input
tw(UPL)
TA0OUT input
(Up/down input)
During event counter mode
TA0IN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(TX)
tw(TXH)
TXiINOUT input
tw(TXL)
tc(CK)
tw(CKH)
CLK0
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
118
tw(INH)
th(C–D)
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.57. Electrical characteristics (Note 1)
Symbol
Parameter
Measuring condition
Min.
Standard
Unit
Typ. Max.
VOH
HIGH output
voltage
P00 to P07,P10 to P17,P30 to P35,
IOH = - 1mA
P40 to P45,P50 to P54,P60 to P67,P70,P71
2.5
VOH
HIGH output
voltage
HIGHPOWER
IOH = - 1 mA
2.5
XOUT
LOWPOWER
IOH = - 50 µA
2.5
HIGH output
voltage
HIGHPOWER
No load
3.0
XCOUT
LOWPOWER
No load
1.6
LOW output
voltage
P00 to P07,P30 to P35,P40 to P45
P50 to P54,P60 to P67,P70,P71
LOW output
voltage
P10 to P17
LOW output
voltage
XOUT
VOH
VOL
VOL
VOL
VOL
VT+ -VT-
LOW output
voltage
Hysteresis
V
V
V
IOL = 1 mA
0.5
HIGHPOWER
IOL = 3 mA
0.5
LOWPOWER
IOL = 1 mA
0.5
HIGHPOWER
IOH = 0.1 mA
0.5
LOWPOWER
IOH = 50 µA
0.5
HIGHPOWER
No load
0
LOWPOWER
No load
0
XOUT
V
V
V
V
TA0IN,TX0INOUT,TX1INOUT,TX2INOUT
TB0IN,TB1IN INT0,INT1,CLK0,KI0 to KI7
RxD0, RxD1
0.2
0.8
V
0.2
1.8
V
VT+ -VT-
Hysteresis
RESET
IIH
HIGH input
current
P00 to P07,P10 to P17,P30 to P35,
P40 to P45,P50 to P54,P60 to P67,
P70,P71, RESET, CNVss
VI = 3V
4.0
µA
LOW input
current
P00 to P07,P10 to P17,P30 to P35,
P40 to P45,P50 to P54,P60 to P67,
P70,P71, RESET, CNVss
VI = 0V
-4.0
µA
RPULLUP
Pull-up
resistor
P00 to P07,P10 to P17,P30 to P35,
VI = 0V
P40 to P45,P50 to P54,P60 to P67,P70,P71
500.0
kΩ
RXIN
Feedback resistor
XIN
RXIN
Feedback resistor
XIN
V RAM
RAM retention voltage
IIL
66.0
When clock is stopped
f(XIN)=7MHz
Square wave, no division
f(XCIN)=32kHz
Square wave
Icc
Power supply current
I/O pin
has no
load
120.0
3.0
MΩ
10.0
MΩ
2.0
V
6.0
15.0
mA
40.0
µA
f(XCIN)=32kHz
With wait.
Oscillation capacity HIGH (Note 2)
2.8
µA
f(XCIN)=32kHz
With wait.
Oscillation capacity LOW (Note 2)
0.9
µA
Ta=25 C when
clock is stopped
1.0
Ta=85 C when clock
is stopped
20.0
µA
Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHz, with wait)
Note 2: With one timer operated using fC32.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.58. A-D conversion characteristics
Symbol
Parameter
Measuring condition
Resolution
Absolute Sample & hold function not available
accuracy (8bit)
VREF =VCC = 3V,
ØAD = fAD/2
RLADDER
Ladder resistance
VREF =VCC
tCONV
Conversion time(8bit)
VREF
VIA
Reference voltage
–
–
120
Analog input voltage
Min.
Standard
Typ. Max.
VREF =VCC
10
Unit
10
±2
Bits
LSB
40
kohm
µs
14.0
2.7
VCC
V
0
VREF
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M30201 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.59. External clock input
Symbol
Parameter
tc
External clock input cycle time
tw(H)
tw(L)
tr
tf
External clock input HIGH pulse width
External clock input LOW pulse width
Standard
Min.
Max.
Unit
143
ns
60
60
ns
ns
ns
ns
External clock rise time
18
18
External clock fall time
Table 1.60. Timer A input (counter input in event counter mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
TA0IN input HIGH pulse width
150
60
ns
tw(TAH)
tw(TAL)
TA0IN input LOW pulse width
60
ns
ns
Table 1.61. Timer A input (gating input in timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
600
ns
tw(TAH)
tw(TAL)
TA0IN input HIGH pulse width
300
300
ns
ns
TA0IN input LOW pulse width
Table 1.62. Timer A input (external trigger input in one-shot timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TA)
TA0IN input cycle time
300
ns
tw(TAH)
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
150
150
ns
tw(TAL)
ns
Table 1.63. Timer A input (external trigger input in pulse width modulation mode)
Symbol
Parameter
tw(TAH)
TA0IN input HIGH pulse width
tw(TAL)
TA0IN input LOW pulse width
Standard
Min.
Max.
150
150
Unit
ns
ns
Table 1.64. Timer A input (up/down input in event counter mode)
Parameter
Symbol
tc(UP)
TA0OUT input cycle time
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TA0OUT input HIGH pulse width
TA0OUT input LOW pulse width
TA0OUT input setup time
TA0OUT input hold time
Standard
Min.
Max.
3000
1500
1500
600
600
Unit
ns
ns
ns
ns
ns
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.65. Timer B input (counter input in event counter mode)
Symbol
Parameter
Standard
Min.
Max.
tc(TB)
TBiIN input cycle time (counted on one edge)
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
60
tw(TBL)
tc(TB)
tw(TBH)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
60
300
TBiIN input HIGH pulse width (counted on both edges)
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
160
160
150
Unit
ns
ns
ns
ns
ns
ns
Table 1.66. Timer B input (pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
300
300
ns
tw(TBL)
ns
Table 1.67. Timer B input (pulse width measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
tw(TBH)
TBiIN input cycle time
TBiIN input HIGH pulse width
600
300
ns
ns
tw(TBL)
TBiIN input LOW pulse width
300
ns
Table 1.68. Timer X input (counter input in event counter mode)
Symbol
Parameter
tc(TX)
TXiINOUT input cycle time
tw(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
tw(TXL)
Standard
Min.
Max.
Unit
150
ns
60
ns
60
ns
Table 1.69. Timer X input (gate input in timer mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TX)
tw(TXH)
TXiINOUT input HIGH pulse width
600
300
ns
ns
tw(TXL)
TXiINOUT input LOW pulse width
300
ns
TXiINOUT input cycle time
Table 1.70. Timer X input (external trigger input in one-shot timer mode)
Symbol
122
Parameter
Standard
Min.
Max.
Unit
tc(TX)
tw(TXH)
TXiINOUT input HIGH pulse width
300
150
ns
ns
tw(TXL)
TXiINOUT input LOW pulse width
150
ns
TXiINOUT input cycle time
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M30201 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified)
Table 1.71. Timer X input (pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TX)
TXiINOUT input cycle time
600
ns
tw(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
300
ns
300
ns
tw(TXL)
Table 1.72. Timer X input (pulse width measurement mode)
Symbol
tc(TX)
tw(TXH)
tw(TXL)
Parameter
Standard
Min.
Max.
Unit
TXiINOUT input cycle time
600
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
300
ns
ns
300
ns
Table 1.73. Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
tw(CKH)
CLK0 input cycle time
CLK0 input HIGH pulse width
300
150
ns
ns
tw(CKL)
CLK0 input LOW pulse width
150
ns
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
TxDi output delay time
160
TxDi hold time
RxDi input setup time
RxDi input hold time
0
50
90
ns
ns
ns
ns
_______
Table 1.74. External interrupt INTi inputs
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
Standard
Min.
Max.
380
380
Unit
ns
ns
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
tc(TA)
tw(TAH)
TA0IN input
tw(TAL)
tc(UP)
tw(UPH)
TA0OUT input
tw(UPL)
TA0OUT input
(Up/down input)
During event counter mode
TA0IN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(TX)
tw(TXH)
TXiINOUT input
tw(TXL)
tc(CK)
tw(CKH)
CLK0
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
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Description
Outline Performance
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Table AA-1 shows the outline performance of the M30201 (flash memory version).
Table AA-1. Outline Performance of the M30201 (flash memory version)
Item
Performance
Power supply voltage
4.0V to 5.5 V (f(XIN)=10MHz)
Program/erase voltage
VPP=12V ± 5% (f(XIN)=10MHz)
VCC=5V ± 5% (f(XIN)=10MHz)
Flash memory operation mode
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
Erase block
division
User ROM area
See Figure 1.AA.3.
Boot ROM area
One division (4 Kbytes) (Note 1)
Program method
In units of byte
Erase method
Collective erase
Program/erase control method
Program/erase control by software command
Number of commands
6 commands
Program/erase count
100 times
ROM code protect
Parallel I/O mode is supported.
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
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Description
Flash Memory
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The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage
VPP power supply for program/erase operations, in addition to the VCC power supply for device operation.
For this flash memory, three flash memory modes are available in which to read, program, and erase:
parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit
(CPU). Each mode is detailed in the pages to follow.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
Microcomputer mode
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
0000016
SFR
SFR
SFR
RAM
RAM
RAM
0040016
YYYYY16
DF00016
Collective
erasable/
programmable
area
Boot ROM
area
(3.5K bytes)
Collective
erasable/
programmable
area
User ROM
area
Boot ROM
area
(3.5K bytes)
DFDFF16
XXXXX16
User ROM
area
Collective
erasable/
programmable
area
User ROM
area
FFFFF16
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Type No.
M30201F6
XXXXX16
F400016
YYYYY16
00BFF16
Figure AA-3. Block diagram of flash memory version
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
CPU Rewrite Mode
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In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by
reading or writing to the flash memory control register and flash command register. Figure BB-1, Figure BB2 show the flash memory control register, and flash command register respectively.
Also, in CPU rewrite mode, the CNVSS pin is used as the VPP power supply pin. Apply the power supply
voltage, VPPH, from an external source to this pin.
In CPU rewrite mode, only the user ROM area shown in Figure AA-3 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to internal RAM before it can be executed.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0
FCON0
03B416
001000002
1 0
0
Bit symbol
Bit name
Function
FCON00 CPU rewrite mode
select bit
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Reserved bit
This bit can not write. The value, if
read, turns out to be indeterminate.
FCON02 CPU rewrite mode
monitor flag
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
Reserved bit
Must always be set to "0".
Reserved bit
Must always be set to "1".
Nothing is assigned. In an attempt to write this bit, write "0". The value,
if read, turns out to be "0".
Must always be set to "0".
Reserved bit
A
R WW
R
AA
A
A
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
Address
When reset
FCON1
03B516
XXXXXX002
Bit symbol
Bit name
Function
Reserved bit
Must always be set to "0".
Nothing is assigned. In an attempt to write these bits, write "0". The
value, if read, turns out to be indeterminate.
A
R WW
R
Figure BB-1. Flash memory control register
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
FCMD
03B616
0016
Function
Writing of software command
<Software command name>
•Read command
•Program command
•Program verify command
•Erase command
•Erase verify command
•Reset command
<Command code>
"0016"
"4016"
"C016"
"2016" +"2016"
"A016"
"FF16" +"FF6"
R WW
R
A
Figure BB-2. Flash command register
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CPU Rewrite Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Microcomputer Mode and Boot Mode
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The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure AA-3 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low
(VSS). In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU
starts operating using the control program in the boot ROM area. This mode is called the “boot” mode.
The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed onboard by writing commands from the CPU to the flash memory control register (addresses 03B416,
03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot
ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accomplished, a CPU write control program must be written into the boot ROM area in parallel input/output
mode. The following shows a CPU rewrite mode operation procedure.
<Start procedure (Note 1)>
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P52 pin for reset release. Or the user can
jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU
write control program. In this case, set the CPU write mode select bit of the flash memory control
register to “1” before applying VPPH to the CNVSS/VPP pin.
(2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump
to this control program in RAM. (The operations described below are controlled by this program.)
(3) Set the CPU rewrite mode select bit to “1”.
(4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled.
(5) Execute operation on the flash memory by writing software commands to the flash command register.
Note 1: In addition to the above, various other operations need to be performed, such as for entering the
data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and
writing to the watchdog timer.
<Clearing procedure>
(1) Apply VSS to the CNVSS/VPP pin.
(2) Set the CPU rewrite mode select bit to “0”.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
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(1) Operation speed
During erase/program mode, set BCLK to one of the following frequencies by changing the divide
ratio:
5 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state)
10 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
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CPU Rewrite Mode
Software Commands
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Table BB-1 lists the software commands available with the M30201 (flash memory version).
When CPU rewrite mode is enabled, write software commands to the flash command register to specify
the operation to erase or program.
The content of each software command is explained below.
Table BB-1. List of Software Commands (CPU Rewrite Mode)
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D0 to D7)
Read
Write
03B616
0016
Program
Write
03B616
Program verify
Write
Erase
Data
(D0 to D7)
Mode
Address
4016
Write
Program
address
Program
data
03B616
C016
Read
Verify
address
Verify
data
Write
03B616
2016
Write
03B616
2016
Erase verify
Write
03B616
A016
Read
Verify
address
Verify
data
Reset
Write
FF16
Write
03B616
FF16
03B616
Read Command (0016)
The read mode is entered by writing the command code “0016” to the flash command register in the
first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of
the specified address is read out at the data bus (D0–D7), 8 bits at a time.
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” to the flash command register in
the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g.,
STE instruction) in the second bus cycle, the flash memory control circuit executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user
go to the next processing.
During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 1.BB.3 for an example of a programming flowchart.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
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Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” to the flash command
register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte
data from the address to be verified (the previously programmed address) in the second bus cycle,
the content that has actually been written to the address is read out from the memory.
The CPU compares this read data with the data that it previously wrote to the address using the
program command. If the compared data do not match, the user need to execute the program and
program-verify operations one more time.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” to the
flash command register in the first bus cycle and the same command code to the flash command
register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20
ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands. During erase operation, the
watchdog timer remains idle, with the value “7FFF16 set in it.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure BB-3 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” to the flash command register
in the first bus cycle. When the user execute an instruction to read byte data from the address to be
verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out.
The CPU must sequentially erase-verify memory contents one address at a time, over the entire area
erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop
erase-verify at that point and execute erase and erase-verify operations one more time.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
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CPU Rewrite Mode
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Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice to the flash command register, write
command code “FF16” to the flash command register in the first bus cycle and the same command
code to the flash command register again in the second bus cycle. The program command or erase
command is disabled, with the flash memory placed in read mode.
Erase
Program
Start
Start
Address = first location
All bytes =
"0016"?
YES
Loop counter : X=0
NO
Write program data/
address
Program all bytes =
"0016"
Write : 4016
Write program command
Address = First address
Write : Program data
Loop counter X=0
Duration = 20 µs
Loop counter : X=X+1
Write erase command
Write:2016
Write erase command
Write:2016
Duration = 20ms
Write program verify
command
Write : C016
Loop counter X=X+1
Write erase verify
command/address
Duration = 6 µs
X=25 ?
Duration = 6µs
YES
NO
FAIL
PASS
Next address ?
NO
X=1000 ?
PASS
Verify
OK ?
Verify
OK ?
FAIL
FAIL
PASS
FAIL
Verify
OK?
PASS
PASS
Next address
Write read command
YES
NO
Last
address ?
Write read command
Write:A016
Write : 0016
NO
Read:
expect value=FF16
FAIL
Last
address?
Write read command
Write read command
PASS
Figure BB-3. Program and erase execution flowchart in the CPU rewrite mode
132
Verify
OK?
FAIL
Write:0016
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Appendix Parallel I/O Mode
Description of Pin Function (Flash Memory Parallel I/O Mode)
Pin name
Signal name
Function
I/O
Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin.
Power supply input
CNVSS
CNVSS
I
Apply 12 V ± 5 % to the CNVSS pin.
RESET
Reset input
I
Connect this pin to VSS.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When entering an externally derived clock, enter it from XIN and leave
XOUT open.
AVCC, AVSS
Analog power supply input
VREF
Reference voltage input
P00 to P07
Data I/O D0 to D7
P10 to P17
Address input A8 to A15
I
These are address A8–A15 input pins.
P30 to P33
Address input A4 to A7
I
These are address A4–A7 input pins.
P34 to P35
Input port P3
I
Enter low signals to these pins.
P40
WE input
I
This is a WE input pin.
P41
OE input
I
This is a OE input pin.
P43
CE input
I
This is a CE input pin.
P42, P44, P45
Input port P4
I
Enter high signals or low signals to these pins.
P50
Address input A17
I
This is address A17 input pin.
P51
VRFY input
I
Apply VIH (5 V) to this pin when VPP = VPPH (12 V), or VIL (0 V) when VPP
= VPPL (5 V).
P52
Input port P5
I
Enter low signal to this pin.
P53, P54
Input port P5
I
Enter high signals or low signals to these pins.
P60 to P63
Address input A0 to A3
I
These are address A0–A3 input pins.
P64 to P67
Input port P6
I
Enter high signals or low signals to these pins.
P70 to P71
Input port P7
I
Enter high signals or low signals to these pins.
P
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VCC,VSS
Connect AVSS to Vss and AVcc to Vcc, respectively.
I
I/O
Connect this pin to VSS.
These are data D0–D7 input/output pins.
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Appendix Parallel I/O Mode
Parallel I/O Mode
P
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The parallel I/O mode is entered by making connections shown in Figures CC-2 and CC-3 and then turning
the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar
to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences
with regard to the functions not available with the microcomputer (function of read device identification
code) and matters related to memory capacity.
Table CC-2 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode.
Table CC-2. Pin relationship in parallel I/O mode
M30201(flash memory version)
VCC
VCC
M5M28F101
VCC
VSS
VSS
VSS
Address input
P60 to P63, P30 to P33,
P10 to P17, P50
A0 to A15, A17
Data I/O
P00 to P07
D0 to D7
OE input
P41
OE
CE input
P43
CE
WE input
P40
WE
VRFY input (Note)
P51
Note: The VRFY input only selects read-only or read/write mode, and does not have any pin
associated with it on the M5M28F101.
Microcomputer mode
CPU rewrite mode
Standard serial I/O mode
Parallel I/O mode
0000016
SFR
SFR
SFR
RAM
RAM
RAM
0040016
YYYYY16
DF00016
Collective
erasable/
programmable
area
Boot ROM
area
(3.5K bytes)
Collective
erasable/
programmable
area
User ROM
area
Boot ROM
area
(3.5K bytes)
DFDFF16
XXXXX16
User ROM
area
Collective
erasable/
programmable
area
User ROM
area
FFFFF16
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Type No.
M30201F6
XXXXX16
F400016
YYYYY16
00BFF16
Figure CC-1. Block diagram of flash memory version
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Appendix Parallel I/O Mode
AVSS
P60/AN0
VREF
AVCC
P54/CKOUT/AN54
1
2
3
52
51
50
P61/AN1
P62/AN2
P63/AN3
4
5
6
49
48
47
P64/AN4
P65/AN5
7
8
9
46
45
44
A1
A2
A3
P53/CLKS/AN53
P52/CLK0/AN52
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
P71/TB1IN/XCIN
VRFY
A17
VPPH
P70/TB0IN/XCOUT
RESET
XOUT
Connect oscillator circuit.
VSS
XIN
VCC
13
14
15
P45/TX2INOUT
16
17
18
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
P42/RXD1
19
20
21
P41/TA0OUT
P40/TA0IN/TXD1
P35
P34
22
23
24
VCC
CE
10
11
12
OE
WE
A7
P33
25
26
M30201F6SP
M30201F6TSP
P
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A0
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P66/AN6
P67/AN7
P00/KI0
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P14(LED4)
P15(LED5)
P16(LED6)
P17(LED7)
P30
P31
P32
D0
D1
D2
D3
D4
D6
D5
D7
A8
A9
A10
A11
A12
A13
A14
A15
A4
A5
A6
VSS
Figure CC-2. Pin connection diagram in parallel I/O mode (1)
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A3
P66/AN6
P60/AN0
AVSS
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
56
55
54
53
52
51
50
49
48
47
46
45
44
43
N.C.
AVCC
VREF
P
re
lim
in
ar
y
P52/CLK0/AN52
P53/CLKS/AN53
P54/CKOUT/AN54
A1
A2
A0
Appendix Parallel I/O Mode
1
2
42
41
3
4
5
40
39
38
RESET
N.C.
6
7
8
14
VSS
Figure CC-3. Pin connection diagram in parallel I/O mode (2)
136
A12
A14
A13
A15
A7
OE
A6
WE
P42/RXD1
CE
31
30
29
A4
P45/TX2INOUT
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
11
12
13
A5
VCC
34
33
32
P33
P32
P31
P30
P17(LED7)
P16(LED6)
P15(LED5)
P14(LED4)
VCC
9
10
P35
P34
XOUT
VSS
XIN
Connect oscillator
circuit.
37
36
35
M30201F6FP
M30201F6TFP
P40/TA0IN/TXD1
N.C.
VPPH
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A17
P41/TA0OUT
VRFY
P67/AN7
N.C.
P00/KI0
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
D0
D1
D2
D3
D4
D5
D6
A8
D7
A9
A10
A11
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Appendix Parallel I/O Mode
User ROM and Boot ROM Areas
P
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lim
in
ar
y
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure CC-1 can be rewritten.
In the boot ROM area, an erase block operation is applied to only one 4 K byte block. The boot ROM area
has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.
Therefore, using the device in standard serial input/output mode, the user does not need to write to the
boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by
_____ _____ _____
the status of the CE, OE, WE, VRFY, and CNVSS input pins.
The contents of erase, program, and other operations are selected by writing a software command. The
data in memory can only be read out by a read after software command input.
Program and erase operations are controlled using software commands.
Table CC-3. Relationship between control signals and bus operation modes
Pin name
Read
only
OE
WE
VRFY
VPP
Read
VIL
VIL
VIH
VIL
VPPH
Data output
Output disabled
VIL
VIH
VIH
VIL
VPPH
Hi-Z
VIL
VPPH
Hi-Z
Stand by
Read/
Write
D0 to D7
CE
Mode
VIH
X
X
Read
VIL
VIL
VIH
VIH
VPPH
Data output
Output disabled
VIL
VPPH
Hi-Z
VIH
VIH
X
VIH
Stand by
VIH
X
VIH
VIH
VPPH
Hi-Z
VPPH
Data input
Write
VIL
VIH
VIL
Note: X can be VIL or VIH.
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Appendix Parallel I/O Mode
The following explains about bus operation modes, software commands, and status register.
Bus Operation Modes
P
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Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin.
Read-only mode has three states: Read, Output Disable, and Standby which are selected by
_____ _____
______
setting the CE, OE, and WE pins high or low.
Read-write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin.
Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by
_____ _____
______
setting the CE, OE, and WE pins high or low.
Read
______
_____
_____
The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read
mode, the data corresponding to each software command entered is output from the data I/O pins
D0–D7.
Output Disable
_____
_____
_____
The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also,
the data I/O pins are placed in the high-impedance state.
Standby
_____
The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the
high-impedance state.
Write
The Write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin
_____
_____
_____
and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device
accepts the software commands or write data entered from the data I/O pins. A program, erase, or
some other operation is initiated depending on the content of the software command entered here.
_____
The input data such as address is latched at the falling edge of WE pin. The input data such as
_____
software command is latched at the rising edge of WE pin.
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Appendix Parallel I/O Mode
Software Commands
P
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lim
in
ar
y
Table CC-4 lists the software commands available with the M30201 (flash memory version). By entering
a software command from the data I/O pins (D0–D7) in Write mode, specify the content of the operation,
such as erase or program operation, to be performed.
The following explains the content of each software command.
Table CC-4. Software command list (parallel I/O mode)
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D0 to D7)
Read
Write
x
0016
Program
Write
x
Program verify
Write
Erase
Data
(D0 to D7)
Mode
Address
4016
Write
Program
address
Program
data
x
C016
Read
x
Verify
data
Write
x
2016
Write
x
2016
Erase verify
Write
Verify
address
A016
Read
x
Verify
data
Reset
Write
x
FF16
Write
x
FF16
Read Command (0016)
The read mode is entered by writing the command code “0016” in the first bus cycle. When an address
to be read is input in one of the bus cycles that follow, the content of the specified address is read out
at the data I/O pins (D0–D7).
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” in the first bus cycle. When an
address and data to be program is write in the second bus cycle, the flash memory control circuit
executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs
or more before the user go to the next processing.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure CC-4 for an example of a programming flowchart.
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Appendix Parallel I/O Mode
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
P
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ar
y
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” in the
first bus cycle and the same command code again in the second bus cycle. The erase operation
requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure CC-4 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
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Appendix Parallel I/O Mode
P
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lim
in
ar
y
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice, write command code “FF16” in the first
bus cycle and the same command code again in the second bus cycle. The program command or
erase command is disabled, with the flash memory placed in read mode.
Erase
Program
Start
Start
Address = first location
All bytes =
"0016"?
YES
Loop counter : X=0
NO
Write program data/
address
Program all bytes =
"0016"
Write : 4016
Write program command
Address = First address
Write : Program data
Loop counter X=0
Duration = 20 µs
Loop counter : X=X+1
Write erase command
Write:2016
Write erase command
Write:2016
Duration = 20ms
Write program verify
command
Write : C016
Loop counter X=X+1
Write erase verify
command/address
Duration = 6 µs
X=25 ?
Duration = 6µs
YES
NO
FAIL
PASS
Next address ?
NO
X=1000 ?
PASS
Verify
OK ?
Verify
OK ?
FAIL
FAIL
PASS
FAIL
Verify
OK?
PASS
PASS
Next address
Write read command
YES
NO
Last
address ?
Write read command
Write:A016
Write : 0016
NO
Verify
OK?
Read:
expect value=FF16
FAIL
Last
address?
Write read command
PASS
Write read command
Write:0016
FAIL
Figure CC-4. Program and erase execution flowchart in the CPU rewrite mode
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Appendix Parallel I/O Mode
Protect function
P
re
lim
in
ar
y
In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects
the flash memory contents from being read or rewritten easily.
Depending on the content at the protect control address (FFFFF16) in parallel I/O mode, this function
inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is
shown in Figure CC-5 . (This address exists in the user ROM area.)
The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash
memory contents are inhibited against read or modification. The protect function is disabled by setting
both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or
modified. Once the protect function is set, the user cannot change settings of the protect clear bits while
in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode.
Protect control address
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1 1
Symbol
ROMCP
Address
FFFFF16
When shipping
FF16
Bit name
Bit symbol
Reserved bit
Function
Always set to "1".
b5 b4
ROMCR
Protect reset bit
ROMCP
Protect set bit
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When protect is turned on, the flash memory version is protected against readout or modification
in parallel I/O mode.
Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be
changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode.
Figure CC-5. Protect control address
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Appendix Standard Serial I/O Mode
Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Description
I/O
Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin.
Power input
CNVSS
CNVSS
I
Apply 12V ± 5 % to this pin.
RESET
Reset input
I
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
P
re
lim
in
ar
y
VCC,VSS
XIN
Clock input
I
XOUT
Clock output
O
AVCC, AVSS
Analog power supply input
VREF
Reference voltage input
I
P00 to P07
Input port P0
I
P10 to P17
Input port P1
I
Input "H" or "L" level signal or open.
P30 to P35
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P45
Input port P4
I
Input "H" or "L" level signal or open.
P54
Input port P5
I
Input "H" or "L" level signal or open.
P50
TxD output
O
Serial data output pin.
P51
RxD input
I
Serial data input pin.
P52
SCLK input
I
Serial clock input pin.
P53
BUSY output
O
BUSY signal output pin.
P60 to P67
Input port P6
I
Input "H" or "L" level signal or open.
P70 to P71
Input port P7
I
Input "H" or "L" level signal or open.
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
Connect AVSS to Vss and AVcc to Vcc, respectively.
Enter the reference voltage for AD from this pin.
Input "H" or "L" level signal or open.
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Appendix Standard Serial I/O Mode
Mode setup method
Signal
Value
CNVSS
VPPH
VSS
VCC
P
re
lim
in
ar
y
RESET
VSS
AVSS
P60/AN0
1
2
VCC
VREF
AVCC
P54/CKOUT/AN54
3
4
5
BUSY
P53/CLKS/AN53
6
7
8
RXD
TXD
CNVSS
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
RESET
RESET
Connect oscillator circuit.
VCC
VSS
XOUT
VSS
XIN
12
13
14
48
47
46
45
44
43
42
41
40
39
38
VCC
15
16
17
P45/TX2INOUT
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
18
19
20
P42/RXD1
P41/TA0OUT
P40/TA0IN/TXD1
P35
21
22
23
32
31
30
24
25
26
29
28
27
P34
P33
Figure DD-1. Pin connections for serial I/O mode (1)
144
9
10
11
51
50
49
M30201F6SP
M30201F6TSP
P52/CLK0/AN52
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
SCLK
52
37
36
35
34
33
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P00/KI0
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P14(LED4)
P15(LED5)
P16(LED6)
P17(LED7)
P30
P31
P32
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Appendix Standard Serial I/O Mode
Mode setup method
VSS
VCC
VCC
VSS
P66/AN6
P60/AN0
AVSS
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
N.C.
AVCC
VREF
56
55
54
53
52
51
50
49
48
47
46
45
44
43
P52/CLK0/AN52
P53/CLKS/AN53
P54/CKOUT/AN54
P
re
lim
in
ar
y
RESET
VPPH
BUSY
Value
CNVSS
SCLK
Signal
R XD
TXD
Connect oscillator
circuit.
CNVSS
RESET
P51/RXD0/AN51
P50/TXD0/AN50
CNVSS
P71/TB1IN/XCIN
P70/TB0IN/XCOUT
RESET
N.C.
VSS
XOUT
VSS
XIN
VCC
VCC
P45/TX2INOUT
42
41
40
39
38
M30201F6FP
M30201F6TFP
11
12
13
37
36
35
34
33
32
31
30
29
14
P67/AN7
N.C.
P00/KI0
P01/KI1
P02/KI2
P03/KI3
P04/KI4
P05/KI5
P06/KI6
P07/KI7
P10(LED0)
P11(LED1)
P12(LED2)
P13(LED3)
P33
P32
P31
P30
P17(LED7)
P16(LED6)
P15(LED5)
P14(LED4)
P35
P34
P42/RXD1
P41/TA0OUT
P40/TA0IN/TXD1
N.C.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P44/INT1/TX1INOUT
P43/INT0/TX0INOUT
1
2
3
4
5
6
7
8
9
10
Figure DD-2. Pin connections for serial I/O mode (2)
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Appendix Standard Serial I/O Mode
Standard Serial I/O Mode
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The standard serial I/O mode serially inputs and outputs the software commands, addresses and data
necessary for operating (read, program, erase, etc.) the internal flash memory. It uses a purpose-specific
serial programmer.
The standard serial I/O mode differs from the parallel I/O mode in that the CPU controls operations like
rewriting (uses the CPU rewrite mode) in the flash memory or serial input for rewriting data. The standard
serial I/O mode is started by clearing the reset with VPPH at the CNVss pin. (For the normal microprocessor
mode, set CNVss to “L”.)
This control program is written in the boot ROM area when shipped from Mitsubishi Electric. Therefore, if
the boot ROM area is rewritten in the parallel I/O mode, the standard serial I/O mode cannot be used.
Figures DD-1 and DD-2 show the pin connections for the standard serial I/O mode. Serial data I/O uses
three UART0 pins: CLK0, RxD0, and TxD0 and port P53 (BUSY).
The CLK0 pin is the transfer clock input pin and it transfers the external transfer clock. The TxD0 pin outputs
the CMOS signal. The P53 (BUSY) pin outputs an “L” level when reception setup ends and an “H” level
when the reception operation starts. Transmission and reception data is transferred serially in 8-byte
blocks.
In the standard serial I/O mode, only the user ROM area shown in Figure CC-1 can be rewritten, the boot
ROM area cannot.
The standard serial I/O mode has a 7-byte ID code. When the flash memory is not blank and the ID code
does not match the content of the flash memory, the command sent from the programmer is not accepted.
Function Overview (Standard Serial I/O Mode)
In the standard serial I/O mode, software commands, addresses and data are input and output between
the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial I/O
(UART0) and P53. In reception, the software commands, addresses and program data are synchronized
with the rise of the transfer clock input to the CLK0 pin and input into the flash memory via the RxD0 pin.
In transmission, the read data and status are synchronized with the fall of the transfer clock and output to
the outside from the TxD0 pin.
The TxD1 pin is CMOS output. Transmission is in 8-bit blocks and LSB first.
When busy, either during transmission or reception, or while executing an erase operation or program,
the P53 (BUSY) pin is “H” level. Accordingly, do not start the next transmission until the P53 (BUSY) pin is
“L” level.
Also, data in memory and the status register can be read after inputting a software command. It is possible to check flash memory operating status or whether a program or erase operation ended successfully or in error by reading the status register.
Software commands and the status register are explained here following.
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Appendix Standard Serial I/O Mode
Software Commands
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Table DD-1 lists software commands. In the standard serial I/O mode, erase operations, programs and
reading are controlled by transferring software commands via the RxD pin. Software commands are
explained here below.
Table DD-1. Software commands (Standard serial I/O mode)
Control command
2nd byte
1
Page read
FF16
2
Page program
4116
3
Erase all unlocked blocks
A716
4
Read status register
7016
5
Clear status register
5016
6
Read lockbit status
7116
7
ID check function
F516
8
Download function
FA16
9
Version data output function FB16
14 Boot area output function
FC16
3rd byte
4th byte 5th byte 6th byte
Address
(middle)
Address
(high)
Data
output
Data
output
Data
output
Address
(middle)
Address
(high)
Data
input
Data
input
Data
input
D016
SRD
output
SRD1
output
Address
(middle)
Address
(high)
Address
(low)
Size
(low)
Address
(middle)
Size
(high)
Lock bit
data
output
Address
(high)
Checksum
Version
data
output
Address
(middle)
Version
data
output
Address
(high)
Version
data
output
Data
output
When ID is
not verificate
Not
acceptable
Data
output to
259th
byte
Data input
Not
to 259th acceptable
byte
Not
acceptable
Acceptable
Not
acceptable
Not
acceptable
ID size
ID1
To ID7
Acceptable
Data
input
To
Not
required
acceptable
number
of times
Version Version
Version
Acceptable
data
data data output
output output to 9th byte
Data
Data
Data
Not
output output
output to acceptable
259th byte
Note1: Shading indicates transfer from flash memory microcomputer to serial programmer. All other data is
transferred from the serial programmer to the flash memory microcomputer.
Note2: SRD refers to status register data. SRD1 refers to status register 1 data.
Note3: All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode
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Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Send the “FF16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
RxD0
FF16
A8 to
A15
A16 to
A23
data255
data0
TxD0
P53(BUSY)
Figure DD-3. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent in the 1st byte of the
transmission, the contents of the status register (SRD) specified in the 2nd byte of the transmission
and the contents of status register 1 (SRD1) specified in the 3rd byte of the transmission are read.
CLK0
RxD0
7016
TxD0
P53(BUSY)
Figure DD-4. Timing for reading the status register
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SRD1
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Appendix Standard Serial I/O Mode
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Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent in the 1st byte of the transmission, the aforementioned
bits are cleared. When the clear status register operation ends, the P53 (BUSY) signal changes from
the “H” to the “L” level.
CLK0
RxD0
5016
TxD0
P53(BUSY)
Figure DD-5. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Send the “4116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, as write data (D0–D7) for the page (256 bytes) specified with addresses
A8 to A23 is input sequentially from the smallest address first, that page is automatically written.
When reception setup for the next 256 bytes ends, the P53 (BUSY) signal changes from the “H” to the
“L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
CLK0
RxD0
4116
A8 to A16 to
A15
A23
data0
data255
TxD0
P53(BUSY)
Figure DD-6. Timing for the page program
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Appendix Standard Serial I/O Mode
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Send the “A716” command code in the 1st byte of the transmission.
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(2) Send the verify command code “D016” in the 2nd byte of the transmission. With the verify command code, the erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
CLK0
RxD0
A716
D016
TxD0
P53(BUSY)
Figure DD-7. Timing for erasing all unlocked blocks
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status command as explained here following.
(1) Send the “7116” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) The lock bit data of the specified block is output in the 4th byte of the transmission. Write the
highest address of the specified block for addresses A8 to A23.
The M30201 (flash memory version) does not have the lock bit, so the read value is always “1”
(block unlock).
CLK0
RxD0
7116
TxD0
P53(BUSY)
Figure DD-8. Timing for reading lock bit status
150
A8 to
A15
A16 to
A23
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Appendix Standard Serial I/O Mode
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Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Send the “FA16” command code in the 1st byte of the transmission.
(2) Send the program size in the 2nd and 3rd bytes of the transmission.
(3) Send the check sum in the 4th byte of the transmission. The check sum is added to all data sent
in the 5th byte onward.
(4) The program to execute is sent in the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK0
RxD0
FA16
Check
sum
Program
data
Program
data
Data size (low)
TxD0
Data size (high)
P53(BUSY)
Figure DD-9. Timing for download
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Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Send the “FB16” command code in the 1st byte of the transmission.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK0
RxD0
FB16
TxD0
'V'
'E'
'R'
'X'
P53(BUSY)
Figure DD-10. Timing for version information output
Boot Area Output Command
This command outputs the control program stored in the boot area in one page blocks (256 bytes).
Execute the boot area output command as explained here following.
(1) Send the “FC16” command code in the 1st byte of the transmission.
(2) Send addresses A8 to A15 and A16 to A23 in the 2nd and 3rd bytes of the transmission respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the rise of the clock.
CLK0
RxD0
FC16
A8 to
A15
TxD0
P53(BUSY)
Figure DD-11. Timing for boot area output
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A16 to
A23
data0
data255
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Appendix Standard Serial I/O Mode
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ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Send the “F516” command code in the 1st byte of the transmission.
(2) Send addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code in the 2nd, 3rd
and 4th bytes of the transmission respectively.
(3) Send the number of data sets of the ID code in the 5th byte.
(4) The ID code is sent in the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0
F516
DF16
FF16
0F16
ID size
ID1
ID7
TxD0
P53(BUSY)
Figure DD-12. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the serial programmer and the ID code
written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the serial programmer is not accepted. An ID code contains 8 bits of data. Area is,
from the 1st byte, addresses 0FFFDF 16 , 0FFFE3 16 , 0FFFEB 16 , 0FFFEF 16, 0FFFF3 16, and
0FFFF716 . Write a program into the flash memory, which already has the ID code set for these
addresses.
Address
0FFFDF16 to 0FFFDC16
ID1 Undefined instruction vector
0FFFE316 to 0FFFE016
ID2 Overflow vector
0FFFE716 to 0FFFE416
BRK instruction vector
0FFFEB16 to 0FFFE816
ID3 Address match vector
0FFFEF16 to 0FFFEC16
ID4 Single step vector
0FFFF316 to 0FFFF016
ID5 Watchdog timer vector
0FFFF716 to 0FFFF416
ID6 DBC vector
0FFFFB16 to 0FFFF816
ID7
0FFFFF16 to 0FFFFC16
Reset
4 bytes
Figure DD-13. ID code storage addresses
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Appendix Standard Serial I/O Mode
Status Register (SRD)
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The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table DD-2 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table DD-2. Status register (SRD)
Definition
SRD0 bits
Status name
SR7 (bit7)
Status bit
Ready
Busy
SR6 (bit6)
Reserved
-
-
SR5 (bit5)
Erase bit
Terminated in error
Terminated normally
SR4 (bit4)
Program bit
Terminated in error
Terminated normally
SR3 (bit3)
Reserved
-
-
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
"1"
"0"
Status Bit (SR7)
The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready)
is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to
“1” when the operation ends.
Erase Bit (SR5)
The erase bit reports the operating status of the auto erase operation. If an erase error occurs, it is set
to “1”. When the erase status is cleared, it is set to “0”.
Program Bit (SR4)
The program bit reports the operating status of the auto write operation. If a write error occurs, it is set
to “1”. When the program status is cleared, it is set to “0”.
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Appendix Standard Serial I/O Mode
Status Register 1 (SRD1)
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Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table DD-3 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table DD-3. Status register 1 (SRD1)
SRD1 bits
Status name
SR15 (bit7)
Boot update completed bit
SR14 (bit6)
Definition
"1"
"0"
Update completed
Not update
Reserved
-
-
SR13 (bit5)
Reserved
-
-
SR12 (bit4)
Checksum match bit
SR11 (bit3)
ID check completed bits
SR10 (bit2)
SR9 (bit1)
Data receive time out
SR8 (bit0)
Reserved
Match
00
01
10
11
Mismatch
Not verified
Verification mismatch
Reserved
Verified
Time out
Normal operation
-
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the download function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
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Appendix Standard Serial I/O Mode
Example Circuit Application for The Standard Serial I/O Mode
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The below figure shows a circuit application for the standard serial I/O mode. Control pins will vary according to programmer, therefore see the programmer manual for more information.
CLK0
Clock input
P53 output
P53(BUSY)
Data input
RXD0
Data output
TXD0
VPP
M30201 Flash
memory version
CNVss
(1) Control pins and external circuitry will vary according to programmer. For
more information, see the programmer manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are
switched via a switch.
Figure DD-14. Example circuit application for the standard serial I/O mode
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52P4B
Plastic 52pin 600mil SDIP
EIAJ Package Code
SDIP52-P-600-1.78
Weight(g)
5.1
Lead Material
Alloy 42/Cu Alloy
27
1
26
E
52
e1
c
JEDEC Code
–
Symbol
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
L
A1
A
A2
D
e
b
b1
b2
SEATING PLANE
56P6S-A
Dimension in Millimeters
Min
Nom
Max
–
–
5.5
0.51
–
–
–
3.8
–
0.4
0.5
0.6
0.9
1.0
1.3
0.65
0.75
1.05
0.22
0.27
0.34
45.65
45.85
46.05
12.85
13.0
13.15
–
1.778
–
–
15.24
–
3.0
–
–
0°
–
15°
Plastic 56pin 10✕10mm body QFP
EIAJ Package Code
QFP56-P-1010-0.65
Weight(g)
0.59
Lead Material
Alloy 42
MD
e
JEDEC Code
–
ME
HD
D
b2
43
56
1
42
I2
E
HE
Recommended Mount Pad
Symbol
14
29
A
28
15
b
y
F
A1
e
c
A2
L1
L
Detail F
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0
0.1
0.2
2.8
–
–
0.25
0.3
0.4
0.13
0.15
0.2
9.8
10.0
10.2
9.8
10.0
10.2
0.65
–
–
12.5
12.8
13.1
12.5
12.8
13.1
0.4
0.6
0.8
1.4
–
–
0.1
–
–
0°
10°
–
0.35
–
–
1.3
–
–
10.6
–
–
–
–
10.6
157
Keep safety first in your circuit designs!
●
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
●
●
●
●
●
●
●
●
These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
All information contained in these materials, including product data, diagrams, charts,
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without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
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The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
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www.mitsubishichips.com).
When using any or all of the information contained in these materials, including
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all information as a total system before making a final decision on the applicability of
the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information
contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
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If these products or technologies are subject to the Japanese export control
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Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
ductor product distributor for further details on these materials or the products con
tained therein.
MITSUBISHI SEMICONDUCTORS
M30201 Group DATA SHEET REV.D
April First Edition 1998
July Second Edition 1998
February Third Edition 1999
May Fourth Edition 1999
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©1999 MITSUBISHI ELECTRIC CORPORATION