IDT IDT70T651S12BF High-speed 2.5v 256/128k x 36 asynchronous dual-port static ram with 3.3v 0r 2.5v interface Datasheet

HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
Features
◆
◆
◆
◆
◆
◆
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
PRELIMINARY
IDT70T651/9S
◆
◆
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
BE3L
BE 3R
BE2L
BE2R
BE1L
BE 1R
BE0L
BE0R
R/W L
R/WR
BB
EE
01
LL
CE0L
CE1L
BB
EE
23
LL
BBBB
EEEE
3210
R RRR
CE0R
CE1R
OEL
OER
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
256/128K x 36
MEMORY
ARRAY
I/O0L- I/O 35L
A 17L(1)
A0L
Di n_L
Address
Decoder
Di n_R
ADDR_L
CE0L
CE1L
OEL
R/WL
BUSYL (2,3)
SEM L
INTL(3)
I/O 0R - I/O 35R
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE R
(4)
ZZ
CONTROL
CE0R
CE1R
A0R
TDI
JTAG
TD O
TC K
TMS
TRST
R/WR
BUSYR(2,3)
SEMR
INT R(3)
M/S
ZZL
A17R(1)
Address
Decoder
ADDR_R
ZZR
(4)
LOGIC
NOTES:
1. Address A17x is a NC for IDT70T659.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
4869 drw 01
NOVEMBER 2003
1
©2003 Integrated Device Technology, Inc.
DSC-5632/3
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Description
The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous
Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE0 or CE1) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The IDT70T651/9 has a RapidWrite Mode which allows the designer
to perform back-to-back write operations without pulsing the R/W input
each cycle. This is especially significant at the 8 and 10ns cycle times of
the IDT70T651/9, easing design considerations at these high performance levels.
The 70T651/9 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (VDD) is at 2.5V.
2
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3)
70T651/9BC
BC-256(5,6)
256-Pin BGA
Top View
03/18/03
A1
NC
B1
I/O18L
C1
A2
TDI
B2
NC
C2
A3
NC
B3
TDO
C3
I/O18R I/O19L VSS
D1
D2
D3
I/O20R I/O19R I/O20L
E1
E2
E3
A4
A5
A11L
B4
B6
NC
C4
A16L
D4
VDD
E4
B5
A15L
C5
A13L
D5
F2
F3
F4
E5
F5
I/O23L I/O22R I/O23R VDDQL VDD
G1
G2
G3
G4
G5
I/O24R I/O24L I/O25L VDDQR VSS
H1
H2
H3
H4
H5
I/O26L I/O25R I/O26R VDDQR VSS
J1
J2
J3
J4
J5
I/O27L I/O28R I/O27R VDDQL ZZR
K1
K2
K3
K4
K5
I/O29R I/O29L I/O28L VDDQL VSS
L1
L2
L3
L4
L5
I/O30L I/O31R I/O30R VDDQR VDD
M1
M2
M3
M4
I/O32R I/O32L I/O31L VDDQR
N1
N2
N3
N4
A12L
C6
A10L
D6
A7
A 8L
B7
A 9L
C7
A7L
D7
A8
A9
BE2L
B8
CE1L
B9
OEL
B10
CE0L R/WL
BE3L
C8
A10
C9
C10
A11
INTL
B11
NC
C11
A12
A5L
B12
A4L
C12
BE1L BE0L SEML BUSYL A6L
D8
D9
D10
D11
D12
A13
A2L
B13
A1L
C13
A3L
D13
M5
VDD
N5
E6
VDD
F6
NC
G6
VSS
H6
VSS
J6
VSS
K6
VSS
L6
NC
M6
VDD
N6
E7
VSS
F7
VSS
G7
VSS
H7
VSS
J7
VSS
K7
VSS
L7
VSS
M7
VSS
N7
E8
E9
VSS
F8
V SS
F9
V SS
VSS
G8
G9
VSS
H8
V SS
H9
VSS
J8
VSS
J9
VSS
K8
V SS
K9
VSS
L8
VSS
L9
VSS
M8
V SS
M9
VSS
N8
VSS
N9
E10
VSS
F10
VSS
G10
VSS
H10
V SS
J10
VSS
K10
VSS
L10
V SS
M10
VSS
N10
E11
VDD
F11
VSS
G11
VSS
H11
VSS
J11
VSS
K11
VSS
L11
VSS
M11
VDD
N11
E12
P2
P3
I/O35R I/O34L TMS
R1
I/O35L
T1
NC
R2
NC
T2
TCK
R3
TRST
T3
NC
P4
A16R
R4
NC
T4
A0L
B14
NC
C14
A15
NC
B15
I/O17L
C15
A16
NC
B16
NC
C16
OPTL I/O17R I/O16L
D14
D15
D16
E13
P5
A13R
R5
A15R
T5
A17R(4) A14R
P6
A10R
R6
A12R
T6
A11R
P7
A7R
R7
A9R
T7
A8R
P8
P9
P10
P11
BE1R BE0R SEMR BUSYR
R8
R9
R10
BE3R CE0R R/WR
T8
T9
T10
BE2R CE1R OER
R11
M/S
T11
INT R
E14
E15
E16
VDD VDDQR I/O13L I/O14L I/O14R
F12
F13
F14
F15
F16
VDD VDDQR I/O12R I/O13R I/O12L
G12
VSS
H12
VSS
J12
G13
G14
G15
G16
VDDQL I/O10L I/O11L I/O11R
H13
H14
VDDQL I/O9R
J13
J14
H15
H16
IO9L I/O10R
J15
J16
ZZL VDDQR I/O8R I/O7R I/O8L
K12
VSS
L12
VDD
M12
K13
K14
K15
K16
VDDQR I/O6R I/O6L I/O7L
L13
L14
VDDQL I/O5L
M13
M14
L15
L16
I/O4R I/O5R
M15
M16
VDD VDDQL I/O3R I/O3L I/O4L
N12
N13
I/O33L I/O34R I/O33R VDD VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDD
P1
A14
VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD I/O15R I/O15L I/O16R
I/O21R I/O21L I/O22L VDDQL VDD
F1
A6
A17L(4) A14L
P12
A6R
R12
A4R
T12
A5R
P13
A3R
R13
A1R
T13
A2R
N14
I/O2L
P14
N15
P15
I/O0L I/O0R
R14
OPTR
T14
A0R
N16
I/O1R I/O2R
R15
NC
T15
NC
P16
I/O1L
R16
NC
,
T16
NC
5632 drw 02f
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground supply.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
3
,
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
03/18/03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70T651/9DR
DR-208(5,6,7)
208-Pin
PQFP
Top View(8)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O19L
I/O19R
I/O20L
I/O20R
VDDQL
VSS
I/O21L
I/O21R
I/O22L
I/O22R
VDDQR
VSS
I/O23L
I/O23R
I/O24L
I/O24R
VDDQL
VSS
I/O25L
I/O25R
I/O26L
I/O26R
VDDQR
ZZR
VDD
VDD
VSS
VSS
VDDQL
VSS
I/O27R
I/O27L
I/O28R
I/O28L
VDDQR
VSS
I/O29R
I/O29L
I/O30R
I/O30L
VDDQL
VSS
I/O31R
I/O31L
I/O32R
I/O32L
VDDQR
VSS
I/O33R
I/O33L
I/O34R
I/O34L
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VSS
VDDQR
I/O18R
I/O18L
VSS
VDD
TDI
TDO
NC
NC
A17L(4)
A16L
A15L
A14L
A13L
A12L
A11L
A10L
A9L
A8L
A7L
BE3L
BE2L
BE1L
BE0L
CE1L
CE0L
VDD
VDD
VSS
VSS
SEML
OEL
R/WL
BUSYL
INTL
NC
A6L
A5L
A4L
A3L
A2L
A1L
A0L
VDD
VDD
VSS
OPTL
I/O17L
I/O17R
VDDQR
VSS
Pin Configurations(1,2,3) (con't.)
I/O16L
I/O16R
I/O15L
I/O15R
VSS
VDDQL
I/O14L
I/O14R
I/O13L
I/O13R
VSS
VDDQR
I/O12L
I/O12R
I/O11L
I/O11R
VSS
VDDQL
I/O10L
I/O10R
I/O9L
I/O9R
VSS
VDDQR
VDD
VDD
VSS
VSS
ZZ L
VDDQL
I/O8R
I/O8L
I/O7R
I/O7L
VSS
VDDQR
I/O6R
I/O6L
I/O5R
I/O5L
VSS
VDDQL
I/O4R
I/O4L
I/O3R
I/O3L
VSS
VDDQR
I/O2R
I/O2L
I/O1R
I/O1L
VSS
VDDQL
I/O35R
I/O35L
VDD
TMS
TCK
TRST
NC
NC
A17R(4)
A16R
A15R
A14R
A13R
A12R
A11R
A10R
A9R
A8R
A7R
BE3R
BE2R
BE1R
BE0R
CE1R
CE0R
VDD
VDD
VSS
VSS
SEMR
OER
R/WR
BUSYR
INTR
M/S
A6R
A5R
A4R
A3R
A2R
A1R
A0R
VDD
VSS
VSS
OPTR
I/O0L
I/O0R
VDDQL
VSS
5632 drw 02d
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 28mm x 28mm x 3.5mm.
6. This package code is used to reference the package diagram.
7. 8ns Commercial and 10ns Industrial speed grades are not available in the DR-208 package.
8. This text does not indicate orientation of the actual part-marking.
4
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
03/18/03
1
2
3
4
5
6
A
I/O19L
I/O 18L
VSS
TDO
NC
A16L
B
I/O20R
VSS
I/O18R
TDI
A17L (4)
C
V DD QL
I/O 19R
VDD QR
VDD
D
I/O22L
VSS
I/O21L
I/O20L
E
I/O23L
I/O 22R
VD DQ R I/O21R
F
V DD QL
I/O23R
I/O24L
G
I/O26L
VSS
I/O25L
H
VDD
I/O26R
J
VDD QL
VD D
K
I/O28R
L
7
8
9
10 11
12
13 14
15
16 17
A
A12L
A 8L
BE1L
VD D
SEML
INT L
A4L
A0L
OPTL
I/O 17L
A 13L
A9 L
BE2L
CE0L
VSS
BUSYL
A5 L
A 1L
VSS
VDD QR
I/O16L I/O15R
NC
A 14 L
A1 0L
BE3L
CE1L
VSS
R/W L
A6L
A2L
VDD
I/O 16R
I/O15L
A15L
A 11L
A7 L
BE0L
VDD
OEL
NC
A3L
VD D
I/O17R
VD DQ L
I/O14L I/O14R
D
I/O12L
I/O13R
VSS
I/O13L
E
VSS
VSS
I/O12R
I/O 11L
VDD QR
F
I/O 24R
I/O9L
V DD QL
I/O 10L I/O11R
G
VD D
I/O 9R
VSS
I/O10R
H
ZZL
VDD
VSS
V DD QR
J
I/O7R
VD DQL
I/O8R
VSS
K
I/O8L
L
70T651/9BF
BF-208(5,6)
VDD QR I/O25R
VSS
VSS
B
C
VSS
ZZ R
VSS
I/O 27R
VS S
I/O29R
I/O 28L
VD DQ R
I/O27L
I/O 6R
I/O 7L
V SS
M
V DD QL
I/O29L
I/O30R
VSS
VSS
I/O 6L
I/O5R
VDD QR
M
N
I/O31L
VSS
I/O31R
I/O30L
I/O3R
V DD QL
I/O4R
I/O5L
N
P
I/O32R
I/O 32L
VD DQ R I/O3 5R
TRST
A16R
A12R
A 8R
BE1R
V DD
SEMR
INTR
A 4R
I/O2L
I/O3L
V SS
I/O 4L
P
R
VSS
I/O 33L
I/O34R
TCK
A17R(4)
A13R
A9R
BE 2R
CE0R
VSS
BUSY R
A5 R
A1R
VSS
VD DQ L
I/O1R
VDD QR
R
T
I/O33R
I/O 34L
VDD QL
TMS
NC
A14R
A1 0R
BE 3R
CE1R
VSS
R/ WR
A6R
A2R
VS S
I/O 0R
VSS
I/O2R
T
U
VSS
I/O 35L
VD D
NC
A15R
A 11R
A7 R
BE 0R
VDD
OE R
M/ S
A3R
A0R
VDD
OPT R
I/O0L
I/O1L
U
208-Ball
fpBGA
Top View(7)
5632 drw 02e
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All V DDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V DD (2.5V) and 2.5V if OPT pin for that port is
set to V SS (0V).
3. All VSS pins must be connected to ground.
4. A17 X is a NC for IDT70T659.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
5
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
CE0R, CE1R
Chip Enables (Input)
R/WL
R/WR
Read/Write Enable (Input)
Output Enable (Input)
OER
OEL
A0L - A17L
(1)
(1)
A0R - A17R
Address (Input)
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
SEML
SEMR
Semaphore Enable (Input)
INTL
INTR
Interrupt Flag (Output)
BUSYL
BUSYR
Busy Flag (Output)
BE0L - BE3L
BE0R - BE3R
Byte Enables (9-bit bytes) (Input)
VDDQL
VDDQR
Power (I/O Bus) (3.3V or 2.5V)(2) (Input)
OPTL
OPTR
Option for selecting VDDQX(2,3) (Input)
ZZL
ZZR
Sleep Mode Pin(4) (Input)
M/S
Master or Slave Select (Input)(5)
VDD
Power (2.5V)(2) (Input)
VSS
Ground (0V) (Input)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz) (Input)
TMS
Test Mode Select (Input)
TRST
Reset (Initialize TAP Controller) (Input)
NOTES:
1. Address A17x is a NC for IDT70T659.
2. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on I/OX.
3. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPT X is set to VSS (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundry scan not be
operated during sleep mode.
5. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master
(M/S=V IH).
5632 tbl 01
6
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2)
Byte 1
I/O9-17
Byte 0
I/O0-8
H
H
X
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
H
X
L
X
X
X
X
X
L
High-Z
High-Z
High-Z
High-Z
Deselected–Power Down
X
H
L
H
H
H
H
H
X
L
High-Z
High-Z
High-Z
High-Z
All Bytes Deselected
X
H
L
H
H
H
H
L
L
L
High-Z
High-Z
High-Z
DIN
Write to Byte 0 Only
X
H
L
H
H
H
L
H
L
L
High-Z
High-Z
DIN
High-Z
Write to Byte 1 Only
X
H
L
H
H
L
H
H
L
L
High-Z
DIN
High-Z
High-Z
Write to Byte 2 Only
X
H
L
H
L
H
H
H
L
L
DIN
High-Z
High-Z
High-Z
Write to Byte 3 Only
X
H
L
H
H
H
L
L
L
L
High-Z
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
X
H
L
H
L
L
H
H
L
L
DIN
DIN
High-Z
High-Z
Write to Upper 2 bytes Only
X
H
L
H
L
L
L
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
L
H
L
H
H
H
H
L
H
L
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
H
L
H
H
H
L
H
H
L
High-Z
High-Z
DOUT
High-Z
Read Byte 1 Only
L
H
L
H
H
L
H
H
H
L
High-Z
DOUT
High-Z
High-Z
Read Byte 2 Only
L
H
L
H
L
H
H
H
H
L
DOUT
High-Z
High-Z
High-Z
L
H
L
H
H
H
L
L
H
L
High-Z
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
L
H
L
H
L
L
H
H
H
L
DOUT
DOUT
High-Z
High-Z
Read Upper 2 Bytes Only
L
H
L
H
L
L
L
L
H
L
DOUT
DOUT
DOUT
DOUT
X
X
BE3
BE2
BE1
BE0
ZZ
Byte 2
I/O18-26
CE1
SEM
R/W
Byte 3
I/O27-35
CE0
OE
MODE
Read Byte 3 Only
Read All Bytes
H
H
L
H
L
L
L
L
X
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
X
X
X
X
H
High-Z
High-Z
High-Z
High-Z
High-Z Sleep Mode
NOTES:
1. "H" = V IH, "L" = VIL, "X" = Don't Care.
2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
5632 tbl 02
Truth Table II – Semaphore Read/Write Control(1)
Inputs(1)
Outputs
CE(2)
R/W
OE
BE3
BE2
BE1
BE0
SEM
I/O1-35
I/O0
H
H
L
L
L
L
L
L
DATAOUT
DATAOUT
Read Data in Semaphore Flag(3)
H
↑
X
X
X
X
L
L
X
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
X
X
X
X
L
______
______
Mode
Not Allowed
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A 0-A2.
2. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
3. Each byte is controlled by the respective BEn. To read data BEn = VIL.
7
5632 tbl 03
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Commercial
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Ambient
Temperature
GND
0OC to +70OC
Industrial
VDD
VDD
2.5V + 100mV
0V
-40OC to +85OC
2.5V + 100mV
0V
5632 tbl 04
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
CIN
COUT(3)
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max.
Unit
VIN = 3dV
8
pF
VOUT = 3dV
10.5
pF
VTERM
(V DD)
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
Typ.
Max.
Unit
2.4
2.5
2.6
V
(3)
2.4
2.5
2.6
V
0
0
0
V
1.7
____
VDDQ + 100mV (2)
V
1.7
____
VDD + 100mV(2)
V
VDD - 0.2V
____
VDD + 100mV(2)
V
VDDQ
I/O Supply Voltage
VSS
Ground
V IH
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
V IH
Input High Voltage
JTAG
V IH
Input High Voltage ZZ, OPT, M/S
VIL
Input Low Voltage
-0.3(1)
____
0.7
V
VIL
Input Low Voltage ZZ, OPT, M/S
-0.3(1)
____
0.2
V
_
Recommended DC Operating
Conditions with VDDQ at 3.3V
Absolute Maximum Ratings(1)
Commercial
& Industrial
Parameter
5632 tbl 05
5632 tbl 08
Rating
Min.
Core Supply Voltage
NOTES:
1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is
less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VSS(0V), and V DDQX for that port must be
supplied as indicated above.
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
Symbol
Preliminary
Industrial and Commercial Temperature Ranges
Symbol
Unit
V
Min.
Typ.
Max.
Unit
V DD
Core Supply Voltage
Parameter
2.4
2.5
2.6
V
VDDQ
I/O Supply Voltage (3)
3.15
3.3
3.45
V
V SS
Ground
0
0
0
V
2.0
____
VDDQ + 150mV(2)
V
1.7
____
V DD + 100mV (2)
V
VDD - 0.2V
____
V DD + 100mV (2)
V
-0.3(1)
____
0.8
V
(1)
____
0.2
VTERM(2)
(V DDQ )
VDDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
V
VIH
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
VTERM(2)
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
-0.3 to VDDQ + 0.3
V
VIH
Input High Voltage
JTAG
TBIAS(3)
Temperature
Under Bias
-55 to +125
o
C
VIH
Input High Voltage ZZ, OPT, M/S
TSTG
Storage
Temperature
-65 to +150
o
C
VIL
Input Low Voltage
VIL
Input Low Voltage ZZ, OPT, M/S
TJN
Junction Temperature
+150
IOUT(For VDDQ = 3.3V) DC Output Current
50
IOUT(For VDDQ = 2.5V) DC Output Current
40
o
C
_
-0.3
V
5632 tbl 06
NOTES:
1. VIL (min.) = -1.0V for pulse width less than t RC/2 or 5ns, whichever is less.
2. VIH (max.) = V DDQ + 1.0V for pulse width less than t RC/2 or 5ns, whichever is
less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be
supplied as indicated above.
mA
mA
5632 tbl 07
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any Input or I/O pin cannot exceed VDDQ during power
supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
8
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T651/9S
Symbol
Parameter
Test Conditions
Input Leakage Current(1)
|ILI|
(1,2)
|ILI|
JTAG & ZZ Input Leakage Current
(1,3)
|ILO|
Min.
Max.
Unit
VDDQ = Max., VIN = 0V to VDDQ
___
10
µA
VDD = Max. , VIN = 0V to VDD
___
+30
µA
Output Leakage Current
CE0 = V IH or CE 1 = VIL, VOUT = 0V to VDDQ
___
10
µA
VOL (3.3V)
Output Low Voltage (1)
IOL = +4mA, VDDQ = Min.
___
0.4
V
VOH (3.3V)
Output High Voltage
(1)
IOH = -4mA, VDDQ = Min.
2.4
___
V
VOL (2.5V)
Output Low Voltage (1)
IOL = +2mA, VDDQ = Min.
___
0.4
V
VOH (2.5V)
Output High Voltage (1)
IOH = -2mA, VDDQ = Min.
2.0
___
V
5632 tbl 09
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to page 6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 2.5V ± 100mV)
70T651/9S8(7)
Com'l Only
Symbol
IDD
(6)
ISB1
ISB2(6)
ISB3
(6)
ISB4
IZZ
Parameter
Test Condition
Version
70T651/9S10
Com'l
& Ind(7)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Typ.(4)
Max.
Unit
mA
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled
f = fMAX(1)
COM'L
S
350
475
300
405
300
355
225
305
IND
S
____
____
300
445
300
395
____
____
Standby Current
(Both Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L
S
115
140
90
120
75
105
60
85
IND
S
____
____
90
145
75
130
____
____
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(5)
Active Port Outputs Disabled,
f = fMAX(1)
COM'L
S
240
315
200
265
180
230
150
200
IND
S
____
____
200
290
180
255
____
____
COM'L
S
2
10
2
10
2
10
2
10
IND
S
____
____
2
20
2
20
____
____
Full Standby Current Both Ports CEL and
(Both Ports - CMOS CER > VDD - 0.2V, VIN > VDD - 0.2V
Level Inputs)
or VIN < 0.2V, f = 0(2)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDD - 0.2V COM'L
VIN > VDD - 0.2V or VIN < 0.2V, Active
IND
Port, Outputs Disabled, f = fMAX(1)
S
240
315
200
265
180
230
150
200
S
____
____
200
290
180
255
____
____
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR = VIH
f = fMAX(1)
COM'L
S
2
10
2
10
2
10
2
10
IND
S
____
____
2
20
2
20
____
____
(5)
mA
mA
mA
mA
mA
5632 tbl 10
NOTES:
1. At f = f MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input
levels of GND to 3.3V.
2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, T A = 25°C for Typ, and are not production tested. IDD DC(f=0) = 100mA (Typ).
5. CE X = VIL means CE0X = VIL and CE1X = VIH
CE X = VIH means CE0X = VIH or CE1X = V IL
CE X < 0.2V means CE0X < 0.2V and CE1X > VDDQX - 0.2V
CE X > VDDQX - 0.2V means CE 0X > VDDQX - 0.2V or CE1X < 0.2V.
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (I SB3) on the appropriate port(s) if ZZL and /or ZZ R = VIH.
7. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
9
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
GND to 3.0V / GND to 2.4V
Input Pulse Levels
2ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
1.5V/1.25V
Output Reference Levels
1.5V/1.25V
Figure 1
Output Load
5632 tbl 11
50Ω
50Ω
DATAOUT
1.5V/1.25
10pF
(Tester)
5632 drw 03
Figure 1. AC Output Test load.
4
3.5
3
∆ tAA/tACE
(Typical, ns)
2.5
2
1.5
1
0.5
0
0
20
40
60
80
100
120
∆ Capacitance (pF) from AC Test Load
140
5632 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
10
160
,
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70T651/9S8(5)
Com'l Only
Symbol
Parameter
Min.
Max.
70T651/9S10
Com'l
& Ind(5)
Min.
Max.
70T651/9S12
Com'l
& Ind
Min.
Max.
70T651/9S15
Com'l Only
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
8
____
10
____
12
____
15
____
ns
____
8
____
10
____
12
____
tAA
Address Access Time
15
ns
tACE
Chip Enable Access Time
(3)
____
8
____
10
____
12
____
15
ns
tABE
Byte Enable Access Time (3)
____
4
____
5
____
6
____
7
ns
tAOE
Output Enable Access Time
____
4
____
5
____
6
____
7
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time Chip Enable and Semaphore (1,2)
3
____
3
____
3
____
3
____
ns
0
____
0
____
0
____
0
____
ns
0
3.5
0
4
0
6
0
8
ns
0
____
0
____
0
____
0
____
ns
____
7
____
8
____
8
____
12
ns
____
4
____
4
____
6
____
8
ns
2
8
2
10
2
12
2
15
ns
____
5
____
5
____
6
____
7
tLZOB
Output Low-Z Time Output Enable and Byte Enable
(1,2)
(1,2)
tHZ
Output High-Z Time
tPU
Chip Enable to Power Up Time (2)
(2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
tSOE
Semaphore Output Enable Access Time
ns
5632tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70T651/9S8(5)
Com'l Only
Symbol
Parameter
70T651/9S10
Com'l
& Ind(5)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
8
____
10
____
12
____
15
____
ns
tEW
Chip Enable to End-of-Write
(3)
6
____
7
____
9
____
12
____
ns
tAW
Address Valid to End-of-Write
6
____
7
____
9
____
12
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
6
____
7
____
9
____
12
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
4
____
5
____
7
____
10
____
ns
tDH
Data Hold Time
0
____
0
____
0
____
0
____
ns
____
(1,2)
tWZ
Write Enable to Output in High-Z
3.5
____
4
____
6
____
8
ns
tOW
Output Active from End-of-Write (1,2)
3
____
3
____
3
____
3
____
ns
SEM Flag Write to Read Time
4
____
5
____
5
____
5
____
ns
SEM Flag Contention Window
4
____
5
____
5
____
5
____
tSWRD
tSPS
ns
5632 tbl 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE 0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
11
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
(6)
CE
tAOE
(4)
OE
tABE (4)
BEn
R/W
tOH
(1)
tLZ/tLZOB
DATAOUT
VALID DATA
(4)
tHZ
(2)
BUSYOUT
.
tBDD
(3,4)
5632 drw 06
NOTES:
1. Timing depends on which signal is asserted last, OE, CE or BEn.
2. Timing depends on which signal is de-asserted first CE, OE or BEn.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE , tAA, tABE or tBDD .
5. SEM = VIH.
6. CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
50%
50%
ISB
.
5632 drw 07
12
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
(9)
CE or SEM
(9)
BEn
(2)
tAS (6)
tWR
tWP
(3)
R/W
tWZ (7)
tOW
(4)
DATAOUT
(7)
(4)
tDW
tDH
DATAIN
.
5632 drw 10
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5,8)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tWR(3)
tEW (2)
BEn(9)
R/W
tDW
tDH
DATAIN
.
5632 drw 11
.
NOTES:
1. R/W or CE or BEn = VIH during all address transitions for Write Cycles 1 and 2.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL, BEn = VIL, and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of CE, BEn or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW . If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP .
9. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL
and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
13
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
RapidWrite Mode Write Cycle
Preliminary
Industrial and Commercial Temperature Ranges
taken to still meet the Write Cycle time (tWC), the time in which the Address
inputs must be stable. Input data setup and hold times (tDW and tDH) will
now be referenced to the ending address transition. In this RapidWrite
Mode the I/O will remain in the Input mode for the duration of the operations
due to R/W being held low. All standard Write Cycle specifications must
be adhered to. However, tAS and tWR are only applicable when switching
between read and write operations. Also, there are two additional
conditions on the Address Inputs that must also be met to ensure correct
address controlled writes. These specifications, the Allowable Address
Skew (tAAS) and the Address Rise/Fall time (tARF), must be met to use the
RapidWrite Mode. If these conditions are not met there is the potential for
inadvertent write operations at random intermediate locations as the
device transitions between the desired write addresses.
Unlike other vendors' Asynchronous Random Access Memories,
the IDT70T651/9 is capable of performing multiple back-to-back write
operations without having to pulse the R/W, CE, or BEn signals high
during address transitions. This RapidWrite Mode functionality allows the
system designer to achieve optimum back-to-back write cycle performance
without the difficult task of generating narrow reset pulses every cycle,
simplifying system design and reducing time to market.
During this new RapidWrite Mode, the end of the write cycle is now
defined by the ending address transition, instead of the R/W or CE or BEn
transition to the inactive state. R/W, CE, and BEn can be held active
throughout the address transition between write cycles. Care must be
Timing Waveform of Write Cycle No. 3, RapidWrite Mode Write Cycle(1,3)
(4)
tWC
tWC
tWC
ADDRESS
(2)
CE or SEM
(6)
tEW
BEn
tWR
tWP
R/W
(5)
(5)
tWZ
tOW
DATAOUT
tDH
tDH
tDW
tDW
tDH
tDW
DATAIN
5632 drw 08
NOTES:
1. OE = VIL for this timing waveform as shown. OE may equal VIH with same write functionality; I/O would then always be in High-Z state.
2. A write occurs during the overlap (tEW or tWP) of a CE = V IL, BEn = VIL, and a R/W = VIL for memory array writing cycle. The last transition LOW of CE, BEn, and
R/W initiates the write sequence. The first transition HIGH of CE, BEn, and R/W terminates the write sequence.
3. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
4. The timing represented in this cycle can be repeated multiple times to execute sequential RapidWrite Mode writes.
5. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
6. To access RAM, CE = V IL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. CE = V IL when CE0 = V IL
and CE1 = VIH. CE = V IH when CE0 = VIH and/or CE1 = VIL.
14
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics over the Operating Temperature Range
and Supply Voltage Range for RapidWrite Mode Write Cycle(1)
Symbol
Parameter
Min
tAAS
Allowable Address Skew for RapidWrite Mode
____
tARF
Address Rise/Fall Time for RapidWrite Mode
1.5
Max
Unit
1
ns
____
V/ns
5632 tbl 14
NOTE:
1. Timing applies to all speed grades when utilizing the RapidWrite Mode Write Cycle.
Timing Waveform of Address Inputs for RapidWrite Mode Write Cycle
A0
tARF
tAAS
(1)
A17
tARF
5632 drw 09
NOTE:
1. A16 for IDT70T659.
15
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
VALID ADDRESS
tWR
tACE
tEW
SEM(1)
tOH
tSOP
tDW
I/O
DATAOUT(2)
VALID
DATA IN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tSOE
tSOP
Write Cycle
Read Cycle
5632 drw 12
.
NOTES:
1. CE0 = VIH and CE1 = VIL are required for the duration of both the write cycle and the read cycle waveforms shown above. Refer to Truth Table II for details and for
appropriate BEn controls.
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
5632 drw 13 .
NOTES:
1. DOR = D OL = VIL, CEL = CE R = VIH. Refer to Truth Table II for appropriate BE controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
16
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70T651/9S8(6)
Com'l Only
Symbol
Parameter
70T651/9S10
Com'l
& Ind(6)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH)
tBAA
BUSY Access Time from Address Match
____
8
____
10
____
12
____
15
ns
tBDA
BUSY Disable Time from Address Not Matched
____
8
____
10
____
12
____
15
ns
tBAC
BUSY Access Time from Chip Enable Low
____
8
____
10
____
12
____
15
ns
tBDC
BUSY Disable Time from Chip Enable High
____
8
____
10
____
12
____
15
ns
tAPS
Arbitration Priority Set-up Time (2)
2.5
____
2.5
____
2.5
____
2.5
____
ns
____
8
____
10
____
12
____
15
ns
6
____
7
____
9
____
12
____
ns
tBDD
tWH
(3)
BUSY Disable to Valid Data
Write Hold After BUSY
(5)
BUSY TIMING (M/S=VIL)
tWB
BUSY Input to Write(4)
0
____
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
6
____
7
____
9
____
12
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay (1)
____
12
____
14
____
16
____
20
ns
tDDD
Write Data Valid to Read Data Delay (1)
____
12
____
14
____
16
____
20
ns
5632 tbl 15
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2,3)
70T651/9S8(4)
Com'l Only
Symbol
Parameter
70T651/9S10
Com'l
& Ind(4)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
SLEEP MODE TIMING (ZZx=V IH)
tZZS
Sleep Mode Set Time
8
____
10
____
12
____
15
____
tZZR
Sleep Mode Reset Time
8
____
10
____
12
____
15
____
tZZPD
Sleep Mode Power Down Time (5)
8
____
10
____
12
____
15
____
tZZPU
Sleep Mode Power Up Time (5)
____
0
____
0
____
0
____
0
5632 tbl 15a
NOTES:
1. Timing is the same for both ports.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep mode pins themselves (ZZx) are not affected
during sleep mode. It is recommended that boundary scan not be operated during sleep mode.
3. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
4. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
5. This parameter is guaranteed by device characterization, but is not production tested.
17
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD (3)
.
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CE0L = CE0R = VIL; CE1L = CE1R = VIH.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = VIL)
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH
R/W"B"
(1)
(2)
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH.
3. tWB only applies to the slave mode.
5632 drw 15
18
.
5632 drw 14
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS (2)
CE"B"
tBAC
tBDC
BUSY"B"
.
5632 drw 16
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1,3,4)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
,
5632 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. CEX = VIL when CE0X = VIL and CE1X = VIH. CEX = VIH when CE 0X = VIH and/or CE1X = VIL.
4. CE0X = OEX = BEnX = VIL. CE1X = VIH.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
70T651/9S8(3)
Com'l Only
Symbol
Parameter
70T651/9S10
Com'l
& Ind(3)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
8
____
10
____
12
____
15
ns
tINR
Interrupt Reset Time
____
8
____
10
____
12
____
15
NOTES:
1. Timing is the same for both ports.
2. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
3. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
19
ns
5632 tbl 16
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1)
tWC
(2)
ADDR"A"
INTERRUPT SET ADDRESS
tWR (5)
tAS(4)
CE"A"(3)
R/W"A"
tINS
(4)
INT"B"
.
5632 drw 18
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS
(2)
(4)
CE"B"(3)
OE"B"
tINR (4)
INT"B"
5632 drw 19
.
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. CEX = VIL means CE0X = VIL and CE 1X = V IH. CEX = VIH means CE0X = VIH and/or CE1X = VIL.
4. Timing depends on which enable signal (CE or R/W) is asserted last.
5. Timing depends on which enable signal (CE or R/W) is de-asserted first.
Truth Table III — Interrupt Flag(1,4)
Left Port
R/WL
CEL
OEL
Right Port
(5)
A17L-A0L
INTL
R/WR
CER
OER
A17R-A0R(5)
INTR
(2)
Function
L
L
X
3FFFF
X
X
X
X
X
L
Set Right INTR Flag
X
X
X
X
X
X
L
L
3FFFF
H(3)
Reset Right INTR Flag
X
X
X
X
L(3)
L
L
X
3FFFE
X
Set Left INTL Flag
X
L
L
3FFFE
H(2)
X
X
X
X
X
Reset Left INTL Flag
NOTES:
1. Assumes BUSYL = BUSYR =VIH. CE0X = VIL and CE1X = VIH.
2. If BUSYL = V IL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A17x is a NC for IDT70T659. Therefore, Interrupt Addresses are 1FFFF and 1FFFE.
20
5632 tbl 17
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table IV —
Address BUSY Arbitration
Inputs
CEL(5) CER(5)
Outputs
AOL-A17L(4)
AOR-A17R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
5632 tbl 18
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70T651/9 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A17 is a NC for IDT70T659. Address comparison will be for A0 - A 16.
5. CEX = L means CE 0X = V IL and CE 1X = V IH. CEX = H means CE0X = VIH and/or CE1X = V IL.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D35 Left
D0 - D35 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T651/9.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35 ). These eight semaphores are addressed by A0 - A2.
3. CE = VIH, SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
5632 tbl 19
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 3FFFE when CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (INTR) is asserted when the left port
writes to memory location 3FFFF (HEX) and to clear the interrupt
flag (INTR), the right port must read the memory location 3FFFF. The
message (36 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70T659)
is user-defined since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FFFE and 3FFFF are not used
The IDT70T651/9 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T651/9 has an automatic power down
feature controlled by CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = HIGH). When a port is enabled, access to the
entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
21
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
as mail boxes, but as part of the random access memory. Refer to Truth
Table III for the interrupt operation.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70T651/9 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
Semaphores
The IDT70T651/9 is an extremely fast Dual-Port 256/128K x 36
CMOS Static RAM with an additional 8 address locations dedicated to
binary semaphore flags. These flags allow either processor on the left or
right side of the Dual-Port RAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port RAM or any other
shared resource.
The Dual-Port RAM features a fast access time, with both ports
being completely independent of each other. This means that the
activity on the left port in no way slows the access time of the right port.
Both ports are identical in function to standard CMOS Static RAM and
can be read from or written to at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic power-down
feature controlled by CE0 and CE1, the Dual-Port RAM chip enables, and
SEM, the semaphore enable. The CE0, CE1, and SEM pins control onchip power down circuitry that permits the respective port to go into standby
mode when not selected.
Systems which can best use the IDT70T651/9 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70T651/9s
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70T651/9 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
A18
CE0
MASTER
Dual Port RAM
BUSYL
BUSYR
CE0
SLAVE
Dual Port RAM
BUSYL
BUSYR
CE1
MASTER
Dual Port RAM
CE1
SLAVE
Dual Port RAM
BUSYL
BUSYL
BUSYR
BUSYR
5632 drw 20
Preliminary
Industrial and Commercial Temperature Ranges
.
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70T651/9 Dual-Port RAMs.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70T651/9 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAMs
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master use the BUSY signal as a write inhibit signal. Thus on the
IDT70T651/9 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
22
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
the gap between the read and write cycles.
It is important to note that a failed semaphore request must be followed
by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore
request latches feed into a semaphore flag. Whichever latch is first to
present a zero to the semaphore flag will force its side of the semaphore
flag LOW and the other side HIGH. This condition will continue until a one
is written to the same semaphore request latch. If the opposite side
semaphore request latch has been written to zero in the meantime, the
semaphore flag will flip over to the other side as soon as a one is written
into the first request latch. The opposite side flag will now stay LOW until
its semaphore request latch is written to a one. From this it is easy to
verifies its success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side processor
has set the latch first, has the token and is using the shared resource.
The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70T651/9 in a
separate memory space from the Dual-Port RAM. This address space
is accessed by placing a low input on the SEM pin (which acts as a chip
select for the semaphore flags) and using the other control pins (Address,
CE0, CE1,R/W and BEn) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which can
be accessed by either side through address pins A0 – A2. When accessing
the semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low level
is written into an unused semaphore location, that flag will be set to
a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the flag
will be set to a one for both sides (unless a semaphore request
from the other side is pending) and then can be written to by both sides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thorough
discussion on the use of this feature follows shortly.) A zero written into the
same location from the other side will be stored in the semaphore request
latch for that side until the semaphore is freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros for a semaphore read, the SEM, BEn, and OE
signals need to be active. (Please refer to Truth Table II). Furthermore,
the read value is latched into one side’s output register when that side's
semaphore select (SEM, BEn) and output enable (OE) signals go active.
This serves to disallow the semaphore from changing state in the middle
of a read cycle due to a write cycle from the other side.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side
during subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
Q
SEMAPHORE
READ
Figure 4. IDT70T651/9 Semaphore Logic
D
D0
WRITE
SEMAPHORE
READ
5632 drw 21
understand that, if a semaphore is requested and the processor which
requested it no longer needs the resource, the entire system can hang up
until a one is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one,
all semaphores on both sides should have a one written into them
at initialization from both sides to assure that they will be free
when needed.
23
24
VALIDDATA
VALIDADDRESS
NOTES:
1. CE1 = V IH.
2. All timing is same for Left and Right ports.
IDD
DATA
ADDRESS
ZZ
CE0
Normal Operation
tZZS
tZZPD
No newreads or writes allowed
Timing Waveform of Sleep Mode(1,2)
IZZ
Sleep Mode
tZZPU
tZZR
No reads or writes allowed
,
5632 drw22
Normal Operation
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Sleep Mode
The IDT70T651/9 is equipped with an optional sleep or low power
mode on both ports. The sleep mode pin on both ports is active high. During
normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the
port will enter sleep mode where it will meet lowest possible power
conditions. The sleep mode timing diagram shows the modes of operation:
Normal Operation, No Read/Write Allowed and Sleep Mode.
For a period of time prior to sleep mode and after recovering from sleep
mode (tZZS and tZZR), new reads or writes are not allowed. If a write or read
operation occurs during these periods, the memory array may be
corrupted. Validity of data out from the RAM cannot be guaranteed
immediately after ZZ is asserted (prior to being in sleep).
During sleep mode the RAM automatically deselects itself. The RAM
disconnects its internal buffer. All outputs will remain in high-Z state while
in sleep mode. All inputs are allowed to toggle. The RAM will not be selected
and will not perform any reads or writes.
JTAG Timing Specifications
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
x
5632 drw 23
tJRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4,5)
70T651/9
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
(1)
tJR
JTAG Clock Rise Time
____
3
ns
tJF
JTAG Clock Fall Time
____
3(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
5. JTAG cannot be tested in sleep mode.
ns
5632 tbl 20
25
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Revision Number (31:28)
Description
0x0
IDT Device ID (27:12)
0x338(1)
IDT JEDEC ID (11:1)
0x33
ID Register Indicator Bit (Bit 0)
Reserved for version number
Defines IDT part number 70T651
Allows unique identification of device vendor as IDT
1
Indicates the presence of an ID register
5632 tbl 21
NOTE:
1. Device ID for IDT70T659 is 0x339.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
4
Bypass (BYR)
1
Identification (IDR)
Boundary Scan (BSR)
32
Note (3)
5632 tbl 22
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs (1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
1111
Places the bypass register (BYR) between TDI and TDO.
IDCODE
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
HIGHZ
CLAMP
0011
SAMPLE/PRELOAD
0001
RESERVED
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs (2) and outputs (1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
Several combinations are reserved. Do not use codes other than those
identified above.
All Other Codes
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, TCK and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
26
5632 tbl 23
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
Device
Type
A
999
A
A
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BC
DR
BF
256-ball BGA (BC-256)
208-pin PQFP (DR-208)
208-ball fpBGA (BF-208)
8
10
12
15
Commercial Only(1)
Commercial & Industrial(1)
Commercial & Industrial
Commercial Only
S
Standard Power
.
Speed in nanoseconds
70T651 9Mbit (256K x 36) Asynchronous Dual-Port RAM
70T659 4Mbit (128K x 36) Asynchronous Dual-Port RAM
5632 drw 24
NOTE:
1. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions for products that are in early release.
Datasheet Document History:
04/25/03: Initial Datasheet
10/01/03: Page 9 Added 8ns speed DC power numbers to DC Electrical Characteristics Table
Page 9 Updated DC power numbers for 10, 12 & 15ns speeds in the DC Electrical Characteristics Table
Page 9, 11, 15, 17 & 25 Added footnote that indicates that 8ns speed is available in BF-208 and BC-256 packages only
Page 10 Added Capacitance Derating Drawing
Page 11, 15 & 17 Added 8ns AC timing numbers to the AC Electrical Characteristics Tables
Page 11 Added tSOE and tLZOB to the AC Read Cycle Electrical Characteristics Table
Page 12 Added tLZOB to the Waveform of Read Cycles Drawing
Page 14 Added tSOE to Timing Waveform of Semaphore Read after Write Timing, Either Side Drawing
Page 1 & 25 Added 8ns speed grade and 10ns I-temp to features and to ordering information
Page 1, 14 & 15 Added RapidWrite Mode Write Cycle text and waveforms
10/20/03:
Page 15 Corrected tARF to 1.5V/ns Min.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
27
for Tech Support:
831-754-4613
[email protected]
Similar pages