MOTOROLA MCM6323ATS10R 64k x 16 bit 3.3 v asynchronous fast static ram Datasheet

MOTOROLA
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by MCM6323A/D
SEMICONDUCTOR TECHNICAL DATA
MCM6323A
Product Preview
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
YJ PACKAGE
400 MIL SOJ
CASE 919–01
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) package and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
•
•
•
•
•
•
•
•
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–01
PIN ASSIGNMENT
Single 3.3 V ± 0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: – 40 to + 85°C
Part Number: SCM6323AYJ10A
A
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
16
E
W
9
HIGH
BYTE
OUTPUT
BUFFER
ROW
COLUMN
DECODER DECODER
8
CHIP
ENABLE
BUFFER
WRITE
ENABLE
BUFFER
64K x 16
BIT
MEMORY
ARRAY
16
LOW
BYTE
OUTPUT
BUFFER
8
UB
BYTE
ENABLE
BUFFER
LOW
BYTE
WRITE
DRIVER
A
3
42
A
A
4
41
G
A
5
40
UB
E
6
39
LB
38
DQb
8
37
DQb
DQa
DQa
9
10
36
35
DQb
DQb
VDD
VSS
DQa
11
34
12
13
33
32
VSS
VDD
DQb
DQa
14
31
DQb
DQa
15
30
DQb
8 DQb
DQa
16
29
DQb
8
W
17
28
NC
A
18
27
A
A
19
26
A
A
A
20
21
25
24
A
A
NC
22
23
NC
8
SENSE
AMPS
8
LB
HIGH
BYTE
WRITE
DRIVER
A
A
7
LOW BYTE OUTPUT ENABLE
8
44
43
DQa
HIGH BYTE OUTPUT ENABLE
7
1
2
DQa
BLOCK DIAGRAM
G
A
A
8 DQa
PIN NAMES
8
8
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
A . . . . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte
LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte
DQa . . . . . . . . . . . . Lower Data Input/Output
DQb . . . . . . . . . . . . Upper Data Input/Output
VDD . . . . . . . . . . . . . . + 3.3 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
REV 1
10/17/97

Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM6323A
1
TRUTH TABLE (X = Don’t Care)
E
G
W
LB
UB
Mode
VDD Current
DQa’s
DQb’s
H
X
X
X
X
Not Selected
ISB1, ISB2
High–Z
High–Z
L
H
H
X
X
Output Disabled
IDDA
High–Z
High–Z
L
X
X
H
H
Output Disabled
IDDA
High–Z
High–Z
L
L
H
L
H
Low Byte Read
IDDA
Dout
High–Z
L
L
H
H
L
High Byte Read
IDDA
High–Z
Dout
L
L
H
L
L
Word Read
IDDA
Dout
Dout
L
X
L
L
H
Low Byte Write
IDDA
Din
High–Z
L
X
L
H
L
High Byte Write
IDDA
High–Z
Din
L
X
L
L
L
Word Write
IDDA
Din
Din
ABSOLUTE MAXIMUM RATINGS (See Notes)
Symbol
Value
Unit
VDD
– 0.5 to + 4.6
V
Voltage on Any Pin
Vin
– 0.5 to VDD + 0.5
V
Output Current per Pin
Iout
± 20
mA
Rating
Supply Voltage
Package Power Dissipation
PD
.75
W
Temperature Under Bias
Commerial
Industrial
Tbias
– 10 to + 85
– 45 to + 90
°C
Operating Temperature
Commerial
Industrial
TA
0 to + 70
– 40 to + 85
°C
Tstg
– 55 to + 150
°C
Storage Temperature
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment.
MCM6323A
2
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.2
—
VDD + 0.3**
V
Input Low Voltage
VIL
– 0.5*
—
0.8
V
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Ilkg(O)
—
± 1.0
µA
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter
Output Low Voltage
(IOL = + 4.0 mA)
(IOL = + 100 µA)
VOL
—
0.4
VSS + 0.2
V
Output High Voltage
(IOH = – 4.0 mA)
(IOH = – 100 µA)
VOH
2.4
VDD – 0.2
—
V
POWER SUPPLY CURRENTS (See Note 1)
Symbol
6323A–10
6323A–12
6323A–15
Unit
Notes
AC Active Supply Current (Iout = 0 mA)
(VDD = max, f = fmax)
Commerical
Industrial
IDDA
140
150
135
140
130
135
mA
2
AC Standby Current (E = VIH, VDD = max,
f = fmax)
Commerical
Industrial
ISB1
40
45
35
40
30
35
mA
2
CMOS Standby Current (VDD = max, f = 0 MHz,
E ≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V,
or ≥ VDD – 0.2 V)
Commerical
Industrial
ISB2
5
5
5
5
5
5
mA
Parameter
NOTES:
1. Typical current = 25°C @ 3.3 V.
2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Typ
Max
Unit
Address Input Capacitance
Cin
—
6
pF
Control Input Capacitance
Cin
—
6
pF
Input/Output Capacitance
CI/O
—
8
pF
Parameter
MOTOROLA FAST SRAM
MCM6323A
3
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V ± 0.3 V, TA = 0 to +70°C, Unless Otherwise Noted)
(TA = – 40 to + 85°C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level . . . . . . . . 1.50 V
Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.50 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
READ CYCLE TIMING (See Notes 1, 2, 3, and 4)
MCM6323A–10
P
Parameter
MCM6323A–12
MCM6323A–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Read Cycle Time
tAVAV
10
—
12
—
15
—
ns
5
Address Access Time
tAVQV
—
10
—
12
—
15
ns
Enable Access Time
tELQV
—
10
—
12
—
15
ns
Output Enable Access Time
tGLQV
—
4
—
5
—
6
ns
Output Hold from Address Change
tAXQX
3
—
3
—
3
—
ns
Enable Low to Output Active
tELQX
3
—
3
—
3
—
ns
6, 7, 8
Output Enable Low to Output Active
tGLQX
0
—
0
—
0
—
ns
6, 7, 8
Enable High to Output High–Z
tEHQZ
—
4
—
5
—
6
ns
6, 7, 8
Output Enable High to Output High–Z
tGHQZ
—
4
—
5
—
6
ns
6, 7, 8
Byte Enable Access Time
tBLQV
—
4
—
5
—
6
ns
Byte Enable Low to Output Active
tBLQX
0
—
0
—
0
—
ns
6, 7, 8
Byte High to Output High–Z
tBHQZ
0
5
0
5
0
5
ns
6, 7, 8
6
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.
3. Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL).
4. Addresses valid prior to or coincident with E going low.
5. All read cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured 200 mV from steady–state voltage.
7. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from
device to device.
8. This parameter is sampled and not 100% tested.
MCM6323A
4
MOTOROLA FAST SRAM
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
30 pF
1.5 V
Figure 1. Equivalent AC Test Load
2.0
OUTPUT
CL
DELTA TIME DELAY (ns)
1.5
1.0
0.5
0
– 0.5
0
20
40
60
80
100
LUMPED CAPACITANCE, CL (pF)
@ T = 25°C, VDD = 3.3 V
+0.3
DELTA TIME DELAY (ns)
DELTA TIME DELAY (ns)
Figure 2. Lumped Capacitive Load and Typical Derating Curve
+0.2
+0.1
0
+0.3
+0.2
+0.1
0
–0.1
–0.1
–0.2
– 0.2
– 0.3
3.0
3.1
3.2
3.3
3.4
VDD (V)
@ T = 25°C
3.5
3.6
–50
OUTPUT
–25
30 pF
0
25
50
75
100
T (°C)
@ VDD = 3.3 V
Figure 3. Derating Across Temperature and Voltage
MOTOROLA FAST SRAM
MCM6323A
5
READ CYCLE 1 (See Note 7)
tAVAV
A (ADDRESS)
tAXQX
Q (DATA OUT)
PREVIOUS DATA VALID
DATA VALID
tAVQV
READ CYCLE 2 (See Note 8)
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
LB, UB (BYTE ENABLE)
tBHQZ
tBLQV
tBLQX
Q (DATA OUT)
MCM6323A
6
DATA VALID
MOTOROLA FAST SRAM
WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6323A–10
P
Parameter
MCM6323A–12
MCM6323A–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
tAVAV
10
—
12
—
15
—
ns
3
Address Setup Time
tAVWL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVWH
8
—
9
—
10
—
ns
Write Pulse Width
tWLWH,
tWLEH
8
—
9
—
10
—
ns
Byte Pulse Width
tBLWH,
tBLEH
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVWH
4
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
Write Cycle Time
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled)
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tBLEH
tBLWH
tAVWL
tWHDX
LB, UB (BYTE ENABLE)
tDVWH
D (DATA IN)
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6323A
7
WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6323A–10
P
Parameter
MCM6323A–12
MCM6323A–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
tAVAV
10
—
12
—
15
—
ns
3
Address Setup Time
tAVEL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVEH
8
—
9
—
10
—
ns
Enable to End of Write
tELEH,
tELWH
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVEH
4
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
Write Cycle Time
4, 5
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled)
tAVAV
A (ADDRESS)
tAVEH
tEHAX
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
tDVEH
D (DATA IN)
Q (DATA OUT)
MCM6323A
8
tEHDX
DATA VALID
HIGH–Z
MOTOROLA FAST SRAM
WRITE CYCLE 3 (B Controlled, See Notes 1 and 2)
MCM6323A–10
P
Parameter
MCM6323A–12
MCM6323A–15
S b l
Symbol
Min
Max
Min
Max
Min
Max
U i
Unit
N
Notes
Write Cycle Time
tAVAV
10
—
12
—
15
—
ns
3
Address Setup Time
tAVBL
0
—
0
—
0
—
ns
Address Valid to End of Write
tAVBH
8
—
9
—
10
—
ns
Write Pulse Width
tWLWH,
tWLEH
8
—
9
—
10
—
ns
Byte Pulse Width
tBLWH,
tBLEH,
tBLBH
8
—
9
—
10
—
ns
Data Valid to End of Write
tDVBH
5
—
6
—
7
—
ns
Data Hold Time
tBHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns
4, 5, 6
Write Recovery Time
tBHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
WRITE CYCLE 3
(B Controlled)
tAVAV
A (ADDRESS)
tAVBH
tBHAX
E (CHIP ENABLE)
tBLEH
tBLWH
tBLBH
tAVBL
LB, UB (BYTE ENABLE)
tBHDX
tWLEH
tWLWH
W (WRITE ENABLE)
tDVBH
D (DATA IN)
DATA VALID
tWLQZ
Q (DATA OUT)
HIGH–Z
HIGH–Z
tWHQX
MOTOROLA FAST SRAM
MCM6323A
9
ORDERING INFORMATION
(Order by Full Part Number)
MCM 6323A YJ
XX
Motorola Memory Prefix
X
X
Shipping Method (R = Tape and Reel,
Blank = Rails for SOJ, Blank = Trays for TSOP)
Part Number
Temperature (Blank = Commercial, A = Industrial)
Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns)
Package (YJ = 400 mil SOJ, TS = 44–Lead
TSOP Type II)
MCM6323A
10
Full Commercial Part Numbers — MCM6323AYJ10
MCM6323AYJ10R
MCM6323ATS10
MCM6323ATS10R
MCM6323AYJ12
MCM6323AYJ12R
MCM6323ATS12
MCM6323ATS12R
MCM6323AYJ15
MCM6323AYJ15R
MCM6323ATS15
MCM6323ATS15R
Full Industrial Part Numbers —
SCM6323AYJ12A
SCM6323AYJ12AR
SCM6323ATS12A
SCM6323ATS12AR
SCM6323AYJ15A
SCM6323AYJ15AR
SCM6323ATS15A
SCM6323ATS15AR
SCM6323AYJ10A
SCM6323AYJ10AR
SCM6323ATS10A
SCM6323ATS10AR
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
YJ PACKAGE
400 MIL SOJ
CASE 919–01
44
23
E1
1
22
B
A
D
44X b1
42X
0.007
e
L
C A B
A
A3
SEATING
PLANE
A
e /2
C
44X
0.004 C
b
0.007
M
C A B
E
0.007
A
M
C A B
A2
44X R
E2 /2
A1
0.015 B
22 ZONES 2X
MOTOROLA FAST SRAM
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
R1
DIM
A
A1
A2
A3
b
b1
D
E
E1
E2
e
R1
INCHES
MIN
MAX
0.128
0.148
0.025
–––
0.082
–––
0.035
0.045
0.015
0.020
0.026
0.032
1.120
1.130
0.435
0.445
0.395
0.405
0.370 BSC
0.050 BSC
0.030
0.040
E2
VIEW A–A
MCM6323A
11
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–01
VIEW A
B
4
4
2
(R1)
R
3
(R2)
R
A1
E1
L
A A
q
DETAIL A
ROTATED 90 _ CLOCKWISE
b1
1
22
A
A
D1
BASE METAL
A2
E
C0 A 8
22X
0
.
0M
(
0
.
c1
2
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
ÇÇÇÇ
ÉÉÉÉ
b
0.008 (0.2)
SEATING
PLANE
e /2
C
e
T Z
40 PLACES
0.004 (0.1) C
42X
M
SECTION A–A
44X
4X
c
)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.006 (0.015) PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSIONS SHALL
NOT ALLOW THE b DIMENSION TO EXCEED 0.023
(0.58).
DIM
A
A1
A2
b
b1
c
c1
D1
e
E
E1
L
R1
R2
q
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
–––
0.050
–––
1.270
0.002
0.006
0.051
0.152
0.038
0.042
0.965
1.067
0.012
0.018
0.305
0.457
0.012
0.016
0.305
0.406
0.005
0.008
0.127
0.203
0.004
0.006
0.101
0.152
0.721
0.729 18.313 18.517
0.0315 BSC
0.800 BSC
0.456
0.470 11.582 11.938
0.396
0.404 10.058 10.262
0.016
0.023
0.406
0.584
0.004 REF
0.100 REF
0.004 REF
0.100 REF
0_
5_
0_
5_
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