Samsung K6R4008C1C-E12 512kx8 bit high speed static ram(5v operating). operated at extended and industrial temperature ranges. Datasheet

PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
Document Title
512Kx8 Bit High Speed Static RAM(5V Operating).
Operated at Extended and Industrial Temperature Ranges.
Revision History
Rev No.
History
Draft Data
Remark
Rev. 0.0
Initial release with Preliminary.
Feb. 12. 1999
Preliminary
Rev. 1.0
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics.
1.3 Changed ISB1 to 20mA
Mar. 29. 1999
Preliminary
Rev. 2.0
2.1 Relax D.C parameters.
Aug. 19. 1999
Preliminary
Mar. 27. 2000
Final
Sep. 24. 2001
Final
Item
Previous
170mA
165mA
160mA
12ns
15ns
20ns
ICC
Current
195mA
190mA
185mA
2.2 Relax Absolute Maximum Rating.
Item
Voltage on Any Pin Relative to Vss
Rev. 3.0
Previous
-0.5 to 7.0
Current
-0.5 to Vcc+0.5
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
10ns
12ns
15ns
20ns
ICC
195mA
190mA
185mA
Previous
Isb
Isb1
70mA
20mA
ICC
170mA
160mA
150mA
140mA
Current
Isb
Isb1
60mA
10mA
3.3 Added Extended temperature range
Rev. 4.0
Delete 20ns speed bin
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 60mA(Max.)
(CMOS) : 10mA(Max.)
Operating K6R4008C1C-10 : 170mA(Max.)
K6R4008C1C-12 : 160mA(Max.)
K6R4008C1C-15 : 150mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
K6R4008C1C-J : 36-SOJ-400
K6R4008C1C-T: 44-TSOP2-400BF
The K6R4008C1C is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits.
The K6R4008C1C uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
K6R4008C1C is packaged in a 400 mil 36-pin plastic SOJ and
44-pin plastic TSOP type II.
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 ~I/O8
Pre-Charge Circuit
Row Select
Clk Gen.
ORDERING INFORMATION
Memory Array
1024 Rows
512 x 8 Columns
Data
Cont.
I/O Circuit
Column Select
K6R4008C1C-C10/C12/C15
Commercial Temp.
K6R4008C1C-E10/E12/E15
Extended Temp.
K6R4008C1C-I10/I12/I15
Industrial Temp.
CLK
Gen.
A10 A11 A12 A13 A14 A15 A16 A17 A18
CS
WE
OE
-2-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
PIN CONFIGURATION (Top View)
1
A0
36 N.C
2
A1
35 A18
N.C
1
44 N.C
N.C
2
43 N.C
A0
3
42 N.C
A1
4
A2
3
34 A17
41
A18
A3
4
33 A16
A2
5
40
A17
A4
5
32 A15
A3
6
39
A16
CS
6
31
OE
A4
7
38
A15
I/O1
7
30 I/O8
CS
8
37
OE
I/O1
9
36 I/O8
I/O2
8
Vcc
9
Vss
10
27 Vcc
Vss 12
33 Vcc
I/O3 11
26 I/O6
I/O3 13
32 I/O6
I/O4 12
25 I/O5
I/O4 14
31 I/O5
WE
29 I/O7
36-SOJ
I/O2 10
28 Vss
Vcc 11
24 A14
13
35 I/O7
44-TSOP2
34 Vss
WE
15
30
A14
A5
16
29
A13
A6
17
28
A12
A5
14
23 A13
A6
15
22 A12
A7
18
27
A11
A7
16
21 A11
A8
19
26
A10
A8
17
20 A10
A9
20
25 N.C
A9
18
19 N.C
N.C 21
24 N.C
N.C 22
23 N.C
PIN FUNCTION
Pin Name
A0 - A18
Pin Function
Address Inputs
WE
Write Enable
CS
Chip Select
OE
Output Enable
I/O1 ~ I/O8
Data Inputs/Outputs
VCC
Power(+5.0V)
VSS
Ground
N.C
No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V SS
Symbol
Rating
Unit
VIN, VOUT
-0.5 to VCC+0.5
V
VCC
-0.5 to 7.0
V
Voltage on VCC Supply Relative to VSS
Power Dissipation
Storage Temperature
Operating Temperature
PD
1.0
W
TSTG
-65 to 150
°C
Commercial
TA
0 to 70
°C
Extended
TA
-25 to 85
°C
Industrial
TA
-40 to 85
°C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
-3-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Symbol
Min
Typ
Max
Unit
Supply Voltage
Parameter
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input High Voltage
VIH
2.2
-
VCC+0.5***
V
Input Low Voltage
VIL
-0.5**
-
0.8
V
* The above parameters are also guaranteed at extended and industrial temperature range.
** VIL(Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA.
*** VIH(Max) = V CC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
ILI
VIN=VSS to VCC
-2
2
µA
Output Leakage Current
ILO
CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
-2
2
µA
Operating Current
ICC
Min. Cycle, 100% Duty
CS=VIL, VIN=VIH or VIL, IOUT=0mA
-
170
mA
Com.
10ns
Ext.
Ind.
12ns
-
160
15ns
-
150
10ns
-
185
12ns
-
175
15ns
-
165
ISB
Min. Cycle, CS=VIH
-
60
mA
ISB1
f=0MHz, CS≥VCC-0.2V,
VIN≥VCC-0.2V or VIN≤0.2V
-
10
mA
Output Low Voltage Level
VOL
IOL=8mA
-
0.4
V
Output High Voltage Level
VOH
IOH=-4mA
2.4
-
V
-
3.95
V
Standby Current
VOH1**
IOH1=-0.1mA
* The above parameters are also guaranteed at extended and industrial temperature range.
** VCC=5.0V±5%, Temp.=25°C.
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item
Symbol
Test Conditions
MIN
Max
Unit
Input/Output Capacitance
CI/O
VI/O=0V
-
8
pF
Input Capacitance
CIN
VIN=0V
-
7
pF
* Capacitance is sampled and not 100% tested.
-4-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
* The above test conditions are also applied at extended and industrial temperature range.
Output Loads(A)
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V
RL = 50Ω
DOUT
VL = 1.5V
480Ω
DOUT
30pF*
ZO = 50Ω
255Ω
5pF*
* Including Scope and Jig Capacitance
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
Parameter
Symbol
K6R4008C1C-10
K6R4008C1C-12
K6R4008C1C-15
Unit
Min
Max
Min
Max
Min
Max
tRC
10
-
12
-
15
-
ns
Address Access Time
tAA
-
10
-
12
-
15
ns
Chip Select to Output
tCO
-
10
-
12
-
15
ns
Output Enable to Valid Output
tOE
-
5
-
6
-
7
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
ns
Read Cycle Time
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
5
0
6
0
7
ns
Output Disable to High-Z Output
tOHZ
0
5
0
6
0
7
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
10
-
12
-
15
ns
* The above parameters are also guaranteed at extended and industrial temperature range.
-5-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
WRITE CYCLE*
Parameter
Symbol
K6R4008C1C-10
K6R4008C1C-12
K6R4008C1C-15
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
10
-
12
-
15
-
ns
Chip Select to End of Write
tCW
7
-
8
-
10
-
ns
Address Set-up Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
7
-
8
-
10
-
ns
Write Pulse Width(OE High)
tWP
7
-
8
-
10
-
ns
Write Pulse Width(OE Low)
tWP1
10
-
12
-
15
-
ns
Write Recovery Time
tWR
0
-
0
-
0
-
ns
Write to Output High-Z
tWHZ
0
6
0
6
0
7
ns
Data to Write Time Overlap
tDW
5
-
6
-
7
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
3
-
3
-
3
-
ns
* The above parameters are also guaranteed at extended and industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH )
tRC
Address
tAA
tOH
Data Out
Valid Data
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
(WE=VIH)
tRC
Address
tAA
tCO
CS
tHZ(3,4,5)
tOE
tOHZ
OE
tOH
tOLZ
tLZ(4,5)
Data out
Valid Data
VCC
ICC
Current
ISB
tPU
tPD
50%
50%
NOTES(WRITE CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
-6-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
tWC
Address
tWR(5)
tAW
OE
tCW(3)
CS
tWP(2)
tAS(4)
WE
tDW
Data in
High-Z
tDH
Valid Data
tOHZ(6)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC
Address
tWR(5)
tAW
tCW(3)
CS
tAS(4)
tWP1(2)
WE
tDW
Data in
High-Z
tDH
Valid Data
tWHZ(6)
tOW
(10)
(9)
High-Z(8)
Data out
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC
Address
tAW
tWR(5)
tCW(3)
CS
tAS(4)
tWP(2)
WE
tDW
Data in
High-Z
Valid Data
tLZ
Data out
tDH
High-Z
tWHZ(6)
High-Z(8)
High-Z
-7-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write.
3. t CW is measured from the later of CS going low to end of write.
4. t AS is measured from the address valid to the beginning of write.
5. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
L
H
X*
Not Select
High-Z
ISB, ISB1
H
Output Disable
High-Z
ICC
L
L
H
L
Read
DOUT
ICC
L
X
Write
DIN
ICC
* X means Don′t Care.
-8-
Rev 4.0
September 2001
PRELIMINARY
K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
Units:millimeters/Inches
PACKAGE DIMENSIONS
36-SOJ-400
#19
10.16
0.400
#36
11.18 ±0.12
0.440 ±0.005
9.40 ±0.25
0.370 ±0.010
0.20
#1
+0.10
-0.05
0.008 +0.004
-0.002
#18
0.69
MIN
0.027
23.90 MAX
0.941
23.50 ±0.12
0.925 ±0.005
1.19
)
0.047
1.27
(
)
0.050
(
0.43
( 0.95 )
0.0375
3.76
MAX
0.148
0.10 MAX
0.004
+0.10
-0.05
0.017 +0.004
-0.002
1.27
0.050
0.71 +0.10
-0.05
0.028 +0.004
-0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8°
0.25
0.010 TYP
#23
#44
11.76 ±0.20
0.463 ±0.008
10.16
0.400
0.45 ~0.75
0.018 ~ 0.030
( 0.50 )
0.020
#1
#22
18.81
MAX
0.741
0.075
0.125 +- 0.035
+ 0.003
18.41 ±0.10
0.725 ±0.004
0.005 - 0.001
1.00 ±0.10
0.039 ±0.004
( 0.805 )
0.032
0.30 +0.10
−0.05
0.012 +0.004
−0.002
0.05
0.002MIN
0.80
0.0315
-9-
1.20
MAX
0.047
0.10
0.004 MAX
Rev 4.0
September 2001
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