MITSUBISHI M37471M8

MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
Type name
M37470M2-XXXSP
M37471M2-XXXSP/FP
M37470M4-XXXSP
M37471M4-XXXSP/FP
M37470M8-XXXSP
M37471M8-XXXSP/FP
ROM size
RAM size
4096 bytes
128 bytes
8192 bytes
192 bytes
16384 bytes
384 bytes
I/O ports
26
36
26
36
26
36
FEATURES
●Basic machine-language instructions ...................................... 71
●Memory size
ROM ..................................................... 4096 bytes (M37471M2)
RAM ........................................................ 128 bytes (M37471M2)
●The minimum instruction execution time
....................................... 0.5 µs (at 8 MHz oscillation frequency)
●Power source voltage
.............. 2.7 to 4.5 V (at 2.2VCC–2.0 MHz oscillation frequency)
............................... 4.5 to 5.5 V (at 8 MHz oscillation frequency)
●Power dissipation in normal mode
................................... 35 mW (at 8.0 MHz oscillation frequency)
●Subroutine nesting ...... 64 levels max. (M37470M2, M37471M2)
●Interrupt ................................................... 12 sources, 10 vectors
●8-bit timers .................................................................................. 4
●Programmable I/O ports
(Ports P0, P1, P2, P4) ......................................... 22(7470 group)
28(7471 group)
●Input port (Port P3) ............................................... 4(7470 group)
(Ports P3, P5) ....................................... 8(7471 group)
●Serial I/O (8-bit) .......................................................................... 1
●A-D converter ............................... 8-bit, 4channels (7470 group)
8-bit, 8channels (7471 group)
PIN CONFIGURATION (TOP VIEW)
P17/SRDY
1
32
P07
P16/CLK
2
31
P06
P15/SOUT
3
30
P05
P14/SIN
4
29
P04
P13/ T1
5
28
P03
P12/ T0
6
27
P02
P11
7
26
P01
P10
8
25
P00
P23/IN3
9
24
P41
P22/IN2
10
23
P40
P21/IN1
11
22
P33 /CNTR1
P20/IN0
12
21
P32 /CNTR0
VREF
13
20
P31 /INT1
XIN
14
19
P30 /INT0
XOUT
15
18
RESET
VSS
16
17
VCC
M37470M2-XXXSP
M37470M4-XXXSP
M37470E4-XXXSP
M37470M8-XXXSP
M37470E8-XXXSP
The 7470/7471 group is a single-chip microcomputer designed
with CMOS silicon gate technology. It is housed in a 32-pin shrink
plastic molded DIP. The M37471M2-XXXSP/FP is a single-chip microcomputer designed with CMOS silicon gate technology. It is
housed in a 42-pin shrink plastic molded DIP or a 56-pin plastic
molded QFP.
These single-chip microcomputer are useful for business equipment and other consumer applications.
In addition to its simple instruction set, the ROM, RAM, and I/O
addresses are placed on the same memory map to enable easy
programming .
The differences between the M37471M2-XXXSP and the
M37471M2-XXXFP are the package outline and the power dissipation ability (absolute maximum ratings).
The differences among M37470M2-XXXSP, M37470M4-XXXSP,
M37470M8-XXXSP, M37471M2-XXXSP/FP, M37471M4-XXXSP/
FP and M37471M8-XXXSP/FP are noted below.
Outline 32P4B
APPLICATION
Audio-visual equipment, VCR, Tuner,
Office automation equipment
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P40
29
P22 /IN2
15
28
P33/CNTR1
P32/CNTR0
P21 /IN1
16
27
P31/INT1
P20 /IN0
17
26
P30/INT0
VREF
18
25
RESET
XIN
19
24
P51/XCOUT
XOUT
20
23
P50/XIN
VSS
21
22
VCC
Outline 42P4B
42S1B-A (Window)
49
50
51
52
53
29
24
23
22
21
20
54
19
55
18
56
17
RESET
NC
P51 /XCOUT
P50 /XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
NC
16
30
31
14
P41
30
P23 /IN3
31
25
M37471M2-XXXFP
M37471M4-XXXFP
M37471E4-XXXFP
M37471M8-XXXFP
M37471E8-XXXFP
14
13
P42
48
15
P24 /IN4
32
33
P25 /IN5
12
P43
32
11
33
26
47
12
P26 /IN6
P00
27
13
10
P01
34
35
P27 /IN7
35
34
9
28
46
10
8
P10
45
11
P11
NC
P05
P06
P07
P52
NC
VSS
P53
P17 /SRDY
P16/CLK
P15/SOUT
NC
37
P02
36
36
9
7
8
P03
P12/ T0
39
37
38
6
7
P04
P13/ T1
6
38
41
5
40
P05
P14 /SIN
5
39
42
4
4
P06
P15 /SOUT
3
40
43
3
44
P07
P16/CLK
1
P52
41
2
42
2
NC
P14/SIN
P13/ T1
P12/ T0
P11
P10
P27/IN7
P26/IN6
P25/IN5
P24/IN4
P23 /IN3
P22/IN2
P21/IN1
P20/IN0
VREF
NC
1
M37471M2-XXXSP
M37471M4-XXXSP
M37471E4-XXXSP
M37471M8-XXXSP
M37471E8-XXXSP
M37471E8SS
P53
P17 /SRDY
NC
P04
P03
P02
P01
P00
P43
P42
P41
P40
NC
P33 /CNTR1
P32 /CNTR0
P31/INT1
P30/INT0
NC
PIN CONFIGURATION (TOP VIEW)
Outline 56P6N-A
Note : The differences between 42P4B package type of 7471 group and 56P6N-A package type of 7471 group are package outline, power
dissipation ability (absolute maximum ratings), and the provision of an AV SS pin by the 56P6N-A package type.
NC : No connection
2
8-bit
Arithmetic
and logical
unit
I/O port P4
Input port P3
22 21 20 19
24 23
CNTR0
Index
register
Y(8)
Program
counter
PCL (8)
I/O port P2
S I/O(8)
1
2
4
5
6
I/O port P1
3
P1(8)
Timer 4 (8)
Timer 3 (8)
Timer 2 (8)
Timer 1 (8)
7
8
PWM control
I/O port P0
32 31 30 29 28 27 26 25
P0(8)
Control signal
Instruction decoder
Instruction register (8)
Notes 1 : 8192 bytes for M37470M4/E4-XXXSP, and 16384 bytes for M37470M8/E8-XXXSP
2 : 192 bytes for M37470M4/E4-XXXSP, and 384 bytes for M37470M8/E8-XXXSP
9 10 11 12
13
P2(4)
Stack
pointer
S(8)
4096
bytes
Data bus
Byte
counter (4)
(Note 1)
ROM
VREF
Reference
voltage input
4
A-D converter
INT0
INT1
Index
register
X(8)
P3(4)
CNTR1
Processor
status
register
PS (8)
128
bytes
RAM
Program
counter
PCH(8)
16
17
(Note 2)
VSS
VCC
P4(2)
Accumulator
A(8)
18
Clock generating
circuit
RESET
15
14
Reset
input
Clock
output
XOUT
Clock
input
XIN
M37470M2-XXXSP BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
4
20
P4(4)
33 32 31 30
I/O port P4
1 42 24 23
Input port P5
22
VCC
128
bytes
Input port P3
S I/O(8)
2
3
5
6
7
I/O port P1
4
P1(8)
Timer 4 (8)
Timer 3 (8)
Timer 2 (8)
Timer 1 (8)
8
9
PWM control
I/O port P0
41 40 39 38 37 36 35 34
P0(8)
Control signal
Instruction decoder
Instruction register (8)
Notes 1 : 8192 bytes for M37471M4/E4-XXXSP, and 16384 bytes for M37471M8/E8-XXXSP, M37471E8SS
2 : 192 bytes for M37471M4/E4-XXXSP, and 384 bytes for M37471M8/E8-XXXSP, M37471E8SS
I/O port P2
10 11 12 13 14 15 16 17
18
VREF
Reference
voltage input
29 28 27 26
Stack
pointer
S(8)
4096
bytes
Byte
counter (4)
(Note 1)
ROM
P2(8)
8
A-D converter
INT0
INT1
Index
register
Y(8)
Program
counter
PCL(8)
Data bus
P3(4)
CNTR0
Program
counter
PCH(8)
21
VSS
Index
register
X(8)
(Note 2)
RAM
Processor
status
register
PS (8)
CNTR1
25
RESET
Reset
input
P5(4)
XCIN
XCOUT
Accumulator
A(8)
XCOUT
Sub-clock
output
8-bit
Arithmetic
and logical
unit
XCIN
Sub-clock
input
Clock generating
circuit
19
Main clock Main clock
output
input
XOUT
XIN
M37471M2-XXXSP BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
19
23
VCC
128
bytes
33 32 31 30
Input port P3
38 37 36 35
I/O port P4
52 49 26 25
Input port P5
P3(4)
Index
register
Y(8)
15
VREF
Reference
voltage input
8
7
A-D converter
INT0
INT1
P4(4)
CNTR0
21
Program
counter
PCL(8)
AVSS
VSS
22 51
Program
counter
PCH(8)
Index
register
X(8)
(Note 2)
RAM
Processor
status
register
PS (8)
CNTR1
28
RESET
Reset
input
P5(4)
XCIN
XCOUT
Accumulator
A(8)
XCOUT
Sub-clock
output
8-bit
Arithmetic
and logical
unit
XCIN
Sub-clock
input
Clock generating
circuit
18
Main clock Main clock
output
input
XOUT
XIN
M37471M2-XXXFP BLOCK DIAGRAM
I/O port P2
9 10 11 12 13 14
S I/O(8)
3
4
I/O port P1
53 54 55 2
P1(8)
Timer 4 (8)
Timer 3 (8)
Timer 2 (8)
Timer 1 (8)
5
6
PWM control
I/O port P0
48 47 46 43 42 41 40 39
P0(8)
Control signal
Instruction decoder
Instruction register (8)
Notes 1 : 8192 bytes for M37471M4/E4-XXXFP, and 16384 bytes for M37471M8/E8-XXXFP
2 : 192 bytes for M37471M4/E4-XXXFP, and 384 bytes for M37471M8/E8-XXXFP
8
P2(8)
Stack
pointer
S(8)
4096
bytes
Byte
counter (4)
(Note 1)
ROM
Data bus
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
5
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONS OF 7470/7471 GROUP
Parameter
Functions
Basic machine-language instructions
71
Instruction execution time
0.5 µs (the minimum instructions, at 8 MHz oscillation frequency)
Clock input oscillation frequency
8 MHz (max.)
Memory size
Input/Output port
M37470M2
ROM
4096 bytes
M37471M2
RAM
128 bytes
M37470M4/E4
ROM
8192 bytes
M37471M4/E4
RAM
192 bytes
M37470M8/E8
ROM
16384 bytes
M37471M8/E8
RAM
384 bytes
P0, P1
I/O
8-bit ✕ 2
P2
I/O
8-bit ✕ 1 (4-bit ✕ 1 for 7470 group)
P3, P5
Input
4-bit ✕ 2 (Port P5 is not included in 7470 group)
P4
I/O
4-bit ✕ 1 (2-bit ✕ 1 for 7470 group)
Serial I/O
8-bit ✕ 1
Timers
8-bit timer ✕ 4
8-bit ✕ 1 (8 channels) (8-bit ✕ 1 (4 channels) for M37470M2/M4/M8)
A-D converter
64 level max. (M37470M2, M37471M2)
Subroutine nesting
96 level max. (M37470M4/E4, M37471M4/E4)
192 level max. (M37470M8/E8, M37471M8/E8)
Interrupt
5 external interrupts, 6 internal interrupts, 1 software interrupt
Clock generating circuit
Built-in circuit with internal feedback resistor (a ceramic or a quartzcrystal oscillator)
Power source voltage
2.7 to 4.5 V (at 2.2V CC–2.0 MHz oscillation frequency),
4.5 to 5.5 V (at 8 MHz oscillation frequency)
35 mW (at 8 MHz oscillation frequency)
Power dissipation
Input/Output characters
5V
Output current
–5 to 10 mA (P0, P1, P2, P4 : CMOS tri-states)
Operating temperature range
–20 to 85°C
Device structure
CMOS silicon gate
Package
6
Input/Output voltage
M37470M2/M4/M8/E4/E8-XXXSP
32-pin shrink plastic molded DIP
M37471M2/M4/M8/E4/E8-XXXSP
42-pin shrink plastic molded DIP
M37471M2/M4/M8/E4/E8-XXXFP
56-pin plastic molded QFP
M37471E8SS
42-pin ceramic DIP
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Input/
Output
Functions
VCC , VSS
Power source voltage
Apply voltage of 2.7 to 5.5 V to VCC, and 0 V to V SS.
AVSS
(Note 1)
Analog power
source
Ground level input pin for A-D converter.
Same voltage as VSS is applied.
RESET
Reset input
Input
To enter the reset state, the reset input pin must be kept at “L” for 2 µs or more
(under normal V CC conditions).
XIN
Clock input
Input
XOUT
Clock output
Output
These are I/O pins of internal clock generating circuit for main clock. To control
generating frequency, an external ceramic or a quartz-crystal oscillator is
connected between the XIN and XOUT pins. If an external clock is used, the
clock source should be connected the XIN pin and the XOUT pin should be left
open. Feedback resistor is connected between XIN and XOUT.
VREF
Reference voltage
input
Input
Reference voltage input pin for the A-D converter.
P00 –P07
I/O port P0
I/O
Port P0 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 1-bit and a key on wake up function is provided.
P10 –P17
I/O port P1
I/O
Port P1 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit. P12, P13 are in common with timer output pins T0 , T1 , P14, P15,
P16 , P17 are in common with serial I/O pins SIN, SOUT, CLK, S RDY, respectively. The output structure of SOUT and SRDY can be changed to N-channel
open drain output.
P20 –P27
(Note 2)
I/O port P2
I/O
Port P2 is an 8-bit I/O port. The output structure is CMOS output.
When this port is selected for input, pull-up transistor can be connected in
units of 4-bit.
This port is in common with analog input pins IN0–IN7 .
P30 –P33
Input port P3
Input
Port P3 is a 4-bit input port. P30, P31 are in common with external interrupt
input pins INT0, INT1 , and P32 , P33 are in common with timer input pins
CNTR0, CNTR1 .
P40 –P43
(Note 3)
I/O port P4
I/O
Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this
port is selected for input, pull-up transistor can be connected in units of 4-bit.
P50 –P53
(Note 4)
Input port P5
Input
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of
4-bit. P50 , P51 are in common with input/output pins of clock for clock function
XCIN , XCOUT. When P5 0, P51 are used as XCIN, XCOUT, connect a ceramic or a
quartz-crystal oscillator between XCIN and XCOUT.
If an external clock input is used, connect the clock input to the XCIN pin and
open the XCOUT pin. Feedback resistor is connected between XCIN and XCOUT
pins.
Notes 1
2
3
4
:
:
:
:
AVSS for M37471M2/M4/M8/E4/E8-XXXFP.
Only P20–P23 (IN0–IN 3) 4-bit for 7470 group.
Only P40 and P4 1 2-bit for 7470 group.
This port is not included in 7470 group.
7
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
CPU Mode Register
The 7470/7471 group uses the standard 740 family instruction set.
Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for
details on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The MUL, DIV, WIT, and STP instruction can be used.
b7
The CPU mode register is allocated at address 00FB16.
This register contains the stack page selection bit.
b0
CPU mode register (Address 00FB 16)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
P50, P51/XCIN , XCOUT selection bit (Note 2)
0 : P50 , P51
1 : XCIN , XCOUT
XCOUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN -XOUT ) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN -XOUT selected (normal mode)
1 : XCIN -XCOUT selected (low-speed mode)
Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”.
2 : In the 7470 group, set this bit to “0”.
Fig. 1 Structure of CPU mode register
8
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
• Special Function Register (SFR) Area
The special function register (SFR) area contains the registers
relating to functions such as I/O ports and timers.
• RAM
RAM is used for data storage as well as a stack area.
• ROM
ROM is used for storing user programs as well as the interrupt
vector area.
• Interrupt Vector Area
The interrupt vector area is for storing jump destination addresses used at reset or when an interrupt is generated.
• Zero Page
Zero page addressing mode is useful because it enables access
to this area with fewer instruction cycles.
• Special Page
Special page addressing mode is useful because it enables access to this area with fewer instruction cycles.
000016
RAM (192 bytes)
for
M37470M4/E4
M37470M8/E8
M37471M4/E4
M37471M8/E8
RAM (128 bytes)
for
M37470M2
M37471M2
007F 16
Not used
Zero page
00BF16
SFR area
RAM (192 bytes)
for
M37470M8/E8
M37471M8/E8
00FF16
010016
01BF16
Not used
C00016
E00016
F000 16
ROM
(16K bytes)
for
M37470M8/E8
M37471M8/E8
ROM
(8K bytes)
for
M37470M4/E8
M37471M4/E8
FF0016
ROM
(4K bytes)
for
M37470M2
M37471M2
FFEA 16
Special page
Interrupt vector area
FFFF16
Fig. 2 Memory map
9
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
00C016
Port P0
00E016
00C116
Port P0 direction register
00E116
00C216
Port P1
00E216
00C316
Port P1 direction register
00E316
00C416
Port P2
00E416
00C516
Port P2 direction register
00E516
00C616
Port P3
00E616
00E716
00C716
00C816
Port P4
00E816
00C916
Port P4 direction register
00E916
00CA16
Port P5 (Note 1)
00EA16
00CB16
00EB16
00CC16
00EC16
00CD16
00ED16
00CE16
00EE16
00EF16
00CF16
00D016
P0 pull-up control register
00F016
Timer 1
00D116
P1–P5 pull-up control register (Note 2)
00F116
Timer 2
00D216
00F216
Timer 3
00D316
00F316
Timer 4
00D416
Edge polarity selection register
00D516
00D616
00F416
00F516
Input latch register
00F616
00D716
00F716
Timer FF register
00D816
00F816
Timer 12 mode register
00D916
A-D control register
00F916
Timer 34 mode register
00DA16
A-D conversion register
00FA16
Timer mode register 2
00DB16
00FB16
CPU mode register
00DC16 Serial I/O mode register
00FC16
Interrupt request register 1
00DD16 Serial I/O register
00FD16
Interrupt request register 2
00FE16
Interrupt control register 1
00FF16
Interrupt control register 2
00DE16
Serial I/O counter
Byte counter
00DF16
Notes 1 : This address is not used in the 7470 group.
2 : This address is allocated P1–P4 pull-up control register for the 7470 group.
Fig. 3 SFR (Special Function Register) memory map
10
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts can be caused by 12 different sources consisting of five
external, six internal, and one software sources.
Interrupts are vectored interrupts with priorities shown in Table 1.
Reset is also included in the table because its operation is similar
to an interrupt.
When an interrupt is accepted, the registers are pushed, interrupt
disable flag I is set, and the program jumps to the address specified in the vector table. The interrupt request bit is cleared
automatically. The reset and BRK instruction interrupt can never
be disabled. Other interrupts are disabled when the interrupt disable flag is set.
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits
are in interrupt request registers 1 and 2 and the interrupt enable
bits are in interrupt control registers 1 and 2. External interrupts
INT0 and INT1 can be asserted on either the falling or rising edge
as set in the edge polarity selection register. When “0” is set to this
register, the interrupt is activated on the falling edge; when “1” is
set to the register, the interrupt is activated on the rising edge.
When the device is put into power-down state by the STP instruction or the WIT instruction, if bit 5 in the edge polarity selection
register is “1”, the INT1 interrupt becomes a key on wake up interrupt. When a key on wake up interrupt is valid, an interrupt request
is generated by applying the “L” level to any pin in port P0. In this
case, the port used for interrupt must have been set for the input
mode.
If bit 5 in the edge polarity selection register is “0” when the device
is in power-down state, the INT1 interrupt is selected. Also, if bit 5
in the edge polarity selection register is set to “1” when the device
is not in a power-down state, neither key on wake up interrupt request nor INT1 interrupt request is generated.
The CNTR0/CNTR 1 interrupts function in the same as INT 0 and
INT1 . The interrupt input pin can be specified for either CNTR0 or
CNTR1 pin by setting bit 4 in the edge polarity selection register.
Figure 4 shows the structure of the edge polarity selection register, interrupt request registers 1 and 2, and interrupt control
registers 1 and 2.
Interrupts other than the BRK instruction interrupt and reset are
accepted when the interrupt enable bit is “1”, interrupt request bit
is “1”, and the interrupt disable flag is “0”. The interrupt request bit
can be reset with a program, but not set. The interrupt enable bit
can be set and reset with a program.
Reset is treated as a non-maskable interrupt with the highest priority. Figure 5 shows interrupts control.
Table 1. Interrupt vector address and priority
Priority
Vector addresses
RESET
Interrupt source
1
FFFF16 , FFFE 16
Non-maskable
Remarks
INT 0 interrupt
2
FFFD16 , FFFC 16
External interrupt (polarity programmable)
INT 1 interrupt or key on wake up interrupt
3
FFFB16 , FFFA16
External interrupt (INT1 is polarity programmable)
CNTR 0 interrupt or CNTR1 interrupt
4
FFF916, FFF816
External interrupt (polarity programmable)
Timer 1 interrupt
5
FFF716, FFF616
Timer 2 interrupt
6
FFF516, FFF416
Timer 3 interrupt
7
FFF316, FFF216
Timer 4 interrupt
8
FFF116, FFF016
Serial I/O interrupt
9
FFEF16 , FFEE 16
A-D conversion completion interrupt
10
FFED16 , FFEC16
BRK instruction interrupt
11
FFEB16 , FFEA 16
Non-maskable software interrupt
11
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Edge polarity selection register (EG)
(Address 00D4 16)
INT0 edge selection bit
INT1 edge selection bit
CNTR0 edge selection bit
CNTR1 edge selection bit
0 : Falling edge
1 : Rising edge
CNTR0/CNTR1 interrupt selection bit
0 : CNTR0
1 : CNTR1
INT1 source selection bit (at power-down state)
0 : P31/INT1
1 : P00–P07 “L” level (for key-on wake-up)
Nothing is allocated (The value is undefined at reading)
b7
b0
b7
b0
Interrupt request register 1
(Address 00FC 16)
Interrupt request register 2
(Address 00FD 16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
Nothing is allocated
(The value is undefined at reading)
INT0 interrupt request bit
INT1 interrupt request bit
CNTR0 or CNTR1 interrupt request bit
0 : No interrupt request
1 : Interrupt requested
Nothing is allocated
(The value is undefined at reading)
Serial I/O transmit interrupt request bit
A-D conversion completion interrupt request bit
b7
b0
b7
Interrupt control register 1
(Address 00FE 16)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
Nothing is allocated
(The value is undefined at reading)
b0
Interrupt control register 2
(Address 00FF 16)
INT0 interrupt enable bit
INT1 interrupt enable bit
CNTR0 or CNTR1 interrupt enable bit
0 : Interrupt disable
1 : Interrupt enabled
Nothing is allocated
(The value is undefined at reading)
Serial I/O receive interrupt enable bit
A-D conversion completion interrupt enable bit
Fig. 4 Structure of registers related to interrupt
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Fig. 5 Interrupt control
12
Interrupt request
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMER
The 7470/7471 group has four timers; timer 1, timer 2, timer 3, and
timer 4.
A block diagram of timer 1 through 4 is shown in Figure 6.
Timer 1 can be operated in the timer mode, event count mode, or
pulse output mode. Timer 1 starts counting when bit 0 in the timer
12 mode register (address 00F816 ) is set to “0”.
The count source can be selected from the f(X IN) divided by 16,
f(XCIN ) divided by 16, f(XCIN ), or event input from P32/CNTR0 pin.
Do not select f(XCIN ) as the count source in the 7470 group. When
bit 1 and bit 2 in the timer 12 mode register are “0”, f(X IN) divided
by 16 or f(XCIN ) divided by 16 is selected. Selection between f(XIN)
and f(XCIN) is done by bit 7 in the CPU mode register (address
00FB16 ). When bit 1 in the timer 12 mode register is “0” and bit 2
is “1”, f(X CIN) is selected. And, when bit 1 in the timer 12 mode
register is “1”, an event input from the CNTR 0 pin is selected.
Event inputs are selected depending on bit 2 in the edge polarity
selection register (address 00D4 16). When this bit is “0”, the inverted value of CNTR 0 input is selected; when the bit is “1”,
CNTR0 input is selected.
When bit 3 in the timer 12 mode register is set to “1”, the P12 pin
becomes timer output T0 . When the direction register of P12 is set
for the output mode at this time, the timer 1 overflow divided by 2
is output from T0.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 0 of the timer 12 mode register.
(Timer 1 count stop.)
➁ Set “1” to bit 0 of the timer mode register 2.
➂ Set the output value to bit 0 of the timer FF register.
➃ Set the count value to the timer 1.
➄ Set “0” to bit 0 of the timer 12 mode register.
(Timer 1 count start.)
Timer 2 can only be operated in the timer mode. Timer 2 starts
counting when bit 4 in the timer 12 mode register is set to “0”.
The count source can be selected from the divide by 16, divide by
64, divide by 128, or divide by 256 frequency of f(XIN ) or f(XCIN ),
and timer 1 overflow. Do not select f(XCIN ) as the count source in
the 7470 group. When bit 5 in the timer 12 mode register is “0”,
any of the divide by 16, divide by 64, divide by 128, or divide by
256 frequency of f(XIN) or (XCIN ) is selected. The divide ratio is selected according to bit 6 and bit 7 in the timer 12 mode register,
and selection between f(X IN) and f(XCIN) is made according to bit
7 in the CPU mode register. When bit 5 in the timer 12 mode register is “1”, timer 1 overflow is selected as the count source.
Timer 3 can be operated in the timer mode, event count mode, or
PWM mode. Timer 3 starts counting when bit 0 in the timer 34
mode register (address 00F9 16) is set to “0”.
The count source can be selected from the f(XIN ) divided by 16,
f(XCIN) divided by 16, f(X CIN), timer 1 or timer 2 overflow, or an
event input from P33/CNTR1 pin according to the statuses of bit 1
and bit 2 in the timer 34 mode register, bit 6 in the timer mode register 2 (address 00FA16 ) and bit 7 in the CPU mode register. Do
not select f(XCIN) as the count source in the 7470 group. Note,
however, that if timer 1 overflow or timer 2 overflow is selected for
the count source of timer 3 when timer 1 overflow is selected for
the count source of timer 2, timer 1 overflow is always selected regardless of the status of bit 6 in the timer mode register 2. Event
inputs are selected depending on bit 3 in the edge polarity selection register. When this bit is “0”, the inverted value of CNTR1 input
is selected; when the bit is “1”, CNTR1 input is selected.
Timer 4 can be operated in the timer mode, event count mode,
pulse output mode, pulse width measuring mode, or PWM mode.
Timer 4 starts counting when bit 3 in the timer 34 mode register is
set to “0” when bit 6 in this register is “0”. When bit 6 is “1”, the
pulse width measuring mode is selected. The count source can be
selected from timer 3 overflow, f(XIN) divided by 16, f(XCIN ) divided
by 16, f(XCIN), timer 1 or timer 2 overflow, or an event input from
P33/CNTR 1 pin according to the statuses of bit 4 and bit 5 in the
timer 34 mode register, bit 6 in the timer mode register 2, and bit 7
in the CPU mode register. Do not select f(XCIN ) as the count
source in the 7470 group. Note, however, that if timer 1 overflow or
timer 2 overflow is selected for the count source of timer 4 when
timer 1 overflow is selected for the count source of timer 2, timer 1
overflow is always selected regardless of the status of bit 6 in the
timer mode register 2. Event inputs are selected depending on bit
3 in the edge polarity selection register.
When this bit is “0”, the inverted value of CNTR1 input is selected;
when the bit is “1”, CNTR1 input is selected.
When bit 7 in the timer 34 mode register is set to “1”, the P13 pin
becomes timer output T1. When the direction register of P1 3 is set
for the output mode at this time, the timer 4 overflow divided by 2
is output from T1 when bit 7 in the timer mode register 2 is “0”.
Please set the initial output value in the following procedure.
➀ Set “1” to bit 3 of the timer 34 mode register.
(Timer 4 count stop.)
➁ Set “1” to bit 1 of the timer mode register 2.
➂ Set the output value to bit 1 of the timer FF register.
➃ Set the count value to the timer 4.
➄ Set “0” to bit 3 of the timer 34 mode register.
(Timer 4 count start.)
(1) Timer mode
Timer performs down count operations with the dividing ratio being
1/(n+1). Writing a value to the timer latch sets a value to the timer.
When the value to be set to the timer latch is nn16 , the value to be
set to a timer is nn16 , which is down counted at the falling edge of
the count source from nn 16 to (nn16-1) to (nn 16-2) to ...01 16 to
0016 to FF16 . At the falling edge of the count source immediately
after timer value has reached FF16, value (nn16-1) obtained by
subtracting one from the timer latch value is set (reloaded) to the
timer to continue counting. At the rising edge of the count source
immediately after the timer value has reached FF16 , an overflow
occurs and an interrupt request is generated.
13
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Event count mode
Timer operates in the same way as in the timer mode except that
it counts input from the CNTR0 or CNTR1 pin.
(3) Pulse output mode
In this mode, duty 50% pulses are output from the T0 or T1 pin.
When the timer overflows, the polarity of the T0 or T 1 pin output
level is inverted.
(4) Pulse width measuring mode
The 7470/7471 group can measure the “H” or “L” width of the
CNTR 0 or CNTR 1 input waveform by using the pulse width measuring mode of timer 4. The pulse width measuring mode is
selected by writing “1” to bit 6 in the timer 34 mode register. In the
pulse width measuring mode, the timer counts the count source
while the CNTR0 or CNTR1 input is “H” or “L”. Whether the CNTR0
input or CNTR1 input to be measured can be specified by the status of bit 4 in the edge polarity selection register; whether the “H”
width or “L” width to be measured can be specified by the status of
bit 2 (CNTR 0) and bit 3 (CNTR1) in the edge polarity selection register.
(5) PWM mode
The PWM mode can be entered for timer 3 and timer 4 by setting
bit 7 in the timer mode register 2 to “1”. In the PWM mode, the P13
pin is set for timer output T1 to output PWM waveforms by setting
bit 7 in the timer 34 mode register to “1”. The direction register of
P13 must be set for the output mode before this can be done.
In the PWM mode, timer 3 is counting and timer 4 is idle while the
PWM waveform is “L”. When timer 3 overflows, the PWM waveform
goes “H”. At this time, timer 3 stops counting simultaneously and
timer 4 starts counting. When timer 4 overflows, the PWM waveform goes “L”, and timer 4 stops and timer 3 starts counting again.
Consequently, the “L” duration of the PWM waveform is determined by the value of timer 3; the “H” duration of the PWM
waveform is determined by the value of timer 4.
When a value is written to the timer in operation during the PWM
mode, the value is only written to the timer latch, and not written to
the timer. In this case, if the timer overflows, a value one less the
value in the timer latch is written to the timer. When any value is
written to an idle timer, the value is written to both the timer latch
and the timer.
In this mode, do not select timer 3 overflow as the count source for
timer 4.
14
INPUT LATCH FUNCTION
The 7470/7471 group can latch the P30 /INT0 , P31 /INT 1 , P32 /
CNTR0, and P3 3/CNTR1 pin level into the input latch register (address 00D616) when timer 4 overflows. The polarity of each pin
latched to the input latch register can be selected by using the
edge polarity selection register. When bit 0 in the edge polarity selection register is “0”, the inverted value of the P30/INT 0 pin level is
latched; when the bit is “1”, the P30/INT0 pin level is latched as it
is. When bit 1 in the edge polarity selection register is “0”, the inverted value of the P31 /INT 1 pin level is latched; when the bit is
“1”, the P31/INT 1 pin level is latched as it is. When bit 2 in the edge
polarity selection register is “0”, the inverted value of the P32 /
CNTR0 pin level is latched; when the bit is “1”, the P3 2/CNTR0 pin
level is latched as it is. When bit 3 in the edge polarity selection
register is “0”, the inverted value of the P33 /CNTR1 pin level is
latched; when the bit is “1”, the P33/CNTR1 pin level is latched as
it is.
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
(Note 1)
Data bus
1/2
1/2
XIN
1/8
CM7
Timer 1 latch (8)
T12M 2
T12M 0
P32/CNTR0
Timer 1 (8)
EG 2
Port latch
T12M 1
Timer 1
interrupt request
TM20
1/2
P12/T0
T12M3
Timer 2 latch (8)
T12M6
T12M7
T12M4
Timer 2 (8)
T12M 5
1/4
Timer 2
interrupt request
TM2 6
T34M 1
T34M 2
1/8
1/16
Timer 3 latch (8)
T34M 0
P33/CNTR1
Timer 3 (8)
EG3
Timer 3
interrupt request
T34M 4
T34M 5
Timer 4 latch (8)
Timer 4 (8)
Port latch
T34M 6
EG 4
T34M3
F/F
P13 /T1
1/2
T34M7
P33 /CNTR1
P32 /CNTR0
P31 /INT1
P30 /INT0
(
Timer 4
interrupt request
EG3
TM27
EG2
EG1
TM2 1
C
D3 Q3
D2 Q2
D1 Q1
D0 Q0
EG0
Select gate : At reset, shaded side is connected.)
Note 1 : The 7470 group does not have XCIN input.
Fig. 6 Block diagram of timer 1 through 4
15
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b7
b0
b7
Timer 34 mode register (T34M)
(Address 00F9 16)
Timer 1 overflow FF set enable bit
0 : Set disable
1 : Set enable
Timer 4 overflow FF set enable bit
0 : Set disable
1 : Set enable
Nothing is allocated
(The value is undefined at reading)
Timer 3, timer 4 count overflow signal
selection bit
0 : Timer 1 overflow
1 : Timer 2 overflow
Timer 3, timer 4 function selection bit
0 : Normal mode
1 : PWM mode
Timer 3 count stop bit
0 : Count start
1 : Count stop
Timer 3 count source selection bits (Note 3)
00 : f(XIN ) divided by 16 or
f(X CIN ) divided by 16
01 : f(XCIN )
10 : Timer 1 overflow or timer 2 overflow
11 : P33 /CNTR1 external clock
Timer 4 count stop bit
0 : Count start
1 : Count stop
Timer 4 count source selection bits (Note 3)
00 : Timer 3 overflow
01 : f(XIN ) divided by 16 or
f(X CIN ) divided by 16
10 : Timer 1 overflow or timer 2 overflow
11 : P33 /CNTR1 external clock
Timer 4 pulse width measuring mode
selection bit
0 : Timer mode
1 : Pulse width measuring mode
P13/T1 port output selection bit
0 : P13 port output
1 : Timer 4 overflow divided by 2
or PWM output
b0
Timer 12 mode register (T12M)
(Address 00F8 16)
Timer 1 count stop bit
0 : Count start
1 : Count stop
Timer 1 count source selection bit
0 : Internal clock (Note 1)
1 : P32/CNTR0 external clock
Timer 1 internal clock source
selection bit (Note 2)
0 : f(XIN) divided by 16 or
f(XCIN ) divided by 16
1 : f(XCIN )
P12 /T0 port output selection bit
0 : P12 port output
1 : Timer 1 overflow divided by 2
Timer 2 count stop bit
0 : Count start
1 : Count stop
Timer 2 count source selection bit
0 : Internal clock
1 : Timer 1 overflow
Timer 2 internal clock source
selection bits (Note 3)
00 : f(XIN) divided by 16 or
f(XCIN ) divided by 16
01 : f(XIN) divided by 64 or
f(XCIN ) divided by 64
10 : f(XIN) divided by 128 or
f(XCIN ) divided by 128
11 : f(XIN) divided by 256 or
f(XCIN ) divided by 256
Notes 1 : f(X IN ) divided by 16 in the 7470 group.
2 : The 7470 group does not use this bit (bit 2). Set this bit to “0”.
3 : Do not select f(X CIN ) as the count source in the 7470 group.
Fig. 7 Structure of timer mode registers
16
b0
Timer mode register 2 (TM2)
(Address 00FA 16)
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The block diagram of serial I/O is shown in Figure 8. In the serial
I/O mode, the receive ready signal (SRDY ), synchronous input/output clock (CLK), and the serial I/O (SOUT, SIN ) pins are used as
P17, P16, P15 , and P14 , respectively.
The serial I/O mode register (address 00DC 16) is an 8-bit register.
Bit 2 of this register is used to select a synchronous clock source.
When this bit is “0”, an external clock from P16 is selected. When
this bit is “1”, an internal clock is selected.
The internal clock can be selected from among the divide by 8, divide by 16, divide by 32, divide by 512 frequency of the oscillator
frequency f(X IN ) or f(XCIN ). Do not select f(XCIN ) as the count
source in the 7470 group. The divide ratio is selected according to
bit 0 and bit 1 in the serial I/O mode register, and selection be-
tween f(XIN ) and f(XCIN ) is mode according to bit 7 in the CPU
mode register.
Bits 3 and 4 decide whether parts of P1 will be used as a serial
I/O or not. When bit 3 is “1”, P16 becomes an I/O pin of the synchronous clock. When an internal synchronous clock is selected,
the clock is output from P1 6. If the external synchronous clock is
selected, the clock is input to P16 .
And P15 will be a serial output. To use P14 as a serial input, set
the direction register bit which corresponds to P14, to “0”. For
more information on the direction register, refer to the I/O pin section.
(Note 1)
XCIN
1/2
XIN
1/2
Counter
1/4
CM7
1/2
SARDY
1/4
1/64
SM1
SM0
SM2
SRDY
Sync. circuit
SM5
CLK input
CLK output
Serial I/O
interrupt request
Serial I/O counter (3)
SM6
SC
Byte counter (4)
Data bus
SIN
Serial I/O register (8)
SOUT
S
Q
R
(
Select gate : At reset, shaded side is connected.)
Note 1 : The 7470 group does not have X CIN input.
Fig. 8 Block diagram of serial I/O
17
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal Clock – The serial I/O counter is set to 7 when data is
stored in the serial I/O register. At each falling edge of the transfer
clock, serial data is output to P15 . During the rising edge of this
clock, data can be input from P1 4 and the data in the serial I/O
register will be shifted 1 bit. Data is output starting with the LSB.
After the transfer clock has counted 8 times, the serial I/O register
will be empty and the transfer clock will remain at a high level. At
this time the interrupt request bit will be set.
External Clock – If an external clock is used, the interrupt request
bit will be set after the transfer clock has counted 8 times but the
transfer clock will not stop. Due to this reason, the external clock
must be controlled from the outside.
Timing diagrams are shown in Figure 9.
Bit 4 determines if P1 7 is used as an output pin for the receive
ready signal (bit 4=“1”, S RDY) or used as a normal I/O pin (bit
4=“0”).
When the P17 pin is used as the SRDY output pin, output signal
can be selected between SRDY signal and SARDY signal by using
bit 5 in the serial I/O mode register. The SRDY signal is driven “L”
by a signal written into the serial I/O register to inform that the device is ready to receive. Then, the SRDY signal is driven “H” on the
first falling edge of the transfer clock.
The SA RDY signal is driven “H” by a signal written into the serial
I/O register, and driven “L” on the last rising edge of the transfer
clock.
The function of serial I/O differs depending on the clock source;
external clock or internal clock.
Synchronous clock
Transfer clock
Serial I/O register write
signal
Serial I/O output
SOUT
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O input
SIN
Receive ready signal
SRDY
Interrupt request bit set
Fig. 9 Serial I/O timing
18
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O mode register (SM)
(Address 00DC 16)
Internal clock selection bits
00 : f(XIN ) or f(XcIN ) divided by 8
01 : f(XIN ) or f(XcIN ) divided by 16
10 : f(XIN ) or f(XcIN ) divided by 32
11 : f(XIN ) or f(XcIN ) divided by 512
Synchronous clock selection bit
0 : External clock
1 : Internal clock
Serial I/O port selection bit
0 : Normal I/O port
1 : S OUT , CLK pins
SRDY signal output selection bit
0 : Normal I/O port
1 : S RDY signal output pin
SRDY signal selection bit
0 : S RDY signal
1 : SARDY signal
Serial I/O byte specify mode selection bit
0 : Normal mode
1 : Byte specify mode
P15/SOUT, P17 /SRDY output structure selection bit
0 : CMOS output
1 : N-channel open drain output
Note : Do not select f(X CIN) as the count source in the 7470 group.
Fig. 10 Structure of serial I/O mode register
BYTE SPECIFY MODE
The serial I/O has a byte specify mode that allows one specific
byte data to be selected for transmission or reception when serial
I/O circuits of two or more microcomputers are connected to send
or receive data through one bus. The data to be sent or received
can be specified by writing a value into the byte counter. The value
written in the byte counter is decremented by one each time eight
cycles of transfer clock are input. When the value in the byte
counter becomes “0”, serial transmission/reception is done by the
next eight cycles of transfer clock. When the value in the byte
counter is not “0”, the output on the SOUT pin is driven “H” by the
falling edge of the first transfer clock pulse to inhibit transmission/
reception.
Serial I/O interrupt requests are generated only when serial transmission/reception is done after the value in the byte counter is
decremented to “0”. When the SA RDY signal output is selected, the
SARDY signal is driven “L” by the last rising edge of the transfer
clock after the value in the byte counter is decremented to “0”.
Note that in the byte mode, an external clock must be used as the
sync. clock for the purpose of the mode.
19
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The A-D conversion register (address 00DA 16 ) contains information on the results of conversion, so that it is possible to know the
results of conversion by reading the contents of this register.
The following explains the procedure to execute A-D conversion.
First, set values to bit 2 to bit 0 in the A-D control register to select
the pins that you want to execute A-D conversion. Next, clear the
A-D conversion end bit to “0”.
When the above is done, A-D conversion is initiated. The A-D conversion is completed after an elapse of 50 machine cycles
(12.5 µs when f(XIN)= 8 MHz), the A-D conversion end bit is set to
“1”, and the interrupt request bit is set to “1”. The results of conversion are contained in the A-D conversion register.
The A-D conversion uses an 8-bit successive comparison method.
Figure 11 shows a block diagram of the A-D conversion circuit.
Conversion is automatically carried out once started by the program.
There are eight analog input pins which are shared with P20 to
P27 of port P2 (Only P20 to P23 4-bit for 7470 group. Which analog inputs are to be A-D converted is specified by using bit 2 to bit
0 in the A-D control register (address 00D9 16 ). Pins for inputs to
be A-D converted must be set for input by setting the direction register bit to “0”. Bit 3 in the A-D control register is an A-D conversion
end bit. This is “0” during A-D conversion; it is set to “1” when the
conversion is terminated. Therefore, it is possible to know whether
A-D conversion is terminated by checking this bit. Bit 4 in the A-D
control register is a V REF connection selection bit.
During A-D conversion, this bit must be set “1” for the ladder resistor and V REF pin to be connected; after the A-D conversion is
terminated, this bit can be reset to “0” to separate the ladder resistor from the VREF pin. In this way, power consumption in the ladder
resistor can be suppressed while no A-D conversion is performed.
Figure 13 shows the relationship between the contents of A-D
control register and the selected input pins.
Data bus
bit 0
bit 4
A-D control register
(Address 00D9 16)
P20/IN0
A-D control circuit
P21/IN1
Channel selector
P22/IN2
P23/IN3
P24/IN4
P25/IN5
Comparator
A-D conversion register
(Address 00DA 16)
Switch tree
Ladder resistor
P26/IN6
P27/IN7
VSS (Note 1)
Notes 1 : AVSS for M37471M2/M4/M8/E4/E8-XXXFP
2 : 7470 group does not have P2 4/IN4 to P27 /IN7 pins.
Fig. 11 A-D converter circuit
20
VREF
A-D conversion completion
interrupt request
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
A-D control register
(Address 00D9 16)
Analog input selection bits
000 : IN 0
001 : IN 1
010 : IN 2
011 : IN 3
100 : IN 4
101 : IN 5
(Note)
110 : IN 6
111 : IN 7
A-D conversion end bit
0 : Under conversion
1 : End conversion
VREF connection selection bit
0 : VREF is separated
1 : VREF is connected
Nothing is allocated
(The value is undefined at reading)
This bit must be set to “0”.
Note : Do not select IN4 to IN7 in the 7470 group.
Fig. 12 Structure of A-D control register
21
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
KEY ON WAKE UP
“Key on wake up” is one way of returning from a power down state
caused by the STP or WIT instruction. If any terminal of port P0
has “L” level applied, after bit 5 of the edge polarity selection register (EG 5 ) is set to “1”, an interrupt is generated and the
microcomputer is returned to the normal operating state. A key
matrix can be connected to port P0 and the microcomputer can be
returned to a normal state by pushing any key.
The key on wake up interrupt is common with the INT1 interrupt.
When EG5 is set to “1”, the key on wake up function is selected.
However, key on wake up cannot be used in the normal operating
state. When the microcomputer is in the normal operating state,
both key on wake up and INT1 are invalid.
P33 /CNTR1
Port P33 data read circuit
EG3
EG2
P32/CNTR0
CNTR interrupt request signal
EG 4
Port P32 data read circuit
XCIN
(P50 )
1/2
XIN
1/2
P30/INT 0
CM 7
Port P3 0 data read circuit
P31/INT 1
EG0
Noise
eliminating
circuit
INT0 interrupt request signal
Port P3 1 data read circuit
EG1
Noise
eliminating
circuit
EG5
INT1 interrupt request signal
CPU halt state signal
P07
P01
Pull-up control
register
Direction register
Pull-up control
register
Direction register
Port P0 data read circuit
P00
(
Pull-up control
register
Direction register
Select gate: At reset, shaded side is connected.)
Note : The 7470 group does not have X CIN input.
Fig. 13 Block diagram of interrupt input and key on wake up circuit
22
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
The 7470/7471 group are reset according to the sequence shown
in Figure 15. It starts the program from the address formed by using the content of address FFFF16 as the high order address and
the content of the address FFFE16 as the low order address, when
the RESET pin is held at “L” level for no less than 2 µs while the
power voltage is in the recommended operating condition and
then returned to “H” level.
The internal initializations following reset are shown in Figure 16.
Example of reset circuit is Figure 14. Immediately after reset, timer
3 and timer 4 are connected, and counts the f(X IN) divided by 16.
At this time, FF16 is set to timer 3, and 0716 is set to timer 4. The
reset is cleared when timer 4 overflows.
Address
(1) Port P0 direction register
(C116) …
0016
(2) Port P1 direction register
(C316) …
0016
(3) Port P2 direction register
(C516) …
0016
(4) Port P4 direction register
(C916) …
(5) P0 pull-up control register
(D016) …
(6) P1–P5 pull-up control register (Note 1)(D116) …
(7) Edge selection register
0 1 0 0 0
(SM) (DC16) …
0016
(10) Timer 12 mode register (T12M) (F816) …
0016
(11) Timer 34 mode register (T34M) (F916) …
0016
(TM2) (FA16) … 0 0
(13) CPU mode register
VCC
0 0 0 0 0
0 0 0 0 0 0
(D916) … 0
(9) Serial I/O mode register
(12) Timer mode register 2
RESET
0
(EG) (D416) …
(8) A-D control register
7470/7471 group
0 0 0 0
0016
0 0
(CM) (FB16) … 0 0 0 0
(14) Interrupt request register 1
(FC16) … 0 0
(15) Interrupt request register 2
(FD16) …
(16) Interrupt control register 1
(FE16) … 0 0
(17) Interrupt control register 2
(FF16) …
(18) Program counter
(19) Processor status register
0 0 0
0 0 0 0
0 0 0
0 0 0 0
0 0 0
(PCH) …
Contents of address
FFFF16
(PC L) …
Contents of address
FFFE16
(PS) …
1
Notes 1 : This address is allocated P1–P4 pull-up control register for
7470 group. Bit 6 is not used.
2 : Since the contents of both registers other than those listed
above (including timers and the serial I/O register) are
undefined at reset, it is necessary to set initial values.
Fig. 14 Example of reset circuit
Fig. 16 Internal state of microcomputer at reset
XIN
φ
RESET
Internal
RESET
SYNC
Address
?
?
?
Data
32768 counts of f(X IN )
00, S
?
00, S-1
PC H
00, S-2
PC L
PS
FFFE
FFFF
AD L
AD H,AD L
AD H
Reset address
from the vector table
Notes 1 : Frequency relation of X IN and φ is f(XIN )=2·φ.
2 : The mark “?” means that the address is changeable
depending upon the previous state.
Fig. 15 Timing diagram at reset
23
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
(1) Port P0
Port P0 is an 8-bit I/O port with CMOS outputs. As shown in
Figure 2, P0 can be accessed as memory through zero page
address 00C016. Port P0’s direction register allows each bit to
be programmed individually as input or output. The direction
register (zero page address 00C116 ) can be programmed as
input with “0”, or as output with “1”. When in the output mode,
the data to be output is latched to the port latch and output.
When data is read from the output port, the output pin level is
not read, only the latched data of the port latch is read. Therefore, a previously output value can be read correctly even
though the output voltage level has been shifted up or down.
Port pins set as input are in the high impedance state so the
signal level can be read. When data is written into the input
port, the data is latched only to the output latch and the pin
still remains in the high impedance state. Following the execution of STP or WIT instruction, key matrix with port P0 can
be used to generate the interrupt to bring the microcomputer
back in its normal state. When this port is selected for input,
pull-up transistor can be connected in units of 1-bit.
(2) Port P1
Port P1 has the same function as port P0. P1 2 –P1 7 serve
dual functions, and the desired function can be selected by
the program. When this port is selected for input, pull-up transistor can be connected in units of 4-bit.
(3) Port P2
Port P2 has the same function as port P0. In the 7470 group,
this port is P2 0–P2 3, a 4-bit I/O port. This port can also be
used as the analog voltage input pins. When this port is selected for input, pull-up transistor can be connected in units of
4-bit.
24
(4) Port P3
Port P3 is a 4-bit input port.
(5) Port P4
Port P4 is a 4-bit I/O port and has basically the same functions as port P0. In the 7470 group, this port is P40 and P41 ,
a 2-bit I/O port. When this port is selected for input, pull-up
transistor can be connected in units of 4-bit .
(6) Port P5
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4-bit. P5 0 and P5 1 are shared with clock
generating circuit input/output pins.
The 7470 group does not have this port.
(7) INT0 pin (P3 0/INT0 pin)
This is an interrupt input pin, and is shared with port P30 .
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT0 interrupt request bit (bit 0 of address 00FD 16) is
set to “1”.
(8) INT1 pin (P3 1/INT1 pin)
This is an interrupt input pin, and is shared with port P31 .
When “H” to “L” or “L” to “H” transition input is applied to this
pin, the INT1 interrupt request bit (bit 1 of address 00FD 16) is
set to “1”.
(9) Counter input CNTR0 pin (P32 /CNTR0 pin)
This is a timer input pin, and is shared with port P32 .
When this pin is selected to CNTR0 or CNTR 1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16) is set to “1”.
(10) Counter input CNTR1 pin (P33 /CNTR1 pin)
This is a timer input pin, and is shared with port P33 .
When this pin is selected to CNTR0 or CNTR 1 interrupt input
pin and “H” to “L” or “L” to “H” transition input is applied to this
pin, the CNTR0 or CNTR 1 interrupt request bit (bit 2 of address 00FD16) is set to “1”.
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0
Pull-up control
register
Tr1
Direction register
Data bus
Port latch
Port P0
Interrupt control circuit
Ports P10–P13
Data bus
Pull-up control
register
Tr2
T34M 7
Direction register
Data bus
Port latch
Port P13
T1
T12M3
Tr3
Direction register
Data bus
Port latch
Port P1 2
T0
Tr4
Direction register
Data bus
Port latch
Port P1 1
Tr5
Direction register
Data bus
Port latch
Port P1 0
Tr1–T r5 are pull-up transistors
Fig. 17 Block diagram of ports P0, P1 0–P13
25
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Ports P1 4 –P17
SM7
Tr6
SM4
Direction register
Data bus
Port latch
Port P17
SRDY
SM2
SM3
Tr7
Direction register
Data bus
Port latch
Port P16
CLK output
CLK input
SM3
Tr8
SM7
Direction register
Data bus
Port latch
Port P15
SOUT
Tr9
Direction register
Data bus
Port latch
Port P14
SIN
Data bus
Pull-up control
register
Tr6–Tr9 are pull-up transistors
Fig. 18 Block diagram of ports P1 4–P17
26
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P2
* : Control in units of 4-bit
Data bus
Pull-up control register *
Tr10
Direction register
Data bus
Port latch
Port P2
A-D conversion circuit
Multiplexer
Port P3
Data bus
Port P3
INT0 , INT1
CNTR0 , CNTR1
Port P4
Data bus
* : Control in units of 4-bit (Control in units of 2-bit for 7470 group)
Pull-up control register *
Tr11
Direction register
Data bus
Port latch
Port P4
Tr10–T r11 are pull-up transistors
Fig. 19 Block diagram of ports P2–P4
27
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P5
Data bus
Pull-up
control register
Tr12
Data bus
Port P53
Tr13
Data bus
Port P5 2
CM4
Tr14
Data bus
Port P51
CM4
CM4
XCIN
CM4
Tr15
Data bus
Port P50
Tr12–Tr15 are pull-up transistors
Note : 7470 group does not have this port.
Fig. 20 Block diagram of port P5
28
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 7470 group has one internal clock generating circuit and 7471
group has two internal clock generating circuits.
Figure 25 shows a block diagram of the clock generating circuit.
Normally, the frequency applied to the clock input pin XIN divided
by two is used as the internal clock φ. Bit 7 of CPU mode register
can be used to switch the internal clock φ to 1/2 the frequency applied to the clock input pin XCIN in the 7471 group.
Figure 21, 22 show a circuit example using a ceramic resonator
(or a quartz-crystal oscillator). Use the manufacturer’s recommended values for constants such as capacitance which will differ
depending on each oscillator. When using an external clock signal,
input from the XIN(XCIN ) pin and leave the XOUT (XCOUT) pin open.
A circuit example is shown in Figure 23, 24.
The 7470/7471 group has two low power dissipation modes; stop
and wait. The microcomputer enters a stop mode when the STP
instruction is executed. The oscillator (both XIN clock and XCIN
clock) stops with the internal clock φ held at “H” level. In this case
timer 3 and timer 4 are forcibly connected and FF 16 is automatically set in timer 3 and 0716 in timer 4.
Although oscillation is restarted when an external interrupt is accepted, the internal clock φ remains in the “H” state until timer 4
overflows. In other words, the internal clock φ is not supplied until
timer 4 overflows. This is because when a ceramic or similar other
oscillator is used, a finite time is required until stable oscillation is
obtained after restart.
The microcomputer enters an wait mode when the WIT instruction
is executed. The internal clock φ stops at “H” level, but the oscillator does not stop. φ is re-supplied (wait mode release) when the
microcomputer receives an interrupt.
Instructions can be executed immediately because the oscillator is
not stopped. The interrupt enable bit of the interrupt used to reset
the wait mode or the stop mode must be set to “1” before executing the WIT or the STP instruction.
Low power dissipation operation is also achieved when the XIN
clock is stopped and the internal clock φ is generated from the
XCIN clock (30 µA typ. at f(X CIN) = 32 kHz). This operation is only
7471 group. X IN clock oscillation is stopped when the bit 6 of CPU
mode register is set and restarted when it is cleared. However, the
wait time until the oscillation stabilizes must be generated with a
program when restarting. Figure 27 shows the transition of states
for the system clock.
M37470M2-XXXSP
XIN
XOUT
Rd
CIN
COUT
Fig. 21 Example of ceramic resonator circuit (7470 group)
M37471M2-XXXSP/FP
XOUT
XIN
XCIN
XCOUT
Rd
CIN
COUT
Rd
CCIN
CCOUT
Fig. 22 Example of ceramic resonator circuit (7471 group)
M37470M2-XXXSP
XIN
XOUT
Open
VCC
VSS
External oscillating circuit
Fig. 23 External clock input circuit (7470 group)
M37471M2-XXXSP/FP
XIN
XOUT
Open
XCIN
XCOUT
Open
External oscillating External oscillating circuit or
circuit
external pulse
VCC
VSS
VCC
VSS
Fig. 24 External clock input circuit (7471 group)
29
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT
XIN
XOUT
1/2
T34M0
(Note 1)
Timer 3
1/8
1/2
CM 7
Timer 4
T34M 1
T34M 2
CM6
CM7
Internal clock φ
S Q
Q S
R
WIT
instruction
STP
instruction
QQ S
S
R
R
R
Reset
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Select gate : At reset, shaded
side is connected
Notes 1 : Refer to Timer 3 of [Figure 6 Block diagram of timer 1 through 4]
2 : 7470 group does not have X CIN input and XCOUT output.
Fig. 25 Block diagram of clock generating circuit
b7
b0
CPU mode register
(Address 00FB 16)
These bits must always be set to “0”.
Stack page selection bit (Note 1)
0 : In page 0 area
1 : In page 1 area
Nothing is allocated (The value is undefined at reading)
S50, P51 /XCIN , XCOUT selection bit (Note 2)
0 : P50, P51
1 : XCIN , XCOUT
XCOUT drive capacity selection bit (Note 2)
0 : Low
1 : High
Clock (XIN -XOUT ) stop bit (Note 2)
0 : Oscillates
1 : Stops
Internal system clock selection bit (Note 2)
0 : XIN -XOUT selected (normal mode)
1 : XCIN -XCOUT selected (low-speed mode)
Notes 1 : In the M37470M2, M37470M4/E4, M37471M2, M37471M4/E4, set this bit to “0”.
2 : In the 7470 group, set this bit to “0”.
Fig. 26 Structure of CPU mode register
30
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM4 = 0
CM5 = 0
CM6 = 0
CM7 = 0
f(XIN ) oscillation
f(X IN) oscillation
WIT instruction
f(XCIN ) stop
φ stop
Timer operation
STP instruction
f(X CIN) stop
P50 , P51 input
φ stop
φ = f(XIN )/2
Interrupt
f(XIN ) stop
f(XCIN ) stop
Interrupt (Note 1)
CM5 = 1
CM4 = 1
CM 4 = 0
(Note 2)
f(XIN ) oscillation
WIT instruction
f(XIN ) oscillation
f(XCIN ) oscillation
φ = f(XIN )/2
Interrupt
f(XIN ) stop
f(XCIN ) stop
f(XCIN ) oscillation
φ stop
Timer operation
STP instruction
φ stop
Interrupt (Note 1)
(CM5 = 0)
CM 7 = 0
CM7 = 1
f(XIN ) oscillation
WIT instruction
f(XIN ) oscillation
f(XCIN ) oscillation
φ = f(XCIN )/2
Interrupt
f(XIN ) stop
f(XCIN ) stop
f(XCIN ) oscillation
φ stop
Timer operation
CM5 = 1
STP instruction
φ stop
Interrupt (Note 1)
CM 6 = 0
CM6 = 1
(Note 2)
f(XIN ) stop
WIT instruction
f(XCIN ) oscillation
Interrupt
φ = f(XCIN )/2
f(XIN ) stop
f(XCIN ) stop
f(XCIN ) oscillation
φ stop
Timer operation
f(XIN ) stop
CM5 = 1
STP instruction
φ stop
Interrupt (Note 1)
Notes 1 : Latency time is automatically generated upon release from the STP instruction due to the connections of timer 3
and 4.
2 : When the system clock is switched over by restarting clock oscillation, a certain wait time required for oscillation
to stabilize must be inserted by the program.
Fig. 27 Transition of states for the system clock
31
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
…
← Operating at f(X IN)
…
Normal program
…
Clock for clock function XC oscillation start (CM4 = 1, CM5 = 1)
↓
Latency time for oscillation to stabilize (by program) ← Operating at f(X IN)
↓
XC clock power down (CM5 : 1→0)
↓
Internal clock φ source switching X→XC (CM7 : 0→1)
↓
Clock X halt (XC in operation) (CM6 = 1)
↓
Internal clock halt (WIT instruction)
↓
Timer 4 (clock count) overflow
↓
Internal clock operation start (WIT instruction released)
Clock processing routine
← Operating at f(XCIN)
…
Operation on the clock function only
Power on reset
↓
Clock X oscillation
↓
Internal system clock start (X→1/2→ φ)
↓
Program start from RESET vector
Internal clock halt (WIT instruction)
Interrupts from INT0, INT 1, CNTR0/CNTR 1, timer 1, timer 2, timer 3, timer 4, serial I/O, key on wake up
↓
Internal clock operation start (WIT instruction released)
↓
Program start from interrupt vector
↓
Clock X oscillation start (CM 6 = 0)
↓
Latency time for oscillation to stabilize (by program)
← Operating at f(XCIN)
↓
Internal clock φ source switching (XC→X) (CM 7 : 1→0)
…



















Return from clock function


























32













Normal operation
<An example of flow for system>
Normal program
→ Operating at f(XIN)
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
…
STP instruction preparation (pushing registers)
↓
Timer 3, timer 4 interrupt disable
↓
X/16 or XC /16 selected for timer 3 count source; timer 3 overflow selected for timer 4 count source
↓
Timer 3, timer 4 start counting
↓
Values set to timer 3, timer 4 that do not cause timer 4 to overflow until STP instruction is executed
↓
Interrupt for return from STP enabled
↓
Timer 4 interrupt request bit cleared
↓
Clock X and clock for clock function X C halt (STP instruction)
RAM backup status
…
Interrupts from INT0 , INT1, CNTR0 /CNTR1 , timer 1, timer 2, serial I/O, key on wake up
↓
Clock X and clock for clock function X C oscillation start
↓
Timer 4 overflow (X/16 or XC/16→timer 3→timer 4)
↓
Internal system clock start
↓
Program start from interrupt vector
Normal program
…

















Return from RAM backup function























RAM backup function
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
33
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUILT-IN PROM TYPE MICROCOMPUTERS
PIN DESCRIPTION
Pin
Mode
Name
Input/
Output
Functions
VCC,VSS
Single-chip
/EPROM
Power source
Power source voltage inputs 2.7 to 5.5 V to VCC and 0 V to VSS .
AVSS
(Note 1)
Single-chip
/EPROM
Analog power
source
Ground level input pin for A-D converter. Same voltage as VSS is applied.
RESET
Single-chip
Reset input
EPROM
Reset input
Single-chip
/EPROM
Clock input
XIN
XOUT
VREF
P00 –P07
P30 –P33
P40 –P43
(Note 3)
P50 –P53
(Note 4)
Connect to VSS.
Input
Single-chip
Reference
voltage input
Input
Reference voltage input pin for the A-D converter.
EPROM
Select mode
Input
VREF works as CE input.
Single-chip
Single-chip
Single-chip
I/O port P0
I/O
Port P0 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 1-bit and a key
on wake up function is provided.
Data input/output D0–D7
I/O
Port P0 works as an 8-bit data bus (D 0–D7).
I/O port P1
I/O
Port P1 is an 8-bit I/O port. The output structure is CMOS output. When this port
is selected for input, pull-up transistor can be connected in units of 4-bit. P12 , P13
are in common with timer output pins T0, T1 . P1 4, P1 5, P1 6, P1 7 are in common
with serial I/O pins S IN , SOUT, CLK, SRDY, respectively. The output structure of
SOUT and SRDY can be changed to N-channel open drain output.
Address input A4–A10
I/O port P2
Input
I/O
34
:
:
:
:
P11 –P17 works as the 7-bit address input (A4–A10). P1 0 must be opened.
Port P2 is an 8-bit input port. This port is in common with analog input pins IN0–IN7.
EPROM
Address input
A0–A3
Input
P20 –P23 works as the lower 4-bit address input (A0–A3).
P24–P27 must be opened.
Single-chip
Input port P3
Input
Port P3 is a 4-bit input port. P3 0, P3 1 are in common with external interrupt input
pins INT 0, INT 1 and P32, P33 are in common with timer input pins CNTR0, CNTR1.
EPROM
Address input
A11, A12
Select mode
VPP input
Input
P30 , P31 works as the 2-bit address input (A11, A12 ).
P32 works as OE input. Connect to P33 to VPP when programming or verifying.
Single-chip
I/O port P4
I/O
Port P4 is a 4-bit I/O port. The output structure is CMOS output. When this port is
selected for input, pull-up transistor can be connected in units of 4-bit.
EPROM
Address input
A13, A14
Input
P40 , P41 works as the higher 2-bit address input (A13 , A14 ).
P42 , P43 must be opened.
Single-chip
Input port P5
Input
Port P5 is a 4-bit input port and pull-up transistor can be connected in units of 4bit. P50 , P51 are in common with input/output pins of clock for clock function X CIN,
XCOUT. When P5 0, P51 are used as XCIN , XCOUT, connect a ceramic or a quartzcrystal oscillator between X CIN and XCOUT. If an external clock input is used, connect the clock input to the X CIN pin and open the XCOUT pin. Feedback resistor is
connected between XCIN and XCOUT pins.
EPROM
Notes 1
2
3
4
These are I/O pins of internal clock generating circuit for main clock. To control
generating frequency, an external ceramic or a quartz-crystal oscillator is connected between the XIN and XOUT pins. If an external clock is used, the clock
source should be connected the X IN pin and the X OUT pin should be left open.
Feedback resistor is connected between XIN and X OUT.
Output
EPROM
P20 –P27
(Note 2)
To enter the reset state, the reset input pin must be kept at a “L” for 2 µs or more
(under normal VCC conditions).
Clock output
EPROM
P10 –P17
Input
AVSS for M37471M2/M4/M8/E4/E8-XXXFP.
Only P20–P23 (IN0–IN 3) 4-bit for the 7470 group.
Only P40 and P4 1 2-bit for the 7470 group.
This port is not included in the 7470 group.
Open.
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
EPROM MODE
Table 2. Pin function in EPROM mode
The M37470E4/E8, M37471E4/E8 feature an EPROM mode in addition to its normal modes. When the RESET signal level is low
(“L”), the chip automatically enters the EPROM mode. Table 2 lists
the correspondence between pins and Figure 30 to 32 give the pin
connection in the EPROM mode. When in the EPROM mode,
ports P0, P1 1–P17, P2 0–P23, P3, P4 0, P4 1, VREF are used for the
PROM (equivalent to the M5L27256). When in this mode, the builtin PROM can be written to or read from using these pins in the
same way as with the M5L27256. The oscillator should be connected to the X IN and X OUT pins, or external clock should be
connected to the XIN pin.
M37470E4/E8, M37471E4/E8
M5L27256
VCC
VCC
VCC
VPP
P33
VPP
VSS
VSS
VSS
Ports
Address input
Data I/O
P11–P17, P20–P23 ,
P30, P31, P40 , P41
Port P0
D0–D7
CE
VREF
CE
OE
P32
OE
42
P52
P17/SRDY
2
41
P07
D7
A9
P16 /CLK
3
40
P06
D6
A8
P15/SOUT
4
39
P05
A7
P14/SIN
5
38
P04
D5
D4
A6
P13/ T1
6
37
P03
D3
A5
P12/ T0
7
36
P02
D2
P11
8
P10
9
A4
P27/IN 7
10
P26/IN 6
11
P25/IN 5
12
P24/IN 4
13
A3
P23/IN 3
14
A2
P22/IN 2
A1
P21/IN 1
A0
CE
VSS
M37471E4-XXXSP
M37471E8-XXXSP
M37471E8SS
1
A10
P53
A0–A14
35
P01
D1
34
P00
D0
33
P43
32
P42
31
P41
30
P40
A13
29
P33 /CNTR1
VPP
15
28
P32 /CNTR0
OE
16
27
P31 /INT1
A12
P20/IN 0
17
26
P30 /INT0
A11
VREF
18
25
RESET
XIN
19
24
P51 /XCOUT
XOUT
20
23
P50 /XCIN
VSS
21
22
VCC
A14
VSS
VCC
: Same functions as M5L27256
Fig. 28 Pin connection in EPROM mode
35
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
OE
A12
A11
29
30
31
33
32
34
35
37
36
39
38
41
40
42
47
26
48
25
49
24
M37471E4-XXXFP
M37471E8-XXXFP
50
51
23
22
VCC
VSS
16
15
14
13
RESET
NC
P51/XCOUT
P50/XCIN
NC
VCC
VSS
AVSS
NC
XOUT
XIN
NC
CE
A7
A6
A5
A4
A3
A2
A1
A0
NC
P14/SIN
P13/ T1
P12 / T0
P11
P10
P27/IN7
P26 /IN6
P25 /IN5
P24/IN 4
P23/IN3
P22/IN2
P21/IN1
P20 /IN0
VREF
NC
12
17
11
18
56
10
19
55
9
20
54
8
53
6
21
7
52
1
A8
27
5
A9
28
46
4
A10
45
3
VSS
NC
P05
P06
P07
P52
NC
VSS
P53
P17/SRDY
P16/SCLK
P15 /SOUT
NC
2
D5
D6
D7
43
44
NC
P04
P03
P02
P01
P00
P43
P42
P41
P40
NC
P33/CNTR1
P32/CNTR0
P31/INT1
P30 /INT0
NC
D4
D3
D2
D1
D0
A14
A13
VPP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
: Same functions as M5L27256
Fig. 29 Pin connection in EPROM mode
P17/SRDY
1
32
P07
P16 /CLK
2
31
P06
D7
D6
A8
P15 /SOUT
3
30
P05
D5
A7
P14/SIN
4
29
P04
D4
A6
P13/ T1
5
28
P03
D3
A5
P12/ T0
6
27
P02
D2
A4
P11
7
26
P01
D1
P10
8
25
P00
D0
A3
P23/IN 3
9
24
P41
A14
A2
P22/IN 2
10
23
P40
A13
A1
P21/IN 1
11
22
P33/CNTR1
VPP
A0
P20/IN 0
12
21
P32/CNTR0
OE
CE
VREF
13
20
P31/INT1
A12
A11
VSS
M37470E4-XXXSP
M37470E8-XXXSP
A10
A9
XIN
14
19
P30/INT0
XOUT
15
18
RESET
VSS
16
17
VCC
: Same functions as M5L27256
Fig. 30 Pin connection in EPROM mode
36
VCC
VSS
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROM READING AND WRITING
Reading
NOTES ON HANDLING
To read the PROM, set the CE and OE pins to “L” level. Input the
address of the data (A0–A14 ) to be read and the data will be output to the I/O pins (D0–D7). The data I/O pins will be floating when
either the CE or OE pin is in the “H” state.
Writing
To write to the PROM, set the OE pin to “H” level. The CPU will enter the program mode when VPP is applied to the VPP pin. The
address to be written to is selected with pins A 0 –A14, and the
data to be written is input to pins D0–D7. Set the CE pin to “L” level
to begin writing.
Notes on Writing
• M37470E4, M37471E4
When using a PROM programmer, the address range should be
between 6000 16 and 7FFF 16. Addresses 000016 to 5FFF 16 cannot be written to or read from correctly.
• M37470E8, M37471E8
When using a PROM programmer, the address range should be
between 4000 16 and 7FFF16 . When data is written between addresses 0000 16 and 7FFF 16, fill addresses 000016 to 3FFF 16
with FF 16.
(1) Sunlight and fluorescent light contain wave lengths capable of
erasing data. For ceramic package types, cover the transparent window with a seal (provided) when this chip is in use.
However, this seal must not contact the lead pins.
(2) Before erasing, the glass should be cleaned and stains such
as finger prints should be removed thoroughly. If these stains
are not removed, complete erasure of the data could be prevented.
(3) Since a high voltage (12.5 V) is used to write data, care should
be taken when turning on the PROM programmer’s power.
(4) For the programmable microcomputer (shipped in One Time
PROM version), Mitsubishi does not perform PROM write test
and screening in the assembly process and following processes. To improve reliability after write, performing write and
test according to the flow below before use is recommended.
Writing with PROM programmer
Screening (Caution) (Leave at 150°C for 40 hours)
Verify test with PROM programmer
Erasing
Data can only erased on the M37471E8SS ceramic package,
which includes a window. To erase data on this chip, use an ultraviolet light source with a 2537 Angstrom wave length. The
minimum radiation power necessary for erasing is 15W·s/cm 2.
Function check in target device
Caution : Since the screening temperature is higher than storage
temperature, never expose to 150°C exceeding 100
hours.
Table 3. I/O signal in each mode
Pin
CE
OE
VPP
VCC
Data I/O
Read-out
VIL
VIL
VCC
VCC
Output
Output disable
VIL
VIH
VCC
VCC
Floating
Programming
VIL
VIH
VPP
VCC
Input
Programming verify
VIH
VIL
VPP
VCC
Output
Program disable
VIH
VIH
VPP
VCC
Floating
Mode
Note : VIL and V IH indicate a “L” and “H” input voltage, respectively.
37
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PROGRAMMING NOTES
(1) The frequency ratio of the timer is 1/(n+1).
(2) The contents of the interrupt request bits are not modified immediately after they have been written. After writing to an
interrupt request register, execute at least one instruction before executing a BBC or BBS instruction.
(3) To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. Only the ADC
and SBC instruction yield proper decimal results. After executing an ADC or SBC instruction, execute at least one
instruction before executing a SEC, CLC, or CLD instruction.
(4) An NOP instruction must be used after the execution of a PLP
instruction.
(5) Do not execute the STP instruction during A-D conversion.
(6) In the M37470, set bit 0, bit 1, and bit 3–bit 7 to “0” of the CPU
mode register.
(7) Multiply/Divide instructions
The index X mode (T) and the decimal mode (D) flag do not
affect the MUL and DIV instruction.
The execution of these instructions does not modify the contents of the processor status register.
DATA REQUIRED FOR MASK ORDERING
Please send the following data for mask orders.
(1) mask ROM confirmation form
(2) mark specification form
(3) ROM data ......................................................... EPROM 3 sets
38
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
VCC
Power source voltage
VI
Input voltage XIN
VI
Input voltage P00–P07 , P10–P17, P20 –P23,
P30–P33, P4 0, P41 , VREF, RESET
VO
Output voltage
All voltages are based on V SS.
Output transistors are cut off.
P00–P07, P10–P17 , P20–P23,
P40, P41, XOUT
Ratings
Unit
–0.3 to 7
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
V
Pd
Power dissipation
1000
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 150
°C
Ta = 25°C
RECOMMENDED OPERATING CONDITIONS
Symbol
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Parameter
Min.
f(XIN) = 2.2VCC–2.0 MHz
2.7
f(XIN) = 8 MHz
4.5
Typ.
Max.
4.5
Unit
VCC
Power source voltage
VSS
Power source voltage
VIH
“H” input voltage
P00 –P07 , P10–P17, P30–P33 , RESET, XIN
0.8VCC
VIH
“H” input voltage
P20 –P23 , P40, P41
0.7VCC
VIL
“L” input voltage P0 0–P07, P10–P17, P30–P33
0
VIL
“L” input voltage
0
0.25V CC
V
VIL
“L” input voltage RESET
0
0.12V CC
V
VIL
“L” input voltage
0
0.16V CC
V
I OH(sum)
“H” sum output current P00–P07, P40 , P41
–30
mA
I OH(sum)
“H” sum output current P10–P17, P20–P23
–30
mA
I OL(sum)
“L” sum output current P0 0–P07, P40, P41
60
mA
I OL(sum)
“L” sum output current P1 0–P17, P20–P23
60
mA
I OH(peak)
“H” peak output current P0 0–P07, P10–P17 , P20–P23, P40 , P41
–10
mA
I OL(peak)
“L” peak output current P0 0–P07, P10–P17 , P20 –P23, P40, P41
20
mA
I OH(avg)
“H” average output current P0 0–P07, P10–P17 , P20–P23, P40, P4 1 (Note 2)
–5
mA
I OL(avg)
“L” average output current
10
mA
f( CNTR)
f( CLK)
f(XIN )
5.5
XIN
P00–P07 , P10 –P17, P20–P23, P40, P41 (Note 2)
CNTR0 (P3 2),
Serial I/O clock input frequency
SCLK (P16) (Note 1)
VCC
V
VCC
V
0.2V CC
V
f(XIN) = 4 MHz
1
f(XIN) = 8 MHz
2
f(XIN) = 4 MHz
1
f(XIN) = 8 MHz
2
VCC = 2.7 to 4.5 V
Clock input oscillation frequency (Note 1)
VCC = 4.5 to 5.5 V
V
V
0
P20 –P23 , P40, P41
Timer input frequency
CNTR1 (P33) (Note 1)
5
2.2VCC – 2.0
MHz
MHz
MHz
8
Notes 1 : Oscillation frequency is at 50% duty cycle.
2 : The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.
39
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37470M2/M4/M8-XXXSP, M37470E4/E8-XXXSP
ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
Parameter
Limits
Test Conditions
Min.
Typ.
Max.
VOH
“H” output voltage P00 –P07 ,
P10–P17 , P20–P23, P40 , P41
VCC = 5 V, I OH = –5 mA
3
VCC = 3 V, I OH = –1.5 mA
2
VOL
“L” output voltage P00–P07,
P10 –P17, P20–P23, P4 0, P41
VCC = 5 V, I OL = 10 mA
2
VCC = 3 V, I OL = 3 mA
1
VT + – V T–
Hysteresis P00 – P07,
P30 – P33
VCC = 5 V
0.5
VCC = 3 V
0.3
VCC = 5 V
0.5
VCC = 3 V
0.3
VT + – VT–
VT + – VT–
I IL
I IL
I IL
Hysteresis
RESET
Hysteresis P16 /CLK
“L” input current P00 –P07 ,
P10–P17 , P30–P32, P40 –P41
“L” input current P33
use as CLK input
V
VCC = 5 V
0.5
VCC = 3 V
0.3
V
V
VCC = 5 V
–5
VCC = 3 V
–3
VI = 0 V,
use pull-up transistor
VCC = 5 V
–0.25
–0.5
–1.0
VCC = 3 V
–0.08
–0.18
–0.35
VCC = 5 V
–5
VCC = 3 V
–3
VI = 0 V, not use as analog input,
not use pull-up transistor
VCC = 5 V
–5
VCC = 3 V
–3
VI = 0 V, not use as analog input,
use pull-up transistor
VCC = 5 V
–0.25
–0.5
–1.0
VCC = 3 V
–0.08
–0.18
–0.35
“L” input current P2 0–P23
–5
“L” input current RESET, X IN
VI = 0 V
(X IN is at stop mode)
VCC = 5 V
I IL
VCC = 3 V
–3
“H” input current P00–P07,
P10–P17 , P30–P32, P40 , P41
VI = VCC,
not use pull-up transistor
VCC = 5 V
I IH
5
VCC = 3 V
3
VCC = 5 V
I IH
“H” input current P33
VI = VCC
5
VCC = 3 V
3
“H” input current P20–P23
VI = VCC, not use as analog input,
not use pull-up transistor
VCC = 5 V
I IH
5
VCC = 3 V
3
“H” input current
VI = VCC,
(X IN is at stop mode)
VCC = 5 V
I IH
5
VCC = 3 V
3
I CC
RESET, XIN
Power source current
At normal
mode, A-D
conversion is
not executed.
f(XIN)=8 MHz
At normal
mode, A-D
conversion is
executed.
f(XIN)=8 MHz
f(XIN)=4 MHz
f(XIN)=4 MHz
f(XIN)=8 MHz
At wait mode.
f(XIN)=4 MHz
At stop mode,
f(XIN)=0, VCC=5 V
VRAM
40
RAM retention voltage
Stop all oscillation
7
14
3.5
7
1.8
3.6
7.5
15
4
8
2
4
2
4
1
2
VCC = 3 V
0.5
1
Ta = 25°C
0.1
1
Ta = 85°C
1
10
VCC = 5 V
VCC = 3 V
VCC = 5 V
VCC = 3 V
VCC = 5 V
2
V
V
VI = 0 V,
not use pull-up transistor
VI = 0 V
Unit
5.5
µA
mA
µA
µA
mA
µA
µA
µA
µA
µA
mA
mA
mA
µA
V
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, f(X IN)=4 MHz, unless otherwise noted)
Symbol
Parameter
–
Resolution
–
Non-linearity error
–
Differential non-linearity error
VOT
VFST
t CONV
Zero transition error
Full-scale transition error
Conversion time
Test Conditions
Limits
Min.
Typ.
Unit
Max.
8
bits
±2
LSB
±0.9
LSB
VCC = VREF = 5.12 V, IOL (sum) = 0 mA
2
VCC = VREF = 3.072 V, IOL (sum) = 0 mA
3
VCC = VREF = 5.12 V
4
VCC = VREF = 3.072 V
7
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
25
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
12.5
VREF
Reference input voltage
0.5VCC
RLADDER
Ladder resistance value
2
VIA
Analog input voltage
0
VCC
5
10
VREF
LSB
LSB
µs
V
kΩ
V
41
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
Ratings
Unit
VCC
Power source voltage
–0.3 to 7
V
VI
Input voltage XIN
–0.3 to VCC +0.3
V
VI
Input voltage P0 0–P07, P10 –P17, P20–P27, All voltages are based on V SS.
P30–P3 3, P40–P43, P50–P53, VREF, RESET Output transistors are cut off.
–0.3 to VCC +0.3
V
VO
Output voltage
–0.3 to VCC +0.3
V
Pd
Power dissipation
1000 (Note 1)
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 150
°C
P00–P07 , P10–P17,
P20–P27 , P40–P43, XOUT
Ta = 25°C
Note 1 : 500 mW for M37471M2/M4/M8-XXXFP.
RECOMMENDED OPERATING CONDITIONS
Symbol
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85°C unless otherwise noted)
Limits
Parameter
Min.
f(XIN) = 2.2V CC – 2.0 MHz
2.7
f(XIN) = 8 MHz
4.5
Typ.
Max.
4.5
Unit
VCC
Power source voltage
VSS
Power source voltage
0
V
AVSS
Analog power source voltage
0
V
VIH
“H” input voltage
P00–P07 , P10–P17, P30–P33, RESET, XIN
0.8VCC
VCC
V
VIH
“H” input voltage
P20–P27 , P40–P43, P50–P53 (Note 1)
0.7VCC
VCC
V
VIL
“L” input voltage P00 –P07 , P10 –P17 , P30 –P33
0
0.2V CC
V
VIL
“L” input voltage P20–P27, P40–P43, P50–P53 (Note 1)
0
0.25V CC
V
VIL
“L” input voltage RESET
0
0.12V CC
V
VIL
“L” input voltage XIN
0
0.16V CC
V
I OH(sum)
“H” sum output current P00–P07, P40–P43
– 30
mA
I OH(sum)
“H” sum output current P10–P17, P20–P27
– 30
mA
I OL(sum)
“L” sum output current P0 0–P07, P40–P43
60
mA
I OL(sum)
“L” sum output current P1 0–P17, P20–P27
60
mA
I OH(peak)
“H” peak output current P00 –P07, P10–P17, P2 0–P27, P40–P43
– 10
mA
I OL(peak)
“L” peak output current P0 0–P07, P10–P17, P20–P27 , P40 –P43
20
mA
I OH(avg)
“H” average output current P0 0–P07, P10–P17, P20 –P27, P40–P43 (Note 2)
–5
mA
I OL(avg)
“L” average output current P00–P07, P10–P17, P20–P27 , P40–P43 (Note 2)
10
mA
f( CNTR)
Timer input frequency CNTR 0 (P32),
CNTR1 (P33) (Note 3)
f(XIN) = 4 MHz
1
f(XIN) = 8 MHz
2
Serial I/O clock input frequency
SCLK (P16) (Note 3)
f(XIN) = 4 MHz
1
f(XIN) = 8 MHz
2
f( CLK)
f(XIN )
Main clock input oscillation frequency (Note 3)
f(XCIN )
Notes 1
2
3
4
42
:
:
:
:
5
VCC = 2.7 to 4.5 V
2.2V CC – 2.0
VCC = 4.5 to 5.5 V
Sub-clock input oscillation frequency for clock function (Note 3, 4)
It is except to use P50 as XCIN.
The average output current IOH (avg) and IOL (avg) are the average value during a 100 ms.
Oscillation frequency is at 50% duty cycle.
When used in the low-speed mode, the clock oscillation frequency for clock function should be f(XCIN ) < f(XIN) / 3.
5.5
V
MHz
MHz
MHz
8
32
50
kHz
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M37471M2/M4/M8-XXXSP/FP, M37471E4/E8-XXXSP/FP, M37471E8SS
ELECTRICAL CHARACTERISTICS (V CC = 2.7 to 5.5 V, V SS = AVSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Symbol
VOH
VOL
VT + – V T–
Parameter
“H” output voltage
P00–P07,
P10–P17 , P20–P27, P4 0–P43
“L” output voltage
P00–P07,
P10–P17 , P20–P27, P4 0–P43
Hysteresis
VT + – VT–
Hysteresis
VT + – VT–
Hysteresis
I IL
I IL
I IH
VCC = 5 V, IOH = –5 mA
3
VCC = 3 V, IOH = –1.5 mA
2
Typ.
VCC = 5 V, IOL = 10 mA
2
VCC = 3 V, IOL = 3 mA
1
VCC = 5 V
0.5
VCC = 3 V
0.3
VCC = 5 V
0.5
VCC = 3 V
0.3
RESET
P16 /CLK
used as CLK input
“L” input current
“L” input current
P33
“H” input current P00–P07, P10–P17 ,
P30–P32 , P40–P43 , P50–P53
0.5
VCC = 3 V
0.3
V
–5
VCC = 3 V
–3
VI = 0 V,
use pull-up transistor
VCC = 5 V
–0.25
–0.5
–1.0
VCC = 3 V
–0.08
–0.18
–0.35
VCC = 5 V
–5
VCC = 3 V
–3
V I = 0 V, not use as analog input,
not use pull-up transistor
VCC = 5 V
–5
VCC = 3 V
–3
VI = 0 V, not use as analog input,
use pull-up transistor
VCC = 5 V
–0.25
–0.5
–1.0
VCC = 3 V
–0.08
–0.18
–0.35
VI = 0 V
(XIN is at stop mode)
VCC = 5 V
–5
VCC = 3 V
–3
VI = VCC,
not use pull-up transistor
VCC = 5 V
5
VCC = 3 V
3
VCC = 5 V
5
VCC = 3 V
3
P20–P27
RESET, XIN
VCC = 5 V
I IH
“H” input current P33
VI = VCC
I IH
“H” input current P20–P27
VI = VCC, not use as analog input,
not use pull-up transistor
VCC = 5 V
5
VCC = 3 V
3
I IH
“H” input current
VI = VCC,
(XIN is at stop mode)
VCC = 5 V
5
VCC = 3 V
3
RESET, XIN
At normal
mode, A-D
conversion is
not executed.
At normal
mode, A-D
conversion is
executed.
I CC
Power source current
f(XIN)=8 MHz
7
VCC = 5 V
f(XIN)=4 MHz
VCC = 3 V
f(XIN)=8 MHz
VCC = 5 V
f(XIN)=4 MHz
7.5
15
4
8
2
4
80
VCC = 3 V
15
40
2
4
1
2
VCC = 3 V
0.5
1
At wait mode, XIN = 0 Hz, XCIN
= 32 kHz, X COUT is low-power
mode, T a=25°C
VCC = 5 V
3
12
VCC = 3 V
2
8
Stop all oscillation
VCC = 5 V
Ta = 25°C
0.1
1
1
10
VCC = 5 V
f(XIN)=4 MHz
RAM retention voltage
3.6
30
f(XIN)=8 MHz
VRAM
7
1.8
VCC = 5 V
At wait mode.
Stop all oscillation
Ta = 85°C
2
µA
mA
µA
µA
mA
µA
µA
µA
µA
µA
14
3.5
VCC = 3 V
At low-speed mode, T a=25°C, f(XIN)=0,
f(XCIN)=32 kHz, X COUT drive capacity
is low, A-D conversion is not executed.
V
V
VCC = 5 V
VI = 0 V
Unit
V
VI = 0 V,
not use pull-up transistor
P00–P07, P1 0–P17, P30 –P32,
“L” input current
Max.
V
P00–P07,
P40–P43, P5 0–P53
I IL
Min.
P30–P33
“L” input current
I IL
Limits
Test Conditions
mA
mA
µA
mA
µA
V
43
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER CHARACTERISTICS
(VCC = 2.7 to 5.5 V, VSS =AVSS = 0 V, Ta = –20 to 85°C, f(XIN) = 4 MHz, unless otherwise noted)
Symbol
Parameter
–
Resolution
–
Non-linearity error
–
Differential non-linearity error
VOT
VFST
t CONV
Zero transition error
Full-scale transition error
Conversion time
Test Conditions
Limits
Min.
Unit
Max.
8
bits
±2
LSB
±0.9
LSB
VCC = VREF = 5.12 V, IOL (sum) = 0 mA
2
VCC = VREF = 3.072 V, IOL (sum) = 0 mA
3
VCC = VREF = 5.12 V
4
VCC = VREF = 3.072 V
7
VCC = 2.7 to 5.5 V, f(XIN) = 4 MHz
25
VCC = 4.5 to 5.5 V, f(XIN) = 8 MHz
12.5
VREF
Reference input voltage
0.5VCC
RLADDER
Ladder resistance value
2
VIA
Analog input voltage
44
Typ.
0
VCC
5
10
VREF
LSB
LSB
µs
V
kΩ
V
MITSUBISHI MICROCOMPUTERS
7470/7471 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
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Notes regarding these materials
•
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© 1998 MITSUBISHI ELECTRIC CORP.
New publication, effective Jan. 1998.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
7470/7471 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
980110
(1/1)