Fairchild AN-5029 Interfacing between pecl and lvds differential technology Datasheet

Fairchild Semiconductor
Application Note
August 2002
Revised August 2002
Interfacing Between
PECL and LVDS Differential Technologies
Introduction
Over the past several years, growth in the demand for
high-speed data transmission has spawned dramatic
changes and innovations in high-speed ICs. Achieving
these increased levels of high performance, lower power
and improved noise immunity involves optimizing the interface between ICs. Often times a more cost effective solution requires interfacing between ICs with different I/O
voltage levels and technology requirements. System
designers must familiarize themselves with the different I/O
circuit configurations to understand the requirements for
proper biasing and effective termination necessary to maintain good signal integrity between differing technologies.
This application note will describe an approach to interfacing Positive Emitter Coupled Logic (PECL) with Low Voltage Differential Signaling (LVDS) technologies.
FIGURE 1. ECL Device Configured for PECL Operation
What is LVDS?
What is PECL?
Emitter Coupled Logic (ECL) is an ultra-high speed digital
logic technology and is based on a differential amplifier.
Small signal swings prevent saturation during switching
and increase operating frequency performance. The input
and output voltage levels are referenced directly to VCC/
VCCA pins which are normally zero volts or ground potential
operating with a negative VEE and negative termination
VTT supplies. With PECL operation the VCC/VCCA pins are
offset to the positive +5V nominal potential, VTT is offset by
+5V from −2V to +3V and the VEE pin becomes 0V or
ground potential. Refer to the schematic representation of
the PECL operation and the associated voltage levels in
Figure 1.
LVDS technology is defined by the ANSI/TIA/EIA-644
industry standard. LVDS is targeted for general purpose
high speed applications requiring very low noise and minimal power consumption. Using a constant current source
driver allows power consumption to be relatively independent of frequency resulting in greater performance. LVDS
drivers have a very low differential swing of typically 350
mV, which is centered on an offset voltage of 1.2V above
circuit common (ground). With lower signal swings, higher
data rates can be achieved as it takes less time to transition between logic states. Noise concerns are reduced with
differential signaling techniques as noise is coupled onto
both conductors with equal magnitude and phase and is
rejected by the receiver, which senses the difference
between the two signals.
TABLE 1. Signal Voltage Comparisons
DC Parameter
5V PECL
LVPECL
LVDS
Power Supply, VCC
+5.0V
3.3V
3.3V
Output HIGH, VOH
4.0V
2.4V
1.4V
Output LOW, VOL
3.3V
1.7V
1.0V
595 to 960 mV
595 to 930 mV
247 to 454 mV
3.65V
2.1V
1.2V
Differential Output, VOD
Common Mode Voltage, VOS
© 2002 Fairchild Semiconductor Corporation
AN500622
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AN-5029 Interfacing Between PECL and LVDS Differential Technologies
AN-5029
AN-5029
5V PECL to 5V LVDS Interface
driving a 5V LVDS receiver. The configuration is possible
providing the receiver has a wide common mode range that
accommodates the worst case PECL output levels and
compliance to all device datasheet specifications is met. To
ensure proper operation of the PECL device within the system the tolerances of the VTT and VCC supplies should be
considered. Refer to waveforms in Figure 3, illustrating the
PECL to LVDS interface operation. Although the configuration conserves power and keeps component count low, an
additional power supply is required.
For a PECL driver, each emitter follower output is properly
terminated with a 50Ω resistor to a termination voltage of
VTT = VCC − 2V. Although this termination technique will
consume significantly less power, an additional supply for
the termination voltage may be undesirable for the system.
The LVDS receiver should have a sufficiently wide common
mode range to respond to the output signals from the
PECL driver. Figure 2 shows how the interface can be configured using a split resistor termination with a VTT of (VCC
− 2V). This configuration consists of a +5V PECL device
FIGURE 2. PECL to 5V LVDS Interface
FIGURE 3. PECL to 5V LVDS Interface
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rated in the design increases the more attractive the VTT
termination scheme becomes. Typically, trade-offs
between the performance requirements and system costs
will dictate which approach the designer will use. The parallel termination technique using an extra VTT power supply is shown in Figure 4. Refer to the Figure 5 for
waveforms of the LVPECL to LVDS interconnect. This configuration conserves power and keeps component count
low, however requires an additional supply voltage.
A similar bench set up was evaluated using an LVPECL
driver with a 1-meter CAT5 Unshielded Twisted Pair (UTP)
cable as a 100Ω characteristic impedance transmission
media driving a Fairchild FIN1018 LVDS receiver. Although
power consumption is significantly less, the parallel termination scheme requires an extra VTT power supply for the
impedance matching load resistor. Depending on the system this extra power supply requirement may prohibit use
of this technique. As the number of PECL devices incorpo-
FIGURE 4. LVPECL to 3V LVDS Interface
Note: Channel 1: LVTTL Input
Channel 2 and 3: Single Ended LVPECL Outputs
Channel 4: LVTTL Output from LVDS Receiver
FIGURE 5. LVPECL to 3V LVDS Interface
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AN-5029
LVPECL to 3V LVDS Interface
AN-5029
Thevenin Equivalent Termination Scheme
being sourced by the device, hence will not alter the reliability of the IC.
As previously mentioned, since an LVPECL output is
designed to drive a 50Ω load connected to a VTT of (VCC −
2V), using a termination supply voltage may not be available in the system application. An alternative approach
involves using a Thevenin equivalent parallel combination
of resistors which is equal to the transmission line impedance and shifts the PECL driver signals to be in the common mode input range of the LVDS receiver using a single
supply voltage. This technique will consume more termination power, however the absence of an additional power
supply will more than compensate for the extra power consumption. This extra power is consumed entirely in the
external resistor network and will not change the current
To explore this approach we will use an LVPECL driver
interfacing to a 3V LVDS receiver. A parallel Thevenin termination network as shown in Figure 6 will provide a resistor divider network to generate the proper DC levels for the
LVDS receiver. The resistor network ensures the LVPECL
outputs are terminated for a 50Ω load to (VCC - 2V) and will
attenuate the LVEPCL output signals to within the input
range of the LVDS receiver. While this technique increases
the component count and dissipates more termination
power, the additional VTT supply is not required.
FIGURE 6. LVPECL to LVDS Interface Using a Thevenin Equivalent Termination Scheme
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(Continued)
The characteristic line impedance is approximately 50Ω for each of the single ended lines, therefore the parallel combination of R1 || (R2 + R3) must provide the correct RT of 50Ω. To illustrate the attenuation resistor network the following equations will be used in the example:
Equation 1:
VA
= R1/(R1 + R2 + R3) = 2/VCC
Equation 2:
VB
= R3/(R1 + R2 + R3) = VIL/VCC
Equation 3:
VLVDSIN = R3/(R2 + R3) * VPECLOUT
Example:
Assume the following differential voltage levels
VLVDSIN
= 350 mV (typical)
VPECLOUT = 700 mV (typical)
= 3.3V
VCC
Using Equation 3:
Ratio of VLVDSIN/ VPECLOUT is 350 mV/700 mV = R3/(R2 + R3), since it’s a 1:2 relationship then R2 = R3
R1 || (R2 + R3) = 50Ω and since R2 = R3, replacing R3 with R2 this equation becomes R1 || (2*R2) = 50Ω
VA = R1/(R1 + R2 + R3) = 2/VCC
= R1/(R1 + R2 + R3) = 2/3.3V
VCC = 3.3V
= R1/(R1 + 2R2) = 0.61V
R3 = R 2
Solve for R1:
R1 = 0.61R1 + 1.22R2
(1 - 0.61)R1 = 1.22R2
R1 = 1.22R2
0.39
R1 = 3.13R2
(R2 ∼ 3 times larger than R1)
Solve for R2:
R1 || (2R2) = 50Ω
R1*2R2 = 50
R1+2R2
2R1R2 = 50R1 + 100R2
2(3.13R2)R2 = 50(3.13R2) + 100R2
R1 = 3.13R2, replace R1 with 3.13R2
R2 = 41Ω
Resistor values are R1 = 128Ω; R2 = 41Ω; R3 = 41Ω
The results of these calculations are non-standard resistor values, adjust and select the resistor values for the specific
application maintaining proper matching of the line impedance and termination of the LVPECL outputs.
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AN-5029
Thevenin Equivalent Termination Scheme
AN-5029 Interfacing Between PECL and LVDS Differential Technologies
Interfacing LVDS to LVPECL
tion resistor, typically 100Ω, for matching the transmission
line impedance without any additional attenuation resistor
network. Refer to Figure 7. For interfacing LVDS to PECL,
direct interface is possible providing the PECL receiver has
extended common mode range inputs to process the LVDS
signals when supplied with 5V ± 5% supply voltage.
If an application requires interfacing from LVDS to
LVPECL, direct interface is possible provided the LVPECL
line receiver has the proper differential common mode
input range. Refer to the individual LVPECL device
datasheets for the specifications and performance requirements. This solution would simply require a single termina-
FIGURE 7. LVDS to LVPECL Interface
Summary
mize reflections. The Thevenin equivalent of the two
resistors for each single ended transmission line needs to
be equal to the characteristic impedance of the line.
Although this scheme will consume more power, this extra
power is consumed entirely in the external resistor network
and will not change the current being sourced by the
device, hence will not alter the reliability of the IC. The
approaches illustrated in this application note provide
guidelines for understanding the requirements. Compliance
to all individual IC maximum ratings should be met to
ensure proper system performance.
Interfacing between multiple differential technologies presents some challenges to system designers who must
evaluate options for a cost-effective solution. Existing system requirements, signal integrity demands and costs will
dictate which approach is preferred to minimize risk and
optimize the reliability of the system. Although the single
resistor termination to VTT conserves power, the interface
requires an additional termination voltage which may be
impractical. An alternative approach to an additional power
supply is to use a resistor divider network to develop a
Thevenin voltage, termination voltage and provide impedance matching termination for the transmission line to mini-
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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