OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable Check for Samples: OPA690 FEATURES DESCRIPTION • The OPA690 represents a major step forward in unity-gain stable, voltage-feedback op amps. A new internal architecture provides slew rate and full-power bandwidth previously found only in wideband, current-feedback op amps. A new output stage architecture delivers high currents with a minimal headroom requirement. These combine to give exceptional single-supply operation. Using a single +5V supply, the OPA690 can deliver a 1V to 4V output swing with over 150mA drive current and 150MHz bandwidth. This combination of features makes the OPA690 an ideal RGB line driver or single-supply Analog-to-Digital Converter (ADC) input driver. 1 2 • • • • • • • FLEXIBLE SUPPLY RANGE: +5V to +12V Single Supply ±2.5V to ±5V Dual Supply UNITY-GAIN STABLE: 500MHz (G = 1) HIGH OUTPUT CURRENT: 190mA OUTPUT VOLTAGE SWING: ±4.0V HIGH SLEW RATE: 1800V/µs LOW SUPPLY CURRENT: 5.5mA LOW DISABLE CURRENT: 100µA WIDEBAND +5V OPERATION: 220MHz (G = 2) APPLICATIONS • • • • • • • VIDEO LINE DRIVING xDSL LINE DRIVER/RECEIVER HIGH-SPEED IMAGING CHANNELS ADC BUFFERS PORTABLE INSTRUMENTS TRANSIMPEDANCE AMPLIFIERS ACTIVE FILTERS The low 5.5mA supply current of the OPA690 is precisely trimmed at +25°C. This trim, along with low temperature drift, gives lower maximum supply current than competing products. System power may be reduced further using the optional disable control pin. Leaving this disable pin open, or holding it HIGH, will operate the OPA690 normally. If pulled LOW, the OPA690 supply current drops to less than 100mA while the output goes to a high-impedance state. This feature may be used for power savings. OPA690 RELATED PRODUCTS SINGLES DUALS TRIPLES Voltage-Feedback — OPA2690 OPA3690 Current-Feedback OPA691 OPA2691 OPA3691 Fixed Gain OPA692 — OPA3692 Single-Supply ADC Driver +5V R1 R1 3.3V 2.5V 0.1mF C1 R2 VI 3 8 C2 R4 20W OPA690 2 4 R3 R5 20W C4 10mF THS1040 C3 20pF C6 20pF AIN+ 10-Bit 40MSPS AIN- VREF = 1V C5 0.1mF 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2010, Texas Instruments Incorporated OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR OPA690 SO-8 D -40°C to +85°C OPA690 OPA690 SOT23-6 DBV -40°C to +85°C OAEI (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA690ID Rails, 100 OPA690IDR Tape and Reel, 2500 OPA690IDBVT Tape and Reel, 250 OPA690IDBVR Tape and Reel, 3000 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Power Supply Internal Power Dissipation OPA690 UNIT ±6.5 VDC See Thermal Analysis section Differential Input Voltage ±1.2 Input Voltage Range ±VS V –65 to +125 °C Storage Temperature Range: D, DBV Junction Temperature (TJ) ESD Ratings (1) V +175 °C Human Body Model (HBM) 2000 V Charge Device Model (CDM) 1500 V Machine Model (MM) 200 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. D PACKAGE SO-8 (TOP VIEW) DRB PACKAGE SOT23-6 (TOP VIEW) NC 1 8 DIS Inverting Input 2 7 +VS Noninverting Input 3 6 Output -VS 4 5 NC Output 1 6 +VS -VS 2 5 DIS Noninverting Input 3 4 Inverting Input 4 5 6 NOTE: NC = not connected. 3 2 1 OAEI Pin Orientation/Package Marking 2 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted. OPA690ID, IDBV MIN/MAX OVER TEMPERATURE TYP PARAMETER +25°C (2) 0°C to +70°C (3) -40°C to +85°C (3) 220 165 160 150 G = +10, VO = 0.5VPP 30 20 19 G ≥ 10 300 200 190 G = +2, VO < 0.5VPP 30 TEST CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = 25Ω 500 G = +2, VO = 0.5VPP MIN/ MAX TEST LEVELS (1) MHz typ C MHz min B 18 MHz min B 180 MHz min B MHz typ C UNIT AC PERFORMANCE (see Figure 36) Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 VO < 0.5VPP 4 dB typ C Large-Signal Bandwidth G = +2, VO < 0.5VPP 200 MHz typ C G = +2, 4V Step 1800 V/ms min B G = +2, VO = 0.5V Step 1.4 ns typ C Slew Rate Rise-and-Fall Time 1400 1200 900 G = +2, VO = 5V Step 2.8 ns typ C Settling Time to 0.02% G = +2, VO = 2V Step 12 ns typ C Settling Time to 0.1% G = +2, VO = 2V Step 8 ns typ C Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP xx x 2nd-Harmonic RL = 100Ω –68 –64 –62 –60 dBc max B RL ≥ 500Ω –77 –70 –68 –66 dBc max B RL = 100Ω –70 –68 –66 –64 dBc max B RL ≥ 500Ω –81 –78 –76 –75 dBc max B f > 1MHz 5.5 nV/√Hz typ C xx x 3rd-Harmonic Input Voltage Noise Input Current Noise f > 1MHz 3.1 pA/√Hz typ C Differential Gain G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.06 % typ C Differential Phase G = +2, NTSC, VO = 1.4VP, RL = 150Ω 0.03 deg typ C DC PERFORMANCE (4) Open-Loop Voltage Gain (AOL) VO = 0V, RL = 100Ω 69 58 56 54 dB min A Input Offset Voltage VCM = 0V ±1.0 ±4 ±4.5 ±4.7 mV max A xxx Average Offset Voltage Drift VCM = 0V ±10 ±10 mV/°C max B Input Bias Current VCM = 0V ±11 ±12 mA max A xxx Average Bias Current Drift (magnitude) VCM = 0V ±20 ±40 nA/°C max B Input Offset Current VCM = 0V ±1.4 ±1.6 mA max A xxx Average Offset Current Drift VCM = 0V ±7 ±9 nA/°C max B ±3 ±0.1 ±10 ±1.0 INPUT Common-mode Input Voltage (CMIR) (5) ±3.5 ±3.4 ±3.3 ±3.2 V min A VCM = ±1V 65 60 57 56 dB min A xxx Differential Mode VCM = 0V 190 || 0.6 kΩ || pF typ C xxx Common-Mode VCM = 0V 3.2 || 0.9 MΩ || pF typ C Common-Mode Rejection Ratio (CMRR) Input Impedance (1) (2) (3) (4) (5) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +10°C at high temperature limit for over temperature specifications. Current is considered positive out of node. Tested < 3dB below minimum specified CMRR at ±CMIR limits. 3 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 36 for ac performance only), unless otherwise noted. OPA690ID, IDBV MIN/MAX OVER TEMPERATURE TYP PARAMETER TEST CONDITIONS +25°C +25°C (2) 0°C to +70°C (3) -40°C to +85°C (3) UNIT MIN/ MAX TEST LEVELS (1) OUTPUT Voltage Output Swing No Load ±4.0 ±3.8 ±3.7 ±3.6 V min A RL = 100Ω ±3.9 ±3.7 ±3.6 ±3.3 V min A Current Output, Sourcing VO = 0V +190 +160 +140 +100 mA min A Current Output, Sinking VO = 0V –190 –160 –140 –100 mA min A Short-Circuit Current Limit VO = 0V ±250 mA typ C G = +2, f =100kHz 0.04 Ω typ C Power-Down Supply Current (+VS) VDIS = 0V –100 µA max A Disable Time VIN = 1VDC 200 ns typ C Enable Time VIN = 1VDC 25 ns typ C Off Isolation G = +2, RL = 150Ω, VIN = 0V 70 dB typ C Output Capacitance in Disable G = +2, RL = 150Ω, VIN = 0V 4 pF typ C Turn-On Glitch ±50 mV typ C Turn-Off Glitch ±20 mV typ C Enable Voltage 3.3 3.5 3.6 3.7 V min A Disable Voltage 1.8 1.7 1.6 1.5 V max A 75 130 150 160 µA max A V typ C ±6.0 ±6 ±6 V max A Closed-Loop Output Impedance DISABLE (Disabled LOW) Control Pin Input BIas Current (VDIS) VDIS = 0V –200 –240 –260 POWER SUPPLY Specified Operating Voltage ±5 Maximum Operating Voltage Range Maximum Quiescent Current VS = ±5V 5.5 5.8 6.2 6.6 mA max A Minimum Quiescent Current VS = ±5V 5.5 5.3 4.6 4.3 mA min A Input-Referred 75 68 66 64 dB min A -40 to +85 °C typ C xx x D xxxx x SO-8 125 °C/W typ C xx x DBV xxx SOT23-6 150 °C/W typ C Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specified Operating Range: D, DBV Thermal Resistance, qJA Junction-to-Ambient 4 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted. OPA690ID, IDBV MIN/MAX OVER TEMPERATURE TYP PARAMETER +25°C (2) 0°C to +70°C (3) -40°C to +85°C (3) 190 150 145 140 G = +10, VO < 0.5VPP 25 18 17 G ≥ 10 250 180 170 G = +2, VO < 0.5VPP 20 TEST CONDITIONS +25°C G = +1, VO = 0.5VPP, RF = ±25Ω 400 G = +2, VO < 0.5VPP MIN/ MAX TEST LEVELS (1) MHz typ C MHz min B 16 MHz min B 160 MHz min B MHz typ C UNIT AC PERFORMANCE (see Figure 37) Small-Signal Bandwidth Gain Bandwidth Product Bandwidth for 0.1dB Gain Flatness Peaking at a Gain of +1 VO < 0.5VPP 5 dB typ C Large-Signal Bandwidth G = +2, VO = 2VPP 220 MHz typ C G = +2, 2V Step 1000 V/ms min B G = +2, VO = 0.5V Step 1.6 ns typ C Slew Rate Rise-and-Fall Time 700 670 550 G = +2, VO = 2V Step 2.0 ns typ C Settling Time to 0.02% G = +2, VO = 2V Step 12 ns typ C Settling Time to 0.1% G = +2, VO = 2V Step 8 ns typ C Harmonic Distortion G = +2, f = 5MHz, VO = 2VPP xx x 2nd-Harmonic RL = 100Ω to VS/2 –65 –60 –59 –56 dBc max B RL ≥ 500Ω to VS/2 –75 –70 –68 –66 dBc max B RL = 100Ω to VS/2 –68 –64 –62 –60 dBc max B RL ≥ 500Ω to VS/2 –77 –73 –71 –70 dBc max B f > 1MHz 5.6 nV/√Hz typ C xx x 3rd-Harmonic Input Voltage Noise Input Current Noise f > 1MHz 3.2 pA/√Hz typ C Differential Gain G = +2, NTSC, VO = 1.4VP, RL = 150Ω to VS/2 0.06 % typ C Differential Phase G = +2, NTSC, VO = 1.4VP, RL = 150Ω to VS/2 0.02 deg typ C DC PERFORMANCE (4) Open-Loop Voltage Gain (AOL) VO = 2.5V, RL = 100Ω to VS/2 63 56 54 52 dB min A Input Offset Voltage VCM = 2.5V ±1.0 ±4 ±4.3 ±4.7 mV max A xxx Average Offset Voltage Drift VCM = 2.5V ±10 ±10 mV/°C max B Input Bias Current VCM = 2.5V ±11 ±12 mA max A xxx Average Bias Current Drift (magnitude) VCM = 2.5V ±20 ±40 nA/°C max B Input Offset Current VCM = 2.5V ±1.4 ±1.6 mA max A xxx Average Offset Current Drift VCM = 2.5V ±7 ±9 nA/°C max B ±3 ±0.3 ±10 ±1 INPUT Least Positive Input Voltage (5) 1.5 1.6 1.7 1.8 V min A Most Positive Input Voltage (5) 3.5 3.4 3.3 3.2 V min A 63 58 56 54 dB min A Common-Mode Rejection Ratio (CMRR) VCM = 2.5V ± 0.5V Input Impedance xxx Differential Mode VCM = 2.5V 92 || 1.4 kΩ || pF typ C xxx Common-Mode VCM = 2.5V 2.2 || 1.5 MΩ || pF typ C (1) (2) (3) (4) (5) Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. Junction temperature = ambient for +25°C specifications. Junction temperature = ambient at low temperature limits; junction temperature = ambient +10°C at high temperature limit for over temperature specifications. Current is considered positive out of node. Tested < 3dB below minimum specified CMRR at ±CMIR limits. 5 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +5V (continued) Boldface limits are tested at +25°C. At RF = 402Ω, RL = 100Ω, and G = +2 (see Figure 37 for ac performance only), unless otherwise noted. OPA690ID, IDBV MIN/MAX OVER TEMPERATURE TYP PARAMETER TEST CONDITIONS +25°C +25°C (2) 0°C to +70°C (3) -40°C to +85°C (3) UNIT MIN/ MAX TEST LEVELS (1) OUTPUT Most Positive Output Voltage No Load 4 3.8 3.6 3.5 V min A RL = 100Ω to 2.5V 3.9 3.7 3.5 3.4 V min A No Load 1 1.2 1.4 1.5 V min A RL = 100Ω to 2.5V 1.1 1.3 1.5 1.7 V max A Current Output, Sourcing +160 +120 +100 +80 mA max A Current Output, Sinking –160 –120 –100 –80 mA min A Short-Circuit Current ±250 mA typ C G = +2, f =100kHz 0.04 Ω typ C µA max A dB typ C Least Positive Output Voltage Closed-Loop Output Impedance DISABLE (Disabled LOW) Power-Down Supply Current (+VS) VDIS = 0V –100 G = +2, 5MHz 65 4 pF typ C Turn-On Glitch G = +2, RL = 150Ω, VIN = VS/2 ±50 mV typ C Turn-Off Glitch G = +2, RL = 150Ω, VIN = VS/2 ±20 mV typ C A Off Isolation Output Capacitance in Disable –200 –240 –260 Enable Voltage 3.3 3.5 3.6 3.7 V min Disable Voltage 1.8 1.7 1.6 1.5 V max A 75 130 150 160 µA typ C V typ C 12 12 12 V max B A Control Pin Input BIas Current (VDIS) VDIS = 0V POWER SUPPLY Specified Single-Supply Operating Voltage 5 Maximum Single-Supply Operating Voltage Maximum Quiescent Current VS = ±5V 4.9 5.44 5.72 6.02 mA max Minimum Quiescent Current VS = ±5V 4.9 4.48 4.0 3.86 mA min A Input-Referred 72 dB typ C –40 to +85 °C typ C xx x D xxxx x SO-8 125 °C/W typ C xx x DBV xxx SOT23-6 150 °C/W typ C Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specification: D, DBV Thermal Resistance, qJA Junction-to-Ambient 6 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted. SMALL−SIGNAL FREQUENCY RESPONSE 9 6 VO = 0.5VPP G = +1 RF = 25W 3 6 0 G=5 -3 -6 VO = 2VPP Gain (3dB/div) Normalized Gain (dB) LARGE−SIGNAL FREQUENCY RESPONSE G=2 G = 10 3 VO = 1VPP 0 VO = 4VPP -9 -3 -12 VO = 7VPP -6 0.5 -15 0.7 1 10 700 100 1 10 Frequency (MHz) Frequency (MHz) Figure 1. Figure 2. SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE G = +2 VO = 0.5VPP 300 G = +2 VO = 5VPP 3 200 Output Voltage (V) Output Voltage (mV) 500 4 400 100 0 -100 -200 2 1 0 -1 -2 -3 -300 -4 -400 Time (5ns/div) Time (5ns/div) 0.200 Figure 3. Figure 4. COMPOSITE VIDEO dG/dP DISABLE FEEDTHROUGH vs FREQUENCY +5V -50 402W Optional 1.3kW Pull- Down dG 402W 0.125 dG 0.100 VDIS = 0 -55 OPA690 0.150 Feedthrough (dB) 75W -45 No Pull- Down With 1.3kW Pull- Down Video In 0.175 dG/dP (%/degree) 100 -5V dP 0.075 0.050 dP -60 -65 -70 -75 -80 -85 -90 0.025 Reverse -95 0 1 2 3 4 -100 100k Number of 150W Loads Forward 1M 10M 100M Frequency (Hz) Figure 5. Figure 6. 7 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE -60 VO = 2VPP RL = 100W f = 5MHz VO = 2VPP f = 5MHz -65 Harmonic Distortion (dBc) Harmonic Distortion (dBc) -60 -70 2nd-Harmonic -75 3rd-Harmonic -80 -85 -65 2nd-Harmonic -70 3rd-Harmonic -75 -80 -90 2.0 1000 100 2.5 3.0 5.0 HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs OUTPUT VOLTAGE 5.5 6.0 -60 RL = 100W f = 5MHz -60 2nd-Harmonic -70 -80 3rd-Harmonic -90 2nd-Harmonic -65 -70 3rd-Harmonic -75 -80 -100 0.1 1 10 0.1 20 5 1 Output Voltage Swing (VPP) Frequency (MHz) Figure 9. Figure 10. HARMONIC DISTORTION vs NONINVERTING GAIN HARMONIC DISTORTION vs INVERTING GAIN -40 -40 VO = 2VPP RL = 100W f = 5MHz -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 4.5 Figure 8. VO = 2VPP RL = 100W -50 4.0 Figure 7. Harmonic Distortion (dBc) Harmonic Distortion (dBc) -40 3.5 Supply Voltage (±VS) Load Resistance (W) -60 2nd-Harmonic 3rd-Harmonic -70 -80 VO = 2VPP RL = 100W f = 5MHz RF = 1kW -50 -60 2nd-Harmonic 3rd-Harmonic -70 -80 -90 1 10 20 1 10 20 Inverting Gain (V/V) Noninverting Gain (V/V) Figure 11. Figure 12. 8 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted. INPUT VOLTAGE AND CURRENT NOISE DENSITY TWO−TONE, 3RD−ORDER INTERMODULATION SPURIOUS -30 -35 3rd-Order Spurious Level (dBc) Voltage Noise (nV/ÖHz) Current Noise (pA/ÖHz) 100 10 Voltage Noise 5.5nV/ÖHz Current Noise 3.1pA/ÖHz 50MHz -40 -45 -50 20MHz -55 -60 -65 10MHz Load Power at Matched 50W Load, see Figure 36 -70 1 -75 100 1k 10k 100k 1M 10M -8 -6 -4 Frequency (Hz) 0 -2 2 4 Figure 13. Figure 14. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 8 10 9 80 G = +2 Gain-to-Capacitive Load (dB) 70 60 RS ( W ) 6 Single-Tone Load Power (dBm) 50 40 30 20 10 CL = 10pF 6 CL = 100pF 3 CL = 22pF 0 CL = 47pF -3 VIN RS VOUT OPA690 1kW CL 402W -6 402W 1kW is optional. 0 -9 1000 100 0 80 100 120 140 160 180 200 LARGE-SIGNAL ENABLE/DISABLE RESPONSE ENABLE/DISABLE GLITCH 2.0 Output Voltage 1.6 Each Channel SO-14 Package Only 1.2 0.8 G = +2 VIN = +1V 4 VDIS 2 0 Output Voltage (10mV/div) 2 6 VDIS (2V/div) 4 0 Output Voltage (0.4V/div) 60 Figure 16. VDIS 0 40 Figure 15. 6 0.4 20 Frequency (20MHz/div) Capacitive Load (pF) VDIS (2V/div) 10 30 20 10 0 -10 Output Voltage VI = 0V -20 -30 Time (50ns/div) Time (20ns/div) Figure 17. Figure 18. 9 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted. OUTPUT VOLTAGE AND CURRENT LIMITATIONS 1 0 25W Load Line 50W Load Line -1 -2 100W Load Line -3 -200 0 -100 100 200 10 Input Offset Current (IOS) 0 0 -0.5 -10 -1.0 Input Offset Voltage (VOS) -1.5 -20 -2.0 -50 300 0 -25 25 50 100 Figure 19. Figure 20. COMMON−MODE REJECTION RATIO AND POWER−SUPPLY REJECTION RATIO vs FREQUENCY SUPPLY AND OUTPUT CURRENTS vs TEMPERATURE 100 8 250 Sourcing Output Current -PSRR 90 80 7 CMRR 70 Supply Current (mA) Power-Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 125 Ambient Temperature (°C) IO (mA) 60 +PSRR 50 40 30 20 200 Sinking Output Current 6 150 5 100 Quiescent Supply Current 4 50 10 0 3 10k 100k 1M 100M 10M -50 -25 Frequency (MHz) 0 25 50 75 Figure 22. CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY OPEN−LOOP GAIN AND PHASE 0 60 OPA690 Open-Loop Gain (dB) 200W ZO -5V 402W 402W 0.1 0.01 100k 1M 10M 100M -30 Open-Loop Gain 50 -60 Open-Loop Phase 40 -90 30 -120 20 -150 10 -180 0 -210 -10 -240 -20 10k 0 125 70 +5V 1 100 Ambient Temperature (°C) Figure 21. 10 Output Impedance ( W ) 75 Output Current (mA) -5 -300 0.5 1W Internal Power Limit Output Current Limit Input Bias Current (IB) 1.0 1k Frequency (Hz) 10k 100k 1M 10M 100M Open-Loop Phase (°) VO (V) 2 -4 20 1.5 3 Input Offset Voltage (mV) 4 2.0 Output Current Limited 1W Internal Power Limit Input Bias and Offset Currents (mA) 5 TYPICAL DC DRIFT OVER TEMPERATURE -270 1G Frequency (Hz) Figure 23. Figure 24. 10 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 36 for ac performance only), unless otherwise noted. 5 10 4 8 3 6 2 4 1 Output Voltage 2 0 0 -1 -2 -2 -4 -3 -4 Input Voltage -5 Output Voltage (V) Input Voltage (V) NONINVERTING OVERDRIVE RECOVERY -6 -8 -10 Time (10ns/div) Figure 25. 11 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS: +5V At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 37 for ac performance only), unless otherwise noted. SMALL−SIGNAL FREQUENCY RESPONSE 6 LARGE−SIGNAL FREQUENCY RESPONSE 9 VO = 0.5VPP 3 6 VO = 3VPP G = +2 0 3 G = +5 Gain (dB) Normalized Gain (dB) VO = 2VPP G = +1 RF = 25W -3 VO = 1VPP 0 G = +10 -6 -3 -9 -6 0.7 1 100 10 700 0.5 1 Figure 26. Figure 27. SMALL-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE 4.1 G = +2 VO = 0.5VPP 2.8 Output Voltage (mV) 2.7 2.6 2.5 2.4 2.3 G = +2 VO = 2VPP 3.7 2.2 3.3 2.9 2.5 2.1 1.7 1.3 2.1 0.9 Time (5ns/div) Time (5ns/div) Figure 28. Figure 29. RECOMMENDED RS vs CAPACITIVE LOAD FREQUENCY RESPONSE vs CAPACITIVE LOAD 9 50 CL = 10pF Gain-to-Capacitive Load (dB) 45 40 35 RS ( W ) 500 Frequency (MHz) 2.9 Output Voltage (mV) 100 10 Frequency (Hz) 30 25 20 15 10 6 CL = 100pF 3 0 CL = 22pF +5V -3 0.1mF 714W VIN RS 58W 714W 714W OPA690 VOUT CL = 47pF CL -6 402W +5V 5 402W -9 0 1 10 100 1000 0 20 40 60 80 100 120 140 160 180 200 Frequency (20MHz/div) Capacitive Load (pF) Figure 30. Figure 31. 12 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS: +5V (continued) At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω (see Figure 37 for ac performance only), unless otherwise noted. HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY -40 -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) VO = 2VPP f = 5MHz -65 -70 2nd-Harmonic 3rd-Harmonic -75 -50 VO = 2VPP RL = 100W to 2.5V -60 2nd-Harmonic -70 -80 3rd-Harmonic -90 -100 -80 1000 100 0.1 1 Figure 32. Figure 33. HARMONIC DISTORTION vs OUTPUT VOLTAGE TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS -60 20 -30 -65 3rd-Order Spurious Level (dBc) RL = 100W to 2.5V f = 5MHz Harmonic Distortion (dBc) 10 Frequency (MHz) Resistance ( W ) 3rd-Harmonic -70 2nd-Harmonic -75 -35 50MHz -40 -45 -50 20MHz -55 -60 -65 10MHz -70 Load Power at Matched 50W Load, see Figure 37 -80 -75 0.1 1 3 -14 Output Voltage Swing (VPP) -12 -10 -8 -6 -4 -2 0 2 Single-Tone Load Power (dBm) Figure 34. Figure 35. 13 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com APPLICATION INFORMATION WIDEBAND VOLTAGE-FEEDBACK OPERATION The OPA690 provides an exceptional combination of high output power capability with a wideband, unity-gain stable voltage-feedback op amp using a new high slew rate input stage. Typical differential input stages used for voltage feedback op amps are designed to steer a fixed-bias current to the compensation capacitor, setting a limit to the achievable slew rate. The OPA690 uses a new input stage which places the transconductance element between two input buffers, using their output currents as the forward signal. As the error voltage increases across the two inputs, an increasing current is delivered to the compensation capacitor. This provides very high slew rate (1800V/ms) while consuming relatively low quiescent current (5.5mA). This exceptional full-power performance comes at the price of a slightly higher input noise voltage than alternative architectures. The 5.5nV/√Hz input voltage noise for the OPA690 is exceptionally low for this type of input stage. Figure 36 shows the dc-coupled, gain of +2, dual power supply circuit configuration used as the basis of the ±5V Electrical Characteristics and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins, while output powers (dBm) are at the matched 50Ω load. For the circuit of Figure 36, the total effective load will be 100Ω || 804Ω. The disable control line is typically left open to ensure normal amplifier operation. Two optional components are included in Figure 36. An additional resistor (175Ω) is included in series with the noninverting input. Combined with the 25Ω dc source resistance looking back towards the signal generator, this gives an input bias current cancelling resistance that matches the 200Ω source resistance seen at the inverting input (see the DC Accuracy and Offset Control section). In addition to the usual power-supply decoupling capacitors to ground, a 0.1mF capacitor is included between the two power-supply pins. In practical printed circuit board (PCB) layouts, this optional-added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. Figure 37 shows the ac-coupled, gain of +2, single-supply circuit configuration which is the basis of the +5V Electrical Characteristics and Typical Characteristics. Though not a rail-to-rail design, the OPA690 requires minimal input and output voltage headroom compared to other very wideband voltage-feedback op amps. It will deliver a 3VPP output swing on a single +5V supply with > 150MHz bandwidth. The key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. The circuit of Figure 37 establishes an input midpoint bias using a simple resistive divider from the +5V supply (two 698Ω resistors). The input signal is then ac-coupled into the midpoint voltage bias. The input voltage can swing to within 1.5V of either supply pin, giving a 2VPP input signal range centered between the supply pins. The input impedance matching resistor (59Ω) used for testing is adjusted to give a 50Ω input load when the parallel combination of the biasing divider network is included. +5V 0.1mF 50W Source VI 6.8mF + 175W DIS VO 50W 50W 50W Load OPA690 0.1mF RF 402W RG 402W + 6.8mF 0.1mF -5V Figure 36. DC-Coupled, G = +2, Bipolar-Supply Specification and Test Circuit +5V +VS + 0.1mF 50W Source 0.1mF VI 59W 6.8mF 698W 50W 698W DIS VO OPA690 100W VS/2 RF 402W RG 402W 0.1mF Figure 37. AC-Coupled, G = +2, Single-Supply Specification and Test Circuit 14 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 Again, an additional resistor (50Ω in this case) is included directly in series with the noninverting input. This minimum recommended value provides part of the dc source resistance matching for the noninverting input bias current. It is also used to form a simple parasitic pole to roll off the frequency response at very high frequencies ( > 500MHz) using the input parasitic capacitance to form a bandlimiting pole. The gain resistor (RG) is ac-coupled, giving the circuit a dc gain of +1, which puts the input dc bias voltage (2.5V) at the output as well. The output voltage can swing to within 1V of either supply pin while delivering > 100mA output current. A demanding 100Ω load to a midpoint bias is used in this characterization circuit. The new output stage circuit used in the OPA690 can deliver large bipolar output currents into this midpoint load with minimal crossover distortion, as shown in the +5V supply, 3rd-harmonic distortion plots. The OPA690 in the circuit of Figure 39 provides > 200MHz bandwidth for a 2VPP output swing. Minimal 3rd-harmonic distortion or two-tone, 3rd-order intermodulation distortion will be observed due to the very low crossover distortion in the OPA690 output stage. The limit of output Spurious-Free Dynamic Range (SFDR) will be set by the 2nd-harmonic distortion. Without RB, the circuit of Figure 39 measured at 10MHz shows an SFDR of 57dBc. This may be improved by pulling additional dc bias current (IB) out of the output stage through the optional RB resistor to ground (the output midpoint is at 2.5V for Figure 39). Adjusting IB gives the improvement in SFDR shown in Figure 38. SFDR improvement is achieved for IB values up to 5mA, with worse performance for higher values. 70 VO = 2VPP, 10MHz 68 66 SINGLE-SUPPLY ADC INTERFACE SFDR (dBc) 64 Most modern, high performance ADCs (such as the TI ADS8xx and ADS9xx series) operate on a single +5V (or lower) power supply. It has been a considerable challenge for single-supply op amps to deliver a low distortion input signal at the ADC input for signal frequencies exceeding 5MHz. The high slew rate, exceptional output swing, and high linearity of the OPA690 make it an ideal single-supply ADC driver. The circuit on the front page shows one possible (inverting) interface. Figure 39 shows the test circuit of Figure 37 modified for a capacitive (ADC) load and with an optional output pull-down resistor (RB). 62 60 58 56 54 52 50 0 1 2 3 4 5 6 7 8 9 10 Output Pull-Down Current (mA) Figure 38. SFDR vs IB +5V Power- supply decoupling not shown. 698W DIS 0.1mF 50W RS 30W VI 1VPP 2.5V DC ±1V AC OPA690 59W 698W 50pF ADC Input 402W 402W RB 0.1mF IB Figure 39. SFDR versus IB Test Circuit 15 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com HIGH-PERFORMANCE DAC TRANSIMPEDANCE AMPLIFIER The 5pF capacitor in the feedback loop provides added bandwidth control for the signal path. High-frequency, direct digital synthesis (DDS) Digital-to-Analog Converters (DACs) require a low distortion output amplifier to retain their SFDR performance into real-world loads. See Figure 40 for a single-ended output drive implementation. In this circuit, only one side of the complementary output drive signal is used. The diagram shows the signal output current connected into the virtual ground summing junction of the OPA690, which is set up as a transimpedance stage or I-V converter. The unused current output of the DAC is connected to ground. If the DAC requires that its outputs terminate to a compliance voltage other than ground for operation, the appropriate voltage level may be applied to the noninverting input of the OPA690. The dc gain for this circuit is equal to RF. At high frequencies, the DAC output capacitance will produce a zero in the noise gain for the OPA690 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise gain peaking. To achieve a flat transimpedance frequency response, the pole in the feedback network should be set to: 1 = 2pRFCF GBP 4pRFCD which will give a closed-loop bandwidth, f−3dB, of approximately: f-3dB = GBP 2pRFCD 50W OPA690 High-Speed DAC VO = IO RF RF CF CD IO IO Figure 40. DAC Transimpedance Amplifier +12V (1) 2kW transimpedance 8VPP 50W 4VPP OPA690 0.1mF 2kW 50W Load (2) Where GBP = gain bandwidth product (Hz) for the OPA690. HIGH-POWER LINE DRIVER The large output swing capability of the OPA690 and its high current capability allow it to drive a 50Ω line with a peak-to-peak signal up to 4VPP at the load, or 8VPP at the output of the amplifier using a single 12V supply. Figure 41 shows such a circuit set for a gain of 8 to the output or 4 to the load. 1VPP 50W Source 50W 400W 5pF Figure 41. High-Power Coax Line Driver 16 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 SINGLE-SUPPLY ACTIVE FILTERS The high bandwidth provided by the OPA690, while operating on a single +5V supply, lends itself well to high-frequency active filter designs. Again, the key additional requirement is to establish the dc operating point of the signal near the supply midpoint for highest dynamic range. See Figure 42 for an example design of a 5MHz low-pass Butterworth filter using the Sallen-Key topology. Both the input signal and the gain setting resistor are ac-coupled using 0.1mF blocking capacitors (actually giving bandpass response with the low-frequency pole set to 32kHz for the component values shown). As discussed for Figure 37, this allows the midpoint bias formed by the two 1.87kΩ resistors to appear at both the input and output pins. The midband signal gain is set to +4 (12dB) in this case. The capacitor to ground on the noninverting input is intentionally set larger to dominate input parasitic terms. At a gain of +4, the OPA690 on a single supply will show ~80MHz small- and large-signal bandwidth. The resistor values have been slightly adjusted to account for this limited bandwidth in the amplifier stage. Tests of this circuit show a precise 5MHz, −3dB point with a maximally flat passband (above the 32kHz ac-coupling corner), and a maximum stop band attenuation of 36dB at the amplifier’s −3dB bandwidth of 80MHz. +5V 5MHz, 2nd-Order Butterworth Filter Response 15 1.87kW 100pF 10 137W DIS 432W VI 4VI OPA690 1.87kW 150pF 5MHz, 2nd-Order Butterworth Filter Gain (dB) 0.1mF 5 0 1.5kW -5 100k 500W 1M 10M Frequency (Hz) 0.1mF Figure 42. Single-Supply, High-Frequency Active Filter 17 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com DESIGN-IN TOOLS DEMONSTRATION FIXTURES Two printed circuit boards (PCBs) are available to assist in the initial evaluation of circuit performance using the OPA690 in its two package options. Both of these are offered free of charge as unpopulated PCBs, delivered with a user’s guide. The summary information for these fixtures is shown in Table 1. Table 1. Demonstration Fixtures by Package PRODUCT PACKAGE ORDERING NUMBER LITERATURE NUMBER OPA690ID SO-8 DEM-OPA-SO-1A SBOU009 OPA690IDBV SOT23-6 DEM-OPA-SOT-1A SBOU010 The demonstration fixtures can be requested at the Texas Instruments web site (www.ti.com) through the OPA690 product folder. MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the OPA690 is available through the OPA690 product folder under Simulation Models. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between the package types in their small-signal ac performance. 18 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 OPERATING SUGGESTIONS OPTIMIZING RESISTOR VALUES Since the OPA690 is a unity-gain stable, voltage-feedback op amp, a wide range of resistor values may be used for the feedback and gain setting resistors. The primary limits on these values are set by dynamic range (noise and distortion) and parasitic capacitance considerations. For a noninverting unity-gain follower application, the feedback connection should be made with a 25Ω resistor, not a direct short. This will isolate the inverting input capacitance from the output pin and improve the frequency response flatness. Usually, for G > 1 applications, the feedback resistor value should be between 200Ω and 1.5kΩ. Below 200Ω, the feedback network will present additional output loading which can degrade the harmonic distortion performance of the OPA690. Above 1.5kΩ, the typical parasitic capacitance (approximately 0.2pF) across the feedback resistor may cause unintentional band-limiting in the amplifier response. A good rule of thumb is to target the parallel combination of RF and RG (see Figure 36) to be less than approximately 300Ω. The combined impedance RF || RG interacts with the inverting input capacitance, placing an additional pole in the feedback network and thus, a zero in the forward response. Assuming a 2pF total parasitic on the inverting node, holding RF || RG < 300Ω will keep this pole above 250MHz. By itself, this constraint implies that the feedback resistor RF can increase to several kΩ at high gains. This is acceptable as long as the pole formed by RF and any parasitic capacitance appearing in parallel is kept out of the frequency range of interest. BANDWIDTH VERSUS GAIN: NONINVERTING OPERATION Voltage-feedback op amps exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the Gain Bandwidth Product (GBP) shown in the Electrical Characteristics. Ideally, dividing GBP by the noninverting signal gain (also called the Noise Gain, or NG) will predict the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high gain configurations. At low gains (increased feedback factors), most amplifiers will exhibit a more complex response with lower phase margin. The OPA690 is compensated to give a slightly peaked response in a noninverting gain of 2 (see Figure 36). This results in a typical gain of +2 bandwidth of 220MHz, far exceeding that predicted by dividing the 300MHz GBP by 2. Increasing the gain will cause the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +10, the 30MHz bandwidth shown in the Electrical Characteristics agrees with that predicted using the simple formula and the typical GBP of 300MHz. The frequency response in a gain of +2 may be modified to achieve exceptional flatness simply by increasing the noise gain to 2.5. One way to do this, without affecting the +2 signal gain, is to add an 804Ω resistor across the two inputs in the circuit of Figure 36. A similar technique may be used to reduce peaking in unity-gain (voltage follower) applications. For example, by using a 402Ω feedback resistor along with a 402Ω resistor across the two op amp inputs, the voltage follower response will be similar to the gain of +2 response of Figure 37. Reducing the value of the resistor across the op amp inputs will further limit the frequency response due to increased noise gain. The OPA690 exhibits minimal bandwidth reduction going to single-supply (+5V) operation as compared with ±5V. This is because the internal bias control circuitry retains nearly constant quiescent current as the total supply voltage between the supply pins is changed. 19 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com INVERTING AMPLIFIER OPERATION Since the OPA690 is a general-purpose, wideband voltage-feedback op amp, all of the familiar op amp application circuits are available to the designer. Inverting operation is one of the more common requirements and offers several performance benefits. Figure 43 shows a typical inverting configuration where the I/O impedances and signal gain from Figure 36 are retained in an inverting circuit configuration. +5V + 0.1mF 6.8mF 0.1mF DIS RB 146W 50W Source RO 50W OPA690 50W Load RG 200W RF 402W RM 67W 0.1mF + 6.8mF -5V Figure 43. Gain of –2 Example Circuit In the inverting configuration, three key design considerations must be noted. The first is that the gain resistor (RG) becomes part of the signal channel input impedance. If input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted-pair, long PCB trace, or other transmission line conductor), RG may be set equal to the required termination value and RF adjusted to give the desired gain. This is the simplest approach and results in optimum bandwidth and noise performance. However, at low inverting gains, the resultant feedback resistor value can present a significant load to the amplifier output. For an inverting gain of 2, setting RG to 50Ω for input matching eliminates the need for RM but requires a 100Ω feedback resistor. This has the interesting advantage that the noise gain becomes equal to 2 for a 50Ω source impedance—the same as the noninverting circuits considered in the previous section. The amplifier output, however, will now see the 100Ω feedback resistor in parallel with the external load. In general, the feedback resistor should be limited to the 200Ω to 1.5kΩ range. In this case, it is preferable to increase both the RF and RG values, as shown in Figure 43, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance becomes the parallel combination of RG and RM. The second major consideration, touched on in the previous paragraph, is that the signal source impedance becomes part of the noise gain equation and influences the bandwidth. For the example in Figure 43, the RM value combines in parallel with the external 50Ω source impedance, yielding an effective driving impedance of 50Ω || 67Ω = 28.6Ω. This impedance is added in series with RG for calculating the noise gain (NG). The resultant NG is 2.8 for Figure 43, as opposed to only 2 if RM could be eliminated as discussed above. The bandwidth will therefore be slightly lower for the gain of ±2 circuit of Figure 43 than for the gain of +2 circuit of Figure 36. The third important consideration in inverting amplifier design is setting the bias current cancellation resistor on the noninverting input (RB). If this resistor is set equal to the total dc resistance looking out of the inverting node, the output dc error, due to the input bias currents, will be reduced to (Input Offset Current) × RF. If the 50Ω source impedance is dc-coupled in Figure 43, the total resistance to ground on the inverting input will be 228Ω. Combining this in parallel with the feedback resistor gives the RB = 146Ω used in this example. To reduce the additional high-frequency noise introduced by this resistor, it is sometimes bypassed with a capacitor. As long as RB < 350Ω, the capacitor is not required because the total noise contribution of all other terms will be less than that of the op amp input noise voltage. As a minimum, the OPA690 requires an RB value of 50Ω to damp out parasitic-induced peaking—a direct short to ground on the noninverting input runs the risk of a very high-frequency instability in the input stage. 20 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 OUTPUT CURRENT AND VOLTAGE The OPA690 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic op amp. Under no-load conditions at +25°C, the output voltage typically swings closer than 1V to either supply rail; the specified swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it will deliver more than ±160mA. The specifications described previously, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit operation. Refer to Figure 19, the Output Voltage and Current Limitations plot in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the OPA690 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the OPA690 can drive ±2.5V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. A 100Ω load line (the standard test circuit load) shows the full ±3.9V output swing capability, as shown in the typical specifications. The minimum specified output voltage and current specifications over temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, their junction temperatures increase, decreasing their VBEs (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). In steady-state operation, the available output voltage and current is always greater than that shown in the over-temperature specifications because the output stage junction temperatures will be higher than the minimum specified operating ambient. OPA690 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier's open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series-isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. The Typical Characteristics show the recommended RS versus capacitive load (Figure 15 for ±5V and Figure 30 for +5V) and the resulting frequency response at the load. Parasitic capacitive loads greater than 2pF can begin to degrade the performance of the OPA690. Long PCB traces, unmatched cables, and connections to multiple devices can easily exceed this value. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA690 output pin (see the Board Layout Guidelines section). The criterion for setting this RS resistor is a maximum bandwidth, flat frequency response at the load. For the OPA690 operating in a gain of +2, the frequency response at the output pin is already slightly peaked without the capacitive load requiring relatively high values of RS to flatten the response at the load. Increasing the noise gain will reduce the peaking as described previously. The circuit of Figure 44 demonstrates this technique, allowing lower values of RS to be used for a given capacitive load. +5V 50W To protect the output stage from accidental shorts to ground and the power supplies, output short-circuit protection is included in the OPA690. The circuit acts to limit the maximum source or sink current to approximately 250mA. 175W 50W RNG Power-supply decoupling not shown. R VO OPA690 402W CL DRIVING CAPACITIVE LOADS One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve ADC linearity. A high-speed, high open-loop gain amplifier like the 402W -5V Figure 44. Capacitive Load Driving with Noise Gain Tuning 21 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com This gain of +2 circuit includes a noise gain tuning resistor across the two inputs to increase the noise gain, increasing the unloaded phase margin for the op amp. Although this technique will reduce the required RS resistor for a given capacitive load, it does increase the noise at the output. It also will decrease the loop gain, slightly decreasing the distortion performance. If, however, the dominant distortion mechanism arises from a high RS value, significant dynamic range improvement can be achieved using this technique. Figure 45 shows the required RS versus CLOAD parametric on noise gain using this technique. This is the circuit of Figure 44 with RNG adjusted to increase the noise gain (increasing the phase margin) then sweeping CLOAD and finding the required RS to get a flat frequency response. This plot also gives the required RS versus CLOAD for the OPA690 operated at higher signal gains. 100 90 80 RS (W) 70 NG = 2 In most op amps, increasing the output voltage swing increases harmonic distortion directly. The new output stage used in the OPA690 actually holds the difference between fundamental power and the 2ndand 3rd-harmonic powers relatively constant with increasing output power until very large output swings are required ( > 4VPP). This also shows up in the 2-tone, 3rd-order intermodulation spurious (IM3) response curves. The 3rd-order spurious levels are moderately low at low output power levels. The output stage continues to hold them low even as the fundamental power reaches very high levels. As the Typical Characteristics show, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 20MHz, with 10dBm/tone into a matched 50Ω load (that is, 2VPP for each tone at the load, which requires 8VPP for the overall two-tone envelope at the output pin), the Typical Characteristics show 47dBc difference between the test tone powers and the 3rd-order intermodulation spurious powers. This performance improves further when operating at lower frequencies. 60 50 NOISE PERFORMANCE 40 30 20 NG = 3 10 NG = 4 0 1 10 100 1000 Capacitive Load (pF) Figure 45. Required RS vs Noise Gain DISTORTION PERFORMANCE The OPA690 provides good distortion performance into a 100Ω load on ±5V supplies. Relative to alternative solutions, it provides exceptional performance into lighter loads and/or operating on a single +5V supply. Generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic dominates the distortion with a negligible 3rd-harmonic component. Focusing then on the 2nd-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network; in the noninverting configuration (see Figure 36), this is sum of RF + RG, while in the inverting configuration it is just RF. Also, providing an additional supply-decoupling capacitor (0.1µF) between the supply pins (for bipolar operation) improves the 2nd-order distortion slightly (3dB to 6dB). High slew rate, unity-gain stable, voltage-feedback op amps usually achieve their slew rate at the expense of a higher input noise voltage. The 5.5nV/√Hz input voltage noise for the OPA690 is, however, much lower than comparable amplifiers. The input-referred voltage noise, and the two input-referred current noise terms, combine to give low output noise under a wide variety of operating conditions. Figure 46 shows the op amp noise analysis model with all the noise terms included. In this model, all noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz. ENI OPA690 RS EO IBN ERS RF Ö4kTRS 4kT RG RG IBI Ö4kTRF 4kT = 1.6E - 20J at 290°K Figure 46. Op Amp Noise Analysis Model 22 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 The total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. Equation 3 shows the general form for the output noise voltage using the terms shown in Figure 46. EO = ENI2 + (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG (3) Dividing this expression by the noise gain [NG = (1 + RF/RG)] will give the equivalent input-referred spot noise voltage at the noninverting input, as shown in Equation 4. EN = ENI2 + (IBNRS)2 + 4kTRS + IBIRF NG 2 + 4kTRF NG (4) Evaluating these two equations for the OPA690 circuit and component values (see Figure 36) gives a total output spot noise voltage of 12.3nV/√Hz and a total equivalent input spot noise voltage of 6.1nV/√Hz. This is including the noise added by the bias current cancellation resistor (175Ω) on the noninverting input. This total input-referred spot noise voltage is only slightly higher than the 5.5nV/√Hz specification for the op amp voltage noise alone. This will be the case as long as the impedances appearing at each op amp input are limited to the previously recommend maximum value of 300Ω. Keeping both (RF || RG) and the noninverting input source impedance less than 300Ω will satisfy both noise and frequency response flatness considerations. Since the resistor-induced noise is relatively negligible, additional capacitive decoupling across the bias current cancellation resistor (RB) for the inverting op amp configuration of Figure 43 is not required. –(NG = noninverting signal gain) ±(NG × VOS(MAX)) ± (RF × IOS(MAX)) = ±(2 × 4mV) ± (402Ω × 1mA) = ±8.4mV A fine-scale output offset null, or dc operating point adjustment, is often required. Numerous techniques are available for introducing dc offset control into an op amp circuit. Most of these techniques eventually reduce to adding a dc current through the feedback resistor. In selecting an offset trim method, one key consideration is the impact on the desired signal path frequency response. If the signal path is intended to be noninverting, the offset control is best applied as an inverting summing signal to avoid interaction with the signal source. If the signal path is intended to be inverting, applying the offset control to the noninverting input may be considered. However, the dc offset voltage on the summing junction will set up a dc current back into the source that must be considered. Applying an offset adjustment to the inverting op amp input can change the noise gain and frequency response flatness. For a dc-coupled inverting amplifier, see Figure 47 for one example of an offset adjustment technique that has minimal impact on the signal frequency response. In this case, the dc offsetting current is brought into the inverting input node through resistor values that are much larger than the signal path resistors. This ensures that the adjustment circuit has minimal effect on the loop gain and hence, the frequency response. +5V Power-supply decoupling not shown. OPA690 VO 328W 0.1mF DC ACCURACY AND OFFSET CONTROL The balanced input stage of a wideband voltage-feedback op amp allows good output dc accuracy in a wide variety of applications. The power-supply current trim for the OPA690 gives even tighter control than comparable amplifiers. Although the high-speed input stage does require relatively high input bias current (typically ±8µA at each input terminal), the close matching between them may be used to reduce the output dc error caused by this current. The total output offset voltage may be considerably reduced by matching the dc source resistances appearing at the two inputs. This reduces the output dc error due to the input bias currents to the offset current times the feedback resistor. Evaluating the configuration of Figure 36, and using worst-case +25°C input offset voltage and current specifications, gives a worst-case output offset voltage equal to: BLANKSPACE BLANKSPACE -5V RG 500W +5V 5kW RF 1kW VI 20kW ±200mV Output Adjustment 10kW 0.1mF 5kW VO VI =- RF RG = -2 -5V Figure 47. DC-Coupled, Inverting Gain of -2, with Offset Adjustment 23 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 DISABLE OPERATION The OPA690 provides an optional disable feature that may be used either to reduce system power or to implement a simple channel multiplexing operation. If the DIS control pin is left unconnected, the OPA690 will operate normally. To disable, the control pin must be asserted LOW. Figure 48 shows a simplified internal circuit for the disable control feature. +VS IS Control -VS Figure 48. Simplified Disable Control Circuit In normal operation, base current to Q1 is provided through the 110kΩ resistor, while the emitter current through the 15kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1's emitter. As VDIS is pulled LOW, additional current is pulled through the 15kΩ resistor, eventually turning on those two diodes (≈75µA). At this point, any further current pulled out of VDIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 48. Additional circuitry ensures that turn-on time occurs faster than turn-off time (make-before-break). When disabled, the output and input nodes go to a high-impedance state. If the OPA690 is operating at a 6 4 VDIS 2 0 VDIS (2V/div) 110kW The transition edge rate (dV/dt) of the DIS control line will influence this glitch. For the plot of Figure 49, the edge rate was reduced until no further reduction in glitch amplitude was observed. This approximately 1V/ns maximum slew rate may be achieved by adding a simple RC filter into the DIS pin from a higher speed logic line. If extremely fast transition logic is used, a 1kΩ series resistor between the logic gate and the DIS input pin provides adequate bandlimiting using just the parasitic input capacitance on the DIS pin while still ensuring adequate logic level swing. Output Voltage (10mV/div) Q1 VDIS gain of +1, this will show a very high impedance at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) and the isolation will be very poor as a result. One key parameter in disable operation is the output glitch when switching in and out of the disabled mode. Figure 49 shows these glitches for the circuit of Figure 36 with the input signal at 0V. The glitch waveform at the output pin is plotted along with the DIS pin voltage. 15kW 25kW www.ti.com 30 20 10 Output Voltage 0 VI = 0V -10 -20 -30 Time (20ns/div) Figure 49. Disable/Enable Glitch 24 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 THERMAL ANALYSIS Due to the high output power capability of the OPA690, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 175°C. Operating junction temperature (TJ) is given by TA + PD × qJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL) where RL includes feedback network loading. As a worst-case example, compute the maximum TJ using an OPA690IDBV (SOT23-6 package) in the circuit of Figure 36 operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load. PD = 10V × 6.2mA + 52/(4 × (20Ω || 804Ω)) = 382mW Maximum TJ = +85°C + (0.38W × 150°C/W) = 142°C. Although this is still well below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. Figure 19, the output V-I plot shown in the ±5V Typical Characteristics, include a boundary for 1W maximum internal power dissipation under these conditions. Note that it is the power in the output stage and not into the load that determines internal power dissipation. 25 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the OPA690 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1mF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1mF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2mF to 6.8mF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB. c. Careful selection and placement of external components will preserve the high-frequency performance of the OPA690. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PCB traces as short as possible. Never use wirewound type resistors in a high-frequency application. Since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can affect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 402Ω feedback used in the Electrical Characteristics is a good starting point for design. Note that a 25Ω feedback resistor, rather than a direct short, is suggested for the unity-gain follower application. This effectively isolates the inverting input capacitance from the output pin that would otherwise cause an additional peaking in the gain of +1 frequency response. d. Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils or 1,27mm to 100mils or 2,54mm) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS from the plot of Recommended RS vs Capacitive Load (Figure 15 for ±5V and Figure 30 for +5V). Low parasitic capacitive loads (< 5pF) may not need an RS because the OPA690 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA690 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. The high output voltage and current capability of the OPA690 allows multiple 26 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 www.ti.com SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of Recommended RS vs Capacitive Load (Figure 15 for ±5V and Figure 30 for +5V). This will not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. e. Socketing a high-speed part like the OPA690 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the OPA690 onto the board. INPUT AND ESD PROTECTION The OPA690 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies, as shown in Figure 50. +VCC External Pin Internal Circuitry -VCC Figure 50. Internal ESD Protection These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (e.g., in systems with ±15V supply parts driving into the OPA690), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. 27 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 OPA690 SBOS223F – DECEMBER 2001 – REVISED FEBRUARY 2010 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (November 2008) to Revision F Page • Changed data sheet format to current standards ................................................................................................................. 1 • Deleted Lead Temperature specification from Absolute Maximum Ratings table ................................................................ 2 • Added Figure 25, Noninverting Overdrive Recovery plot ................................................................................................... 11 Changes from Revision D (August 2008) to Revision E • Page Deleted obsolete OPA680 from Related Products table ...................................................................................................... 1 28 Copyright © 2001–2010, Texas Instruments Incorporated Product Folder Link(s): OPA690 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) OPA690ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 OPA690IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI OPA690IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI OPA690IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI OPA690IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OAEI OPA690IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 OPA690IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 OPA690IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA 690 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) OPA690IDBVR SOT-23 DBV 6 3000 180.0 OPA690IDBVT SOT-23 DBV 6 250 OPA690IDR SOIC D 8 2500 B0 (mm) K0 (mm) P1 (mm) 8.4 3.2 3.1 1.39 4.0 180.0 8.4 3.2 3.1 1.39 330.0 12.4 6.4 5.2 2.1 Pack Materials-Page 1 W Pin1 (mm) Quadrant 8.0 Q3 4.0 8.0 Q3 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA690IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 OPA690IDBVT SOT-23 DBV 6 250 210.0 185.0 35.0 OPA690IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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