ON NBSG16MMN 2.5v/3.3v multilevel input to cml clock/data receiver/driver/translator buffer Datasheet

NBSG16M
2.5V/3.3VMultilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
Inputs incorporate internal 50 termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50 source termination resistor to VCC. The device
generates 400 mV output amplitude with 50 receiver resistor to
VCC.
The VBB pin is internally generated voltage supply available to this
device only. For all single−ended input conditions, the unused
complementary differential input is connected to VBB as a switching
reference voltage. VBB may also rebias AC coupled inputs. When
used, decouple VBB via a 0.01 F capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB output should be left open.
• Maximum Input Clock Frequency > 10 GHz Typical
•
•
•
•
•
•
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MARKING
DIAGRAM*
A
L
Y
W
120 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Positive CML Output with Operating Range: VCC = 2.375 V to
3.465 V with VEE = 0 V
Negative CML Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = −2.375 V to −3.465 V
CML Output Level; 400 mV Peak−to−Peak Output with
50 Receiver Resistor to VCC
50 Internal Input and Output Termination Resistors
= Assembly Location
= Wafer Lot
= Year
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Package
Shipping†
NBSG16MMN
3x3 mm
QFN−16
123 Units / Rail
NBSG16MMNR2
3x3 mm
QFN−16
3000/Tape & Reel
Device
Maximum Input Data Rate > 10 Gb/s Typical
SG
16M
ALYW
QFN−16
MN SUFFIX
CASE 485G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
•
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
• VBB Reference Voltage Output
 Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 3
1
Publication Order Number:
NBSG16M/D
NBSG16M
VCC VBB
16
VTD
1
D
2
VEE
VEE
14
13
15
Exposed Pad (EP)
12
VCC
11
Q
NBSG16M
D
3
10
Q
VTD
4
9
VCC
5
6
7
8
VCC
NC
VEE
VEE
Figure 1. QFN−16 Pinout (Top View)
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
Table 1. PIN DESCRIPTION
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pin
Name
I/O
Description
1
VTD
−
2
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
Inverted Differential Input (Note 3)
3
D
LVDS, CML, ECL, LVTTL,
LVCMOS Input
Noninverted Differential Input. (Note 3)
4
VTD
−
Internal 50 Termination Pin. See Table 2. (Note 3)
5
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation.
6
NC
−
No Connect (Note 1)
7
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation.
8
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation.
9
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation.
10
Q
CML Output
Noninverted CML Differential Output with Internal 50 Source Termination Resistor. (Note 2)
11
Q
CML Output
Inverted CML Differential Output with Internal 50 Source Termination Resistor. (Note 2)
12
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation.
13
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation.
14
VEE
−
Negative Supply Voltage. All VEE pins must be externally connected to Power Supply to guarantee proper operation.
15
VBB
−
Internally Generated ECL Reference Output Voltage
16
VCC
−
Positive Supply Voltage. All VCC pins must be externally connected to Power Supply to guarantee proper operation.
−
EP
−
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must
be attached to a heat−sinking conduit.
Internal 50 Termination Pin. See Table 2. (Note 3)
1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50 receiver termination resistor to VCC for proper operation.
3. In the differential configuration when the input termination pin (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
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2
NBSG16M
VCC
VCC
VTD
50 50 50 50 D
Q
D
Q
50 Q
Q
50 VTD
VBB
16 mA
VEE
VEE
Figure 2. Logic Diagram
Figure 3. CML Output Structure
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD and VTD to VCC
LVDS
Connect VTD and VTD together
AC−COUPLED
Bias VTD and VTD Inputs within (VIHCMR)
Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be applied to the
unused complimentary differential input.
Nominal voltage 1.5 V for LVTTL and VCC/2 for
LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Value
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 4)
Flammability Rating
> 1 kV
> 100 V
> 4 kV
Level 1
Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
145
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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3
NBSG16M
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
s
VCC
Positive Power Supply
VEE = 0 V
3.6
V
VEE
Negative Power Supply
VCC = 0 V
−3.6
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
3.6
−3.6
V
V
VINPP
Differential Input Voltage |D − D|
VCC − VEE 2.8 V
VCC − VEE < 2.8 V
2.8
|VCC − VEE|
V
IIN
Input Current Through RT (50 Resistor)
Static
Surge
45
80
mA
mA
Iout
Output Current
Continuous
Surge
25
50
mA
mA
IBB
VBB Sink/Source
1.0
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
JA
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
QFN−16
QFN−16
42
35
°C/W
°C/W
JC
Thermal Resistance (Junction−to−Case)
1S2P (Note 5)
QFN−16
4.0
°C/W
Tsol
Wave Solder
< 15 sec.
225
°C
VI VCC
VI VEE
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board − 1S2P (1 signal, 2 power)
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NBSG16M
Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 2.5 V; VEE = 0 V (Note 6)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Positive Power Supply Current
37
43
51
37
43
51
37
43
51
mA
VOH
Output HIGH Voltage (Note 7)
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VOL
Output LOW Voltage (Note 6)
VCC −
400
VCC−
330
VCC −
400
VCC−
330
VCC −
400
VCC−
330
mV
VIH
Input HIGH Voltage
(Single−Ended) (Note 8)
VEE +
1.275
VCC −
1.0*
VCC
VEE +
1.275
VCC −
1.0*
VCC
VEE+
1..275
VCC −
1.0*
VCC
V
VIL
Input LOW Voltage
(Single−Ended) (Note 8)
VEE
VCC −
1.4*
VIH−
0.150
VEE
VCC −
1.4*
VIH−
0.150
VEE
VCC −
1.4*
VIH−
0.150
V
VBB
ECL Reference Voltage Output
1075
1170
1265
1075
1170
1265
1075
1170
1265
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 8)
(Differential Configuration)
1.2
2.5
1.2
2.5
1.2
2.5
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
RTOUT
Internal Output Termination
Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
60
100
60
100
60
100
A
IIL
Input LOW Current (@ VIL)
25
50
25
50
25
50
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to −0.965 V.
7. All loading with 50 to VCC.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
*Typicals used for testing purposes.
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5
NBSG16M
Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT VCC = 3.3 V; VEE = 0 V (Note 9)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Positive Power Supply Current
37
43
51
37
43
51
37
43
51
mA
VOH
Output HIGH Voltage (Note 10)
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VOL
Output LOW Voltage (Note 9)
VCC −
400
VCC −
330
VCC −
400
VCC −
330
VCC −
400
VCC −
330
mV
VIH
Input HIGH Voltage
(Single−Ended) (Note 11)
VEE +
1.275
VCC −
1.0*
VCC
VEE +
1.275
VCC −
1.0*
VCC
VEE +
1.275
VCC −
1.0*
VCC
V
VIL
Input LOW Voltage
(Single−Ended) (Note 11)
VEE
VCC −
1.4*
VIH −
0.150
VEE
VCC −
1.4*
VIH −
0.150
VEE
VCC −
1.4*
VIH −
0.150
V
VBB
ECL Reference Voltage Output
1875
1970
2065
1875
1970
2065
1875
1970
2065
mV
VIHCMR
Input HIGH Voltage Common
Mode Range (Note 11)
(Differential Configuration)
1.2
3.3
1.2
3.3
1.2
3.3
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
RTOUT
Internal Output Termination
Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
60
100
60
100
60
100
A
IIL
Input LOW Current (@ VIL)
25
50
25
50
25
50
A
Symbol
Characteristic
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
9. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to −0.165 V.
10. All loading with 50 to VCC.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
*Typicals used for testing purposes.
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NBSG16M
Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT VCC = 0 V; VEE = −3.465 to −2.375 V (Note 12)
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ICC
Positive Power Supply Current
37
43
51
37
43
51
37
43
51
mA
VOH
Output HIGH Voltage (Note 13)
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
VCC −
40
VCC −
10
VCC
mV
VOL
Output LOW Voltage (Note 12)
VCC −
400
VCC −
330
VCC −
400
VCC −
330
VCC −
400
VCC −
330
mV
VIH
Input HIGH Voltage
(Single−Ended) (Note 13)
VEE +
1.275
VCC −
1.0*
VCC
VEE +
1.275
VCC −
1.0*
VCC
VEE +
1.275
VCC −
1.0*
VCC
V
VIL
Input LOW Voltage
(Single−Ended) (Note 13)
VEE
VCC −
1.4*
VIH−
0.150
VEE
VCC −
1.4*
VIH−
0.150
VEE
VCC −
1.4*
VIH−
0.150
V
VBB
ECL Reference Voltage Output
−1425
−1330
−1235
−1425
−1330
−1235
−1425
−1330
−1235
mV
VIHCMR
Input HIGH Voltage Common
Mode Range (Note 14)
(Differential Configuration)
VCC
V
RTIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
RTOUT
Internal Output Termination
Resistor
45
50
55
45
50
55
45
50
55
IIH
Input HIGH Current (@ VIH)
60
100
60
100
60
100
A
IIL
Input LOW Current (@ VIL)
25
50
25
50
25
50
A
Symbol
Characteristic
VEE+1.2
VCC
VEE+1.2
VCC
VEE+1.2
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12. Input and output parameters vary 1:1 with VCC.
13. All loading with 50 to VCC.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
*Typicals used for testing purposes.
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NBSG16M
Table 8. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
−40°C
Symbol
Characteristic
VOUTPP
Output Voltage Amplitude
(See Figure 4) (Note 15)
fin < 7 GHz
fin < 10 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Duty Cycle Skew (Note 16)
tJITTER
RMS Random Clock Jitter (Note 18)
Min
Typ
300
200
400
250
90
110
150
3
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 17)
tr
tf
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
Max
85°C
Min
Typ
Max
Min
Typ
300
200
400
250
100
120
150
15
3
0.2
1
8
15
Max
300
100
400
150
100
125
155
ps
15
3
15
ps
0.2
1
0.2
1.0
8
15
8
15
Unit
mV
ps
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter (Note 19)
fin < 10 Gb/s
VINPP
25°C
75
Q, Q
21
35
2500
75
53
21
35
2500
75
53
21
35
2500
mV
53
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 to VCC. Input edge rates 40 ps (20% − 80%).
16. See Figure 5 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform.
17. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement
operating in differential mode.
18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
19. Additive Peak−to−Peak data dependent jitter with NRZ PRBS231−1 data rate at 10 Gb/s.
OUTPUT VOLTAGE AMPLITUDE (mV)
500
VCC − VEE = 3.3 V
450
400
350
VCC − VEE = 2.5 V
300
250
200
150
100
50
0
0
1
2
3
4
5
6
FREQUENCY (GHz)
7
8
9
Figure 4. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
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8
10
NBSG16M
D
VINPP(D) = VIH(D) − DIL(D)
VINPP(D) = VIH(D) − DIL(D)
D
Q
VOUTPP(Q) = VOH(Q) − VOL(Q)
VOUTPP(Q) = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 5. AC Reference Measurement
VCC
Zo = 50 50 50 Q
Driver
Device
D
Receiver
Device
Zo = 50 Q
D
Figure 6. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 − Termination of ECL Logic Devices)
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NBSG16M
Examples interfaces are illustrated below in a 50 environment (Z = 50 ).
Application Information
All inputs can accept PECL, CML, and LVDS signal
levels. The input voltage can range from VCC to 1.2 V.
VCC
50 VCC
50 Q
D
Z
SG16M
VCC
VTD
Z
Q
D
VCC
50 SG16M
50 VTD
VEE
VEE
Figure 7. CML to CML Interface
VCC
VCC
50 PECL
Driver
D
Z
VBias
50 VTD
SG16M
Z
RT
Recommended RT Values
VCC
VBias
RT
5.0 V 290 3.3 V 150 2.5 V
D
RT
50 50 VTD
VEE
VEE
80 VEE
Figure 9. PECL to CML Receiver Interface
VCC
VCC
D
Z
VTD
LVDS
Driver
50 SG16M
Z
D
50 VTD
VEE
VEE
Figure 8. LVDS to CML Receiver Interface
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NBSG16M
PACKAGE DIMENSIONS
QFN−16
MN SUFFIX
CASE 485G−01
ISSUE A
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
M
−Y−
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
B
N
0.25 (0.010) T
0.25 (0.010) T
J
R
C
0.08 (0.003) T
−T−
K
SEATING
PLANE
E
H
G
L
5
8
4
9
F
12
1
16
D
13
P
NOTE 3
0.10 (0.004)
M
T X Y
SOLDERING FOOTPRINT
0.575
0.022
3.25
0.128
0.30
0.012
1.50
0.059
3.25
0.128
0.50
0.02
0.30
0.012
SCALE 10:1
QFN−16, 3x3 mm,
EP 2x2 mm
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11
mm inches
MILLIMETERS
MIN
MAX
3.00 BSC
3.00 BSC
0.80
1.00
0.23
0.28
1.75
1.85
1.75
1.85
0.50 BSC
0.875
0.925
0.20 REF
0.00
0.05
0.35
0.45
1.50 BSC
1.50 BSC
0.875
0.925
0.60
0.80
INCHES
MIN
MAX
0.118 BSC
0.118 BSC
0.031
0.039
0.009
0.011
0.069
0.073
0.069
0.073
0.020 BSC
0.034
0.036
0.008 REF
0.000
0.002
0.014
0.018
0.059 BSC
0.059 BSC
0.034
0.036
0.024
0.031
NBSG16M
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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http://onsemi.com
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