ON MC74LCX16373DT Low−voltage cmos 16−bit transparent latch with 5 v−tolerant inputs and outputs (3−state, non−inverting) Datasheet

MC74LCX16373
Low−Voltage CMOS 16−Bit
Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
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The MC74LCX16373 is a high performance, non−inverting 16−bit
transparent latch operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16−bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX16373 inputs to be safely driven from 5.0 V devices.
The MC74LCX16373 contains 16 D−type latches with 3−state
5.0 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state outputs are controlled by the Output
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When
OE is HIGH, the standard outputs are in the high impedance state, but
this does not interfere with new data entering into the latches.
TSSOP−48
DT SUFFIX
CASE 1201
48
1
MARKING DIAGRAM
48
LCX16373G
AWLYYWW
Features
•
•
•
•
•
•
•
•
•
•
•
•
Designed for 2.3 to 3.6 V VCC Operation
5.4 ns Maximum tpd
5.0 V Tolerant − Interface Capability With 5.0 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
LVTTL Compatible
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500 mA
ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
These are Pb−Free Devices*
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 6
1
Publication Order Number:
MC74LCX16373/D
MC74LCX16373
OE1 1
48 LE1
O0 2
47 D0
O1 3
46 D1
GND 4
O2 5
45 GND
44 D2
O3 6
43 D3
VCC 7
42 VCC
O4 8
41 D4
O5 9
40 D5
GND 10
O6 11
39 GND
38 D6
O7 12
37 D7
O8 13
36 D8
O9 14
35 D9
GND 15
O10 16
34 GND
33 D10
O11 17
32 D11
VCC 18
31 VCC
O12 19
30 D12
O13 20
29 D13
GND 21
O14 22
28 GND
27 D14
O15 23
26 D15
OE2 24
25 LE2
1
OE1
OE2
48
LE1
LE2
47
D0
46
D1
44
D2
43
D3
41
D4
40
D5
38
D6
37
D7
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
2
Q
3
Q
5
Q
6
Q
8
Q
9
Q
11
Q
12
Q
O0
24
25
36
D8
O1
35
D9
O2
33
D10
O3
32
D11
O4
30
D12
O5
29
D13
O6
27
D14
O7
26
D15
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
nLE
D
13
Q
14
Q
16
Q
17
Q
19
Q
20
Q
22
Q
23
Q
Figure 2. Logic Diagram
Figure 1. Pinout: 48−Lead
(Top View)
Table 1. PIN NAMES
Pins
Function
OEn
LEn
D0−D15
O0−O15
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
TRUTH TABLE
Inputs
H
L
Z
X
Outputs
LE1
OE1
D0:7
O0:7
Inputs
Outputs
LE2
OE2
D8:15
O8:15
X
H
X
Z
X
H
X
Z
H
L
L
L
H
L
L
L
H
L
H
H
H
L
H
H
L
L
X
O0
L
L
X
O0
=
=
=
=
High Voltage Level
Low Voltage Level
High Impedance State
High or Low Voltage Level and Transitions Are Acceptable; for ICC reasons, DO NOT FLOAT Inputs
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2
O8
O9
O10
O11
O12
O13
O14
O15
MC74LCX16373
ORDERING INFORMATION
Package
Shipping†
MC74LCX16373DT
TSSOP−48*
39 Units / Rail
MC74LCX16373DTG
TSSOP−48*
39 Units / Rail
MC74LCX16373DTR2
TSSOP−48*
2500 / Tape & Reel
M74LCX16373DTR2G
TSSOP−48*
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
DC Supply Voltage
Condition
Unit
−0.5 to +7.0
V
V
VI
DC Input Voltage
−0.5 ≤ VI ≤ +7.0
VO
DC Output Voltage
−0.5 ≤ VO ≤ +7.0
Output in 3−State
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State. (Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
V
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Supply Voltage
Operating
Data Retention Only
Min
Typ
Max
Unit
2.0
1.5
2.5, 3.3
2.5, 3.3
3.6
3.6
V
0
5.5
V
0
0
VCC
5.5
V
VI
Input Voltage
VO
Output Voltage
IOH
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
− 24
− 12
−8
mA
IOL
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
VCC = 2.3 V − 2.7 V
+ 24
+ 12
+8
mA
TA
Operating Free−Air Temperature
−40
+85
°C
0
10
ns/V
Dt/DV
(HIGH or LOW State)
(3−State)
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
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MC74LCX16373
DC ELECTRICAL CHARACTERISTICS
TA = −40°C to +85°C
Symbol
VIH
VIL
VOH
VOL
Condition
Min
2.3 V ≤ VCC ≤ 2.7 V
1.7
2.7 V ≤ VCC ≤ 3.6 V
2.0
Characteristic
HIGH Level Input Voltage (Note 2)
LOW Level Input Voltage (Note 2)
HIGH Level Output Voltage
LOW Level Output Voltage
Max
V
2.3 V ≤ VCC ≤ 2.7 V
0.7
2.7 V ≤ VCC ≤ 3.6 V
0.8
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
VCC − 0.2
VCC = 2.3 V; IOH = −8 mA
1.8
VCC = 2.7 V; IOH = −12 mA
2.2
VCC = 3.0 V; IOH = −18 mA
2.4
VCC = 3.0 V; IOH = −24 mA
2.2
Unit
V
V
2.3 V ≤ VCC ≤ 3.6 V; IOL = 100 mA
0.2
VCC = 2.3 V; IOL= 8 mA
0.6
VCC = 2.7 V; IOL= 12 mA
0.4
VCC = 3.0 V; IOL = 16 mA
0.4
VCC = 3.0 V; IOL = 24 mA
0.55
V
II
Input Leakage Current
2.3 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 5.5 V
±5.0
mA
IOZ
3−State Output Current
2.3 ≤ VCC ≤ 3.6 V; 0V ≤ VO ≤ 5.5 V;
VI = VIH or V IL
±5.0
mA
IOFF
Power−Off Leakage Current
VCC = 0 V; VI or VO = 5.5 V
10
mA
ICC
Quiescent Supply Current
2.3 ≤ VCC ≤ 3.6 V; VI = GND or VCC
20
mA
2.3 ≤ VCC ≤ 3.6 V; 3.6 ≤ VI or VO ≤ 5.5 V
±20
mA
2.3 ≤ VCC ≤ 3.6 V; VIH = VCC − 0.6 V
500
mA
DICC
Increase in ICC per Input
2. These values of VI are used to test DC electrical characteristics only.
AC CHARACTERISTICS tR = tF = 2.5 ns; CL = 50 pF; RL = 500 W
TA = −40°C to +85°C
VCC = 3.3 V ± 0.3 V
CL = 50 pF
Symbol
Parameter
VCC = 2.7 V
CL = 50 pF
VCC = 2.5 V ± 0.2 V
CL = 30 pF
Waveform
Min
Max
Min
Max
Min
Max
Unit
tPLH
tPHL
Propagation Delay
Dn to On
1
1.5
1.5
5.4
5.4
1.5
1.5
5.9
5.9
1.5
1.5
6.5
6.5
ns
tPLH
tPHL
Propagation Delay
LE to On
3
1.5
1.5
5.5
5.5
1.5
1.5
6.4
6.4
1.5
1.5
6.6
6.6
ns
tPZH
tPZL
Output Enable Time to
High and Low Level
2
1.5
1.5
6.1
6.1
1.5
1.5
6.5
6.5
1.5
1.5
7.9
7.9
ns
tPHZ
tPLZ
Output Disable Time From
High and Low Level
2
1.5
1.5
6.0
6.0
1.5
1.5
6.3
6.3
1.5
1.5
7.2
7.2
ns
ts
Setup Time, HIGH or LOW Dn to
LE
3
2.5
2.5
3.0
ns
th
Hold Time, HIGH or LOW Dn to LE
3
1.5
1.5
2.0
ns
tw
LE Pulse Width, HIGH
3
3.0
3.0
3.5
ns
tOSHL
tOSLH
Output−to−Output Skew
(Note 3)
1.0
1.0
ns
3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
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4
MC74LCX16373
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Symbol
Characteristic
Min
Condition
Typ
Max
Unit
VOLP
Dynamic LOW Peak Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
V
VOLV
Dynamic LOW Valley Voltage
(Note 4)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
V
4. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
Condition
Typical
Unit
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
7
pF
COUT
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
8
pF
CPD
Power Dissipation Capacitance
10 MHz, VCC = 3.3 V, VI = 0 V or VCC
20
pF
CIN
Parameter
VCC
Vmi
Vmi
Dn
0V
tPHL
tPLH
VOH
Vmo
Vmo
On
VOL
WAVEFORM 1 − PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VCC
OEn
VCC
Dn
Vmi
Vmi
0V
0V
tPZH
tPHZ
Vmo
On
th
VCC
VOH
VHZ
LEn
Vmo
tw
Vmo
0V
tPZL
On
ts
tPLH, tPHL
tPLZ
VOH
On
Vmo
Vmo
VLZ
VOL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
VOL
WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted
Figure 3. AC Waveforms
Table 2. AC WAVEFORMS
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
2.5 V + 0.2 V
Vmi
1.5 V
1.5 V
VCC / 2
Vmo
1.5 V
1.5 V
VCC / 2
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
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5
MC74LCX16373
VCC
R1
PULSE
GENERATOR
DUT
RT
CL
RL
Figure 4. Test Circuit
Table 3. TEST CIRCUIT
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6 V at VCC = 3.3 0.3 V
6 V at VCC = 2.5 0.2 V
Open Collector/Drain tPLH and tPHL
6V
tPZH, tPHZ
CL =
CL =
RL =
RT =
GND
50 pF at VCC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)
30 pF at VCC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)
R1 = 500 W or equivalent
ZOUT of pulse generator (typically 50 W)
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6
6 V or VCC × 2
OPEN
GND
MC74LCX16373
PACKAGE DIMENSIONS
TSSOP−48
DT SUFFIX
CASE 1201−01
ISSUE A
48X
K REF
0.12 (0.005)
M
T U
S
V
S
T U
S
J J1
48
25
SECTION N−N
M
0.254 (0.010)
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
B
−U−
L
N
1
24
A
−V−
PIN 1
IDENT.
N
F
DETAIL E
D
0.076 (0.003)
−T− SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
C
M
0.25 (0.010)
−W−
DETAIL E
G
H
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7
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
12.40
12.60
6.00
6.20
−−−
1.10
0.05
0.15
0.50
0.75
0.50 BSC
0.37
−−−
0.09
0.20
0.09
0.16
0.17
0.27
0.17
0.23
7.95
8.25
0_
8_
INCHES
MIN
MAX
0.488
0.496
0.236
0.244
−−−
0.043
0.002
0.006
0.020
0.030
0.0197 BSC
0.015
−−−
0.004
0.008
0.004
0.006
0.007
0.011
0.007
0.009
0.313
0.325
0_
8_
MC74LCX16373
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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For additional information, please contact your
local Sales Representative.
MC74LCX16373/D
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