ON MC74HCT573A Octal 3−state noninverting transparent latch with lsttl compatible input Datasheet

MC74HCT573A
Octal 3−State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT573A is identical in pinout to the LS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High−Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
•
•
•
•
•
•
•
w
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 10 μA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 234 FETs or 58.5 Equivalent Gates
— Improved Propagation Delays
— 50% Lower Quiescent Power
These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 11
1
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MARKING
DIAGRAMS
20
PDIP−20
N SUFFIX
CASE 738
20
1
20
1
20
MC74HCT573AN
AWLYYWW
1
SOIC WIDE−20
DW SUFFIX
CASE 751D
HCT573A
AWLYYWW
1
20
HCT
573A
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HCT573AN
MC74HCT573ADW
Package
Shipping
PDIP−20
1440 / Box
SOIC−WIDE
38 / Rail
MC74HCT573ADWR2 SOIC−WIDE
1000 / Reel
MC74HCT573ADT
TSSOP−20
75 / Rail
MC74HCT573ADTR2
TSSOP−20
2500 / Reel
Publication Order Number:
MC74HCT573A/D
MC74HCT573A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
Q0
Q1
Q2
NONINVERTING
OUTPUTS
Q3
Q4
Q5
Q6
Q7
11
LATCH ENABLE
PIN 20 = VCC
PIN 10 = GND
1
OUTPUT ENABLE
Inputs
Output
Latch
Enable
D
Q
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
X = Don’t Care
Z = High Impedance
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Design Criteria
Value
Units
Internal Gate Count*
58.5
ea
Internal Gate Propagation Delay
1.5
ns
Internal Gate Power Dissipation
5.0
μW
0.0075
pJ
Speed Power Product
20
VCC
2
19
Q0
D1
3
18
Q1
D2
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
D5
7
14
Q5
D6
8
13
Q6
D7
9
12
10
11
Q7
LATCH
ENABLE
GND
FUNCTION TABLE
Output
Enable
1
*Equivalent to a two−input NAND gate.
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2
MC74HCT573A
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MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, TSSOP or SOIC Package)
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/°C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| v 20 μA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| v 6.0 mA
4.5
0.26
0.33
0.4
Symbol
VOL
Parameter
Maximum Low−Level Output
Voltage
Test Conditions
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
μA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
5.5
± 0.5
± 5.0
± 10
μA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout v 0 μA
5.5
4.0
40
160
μA
ΔICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 μA
5.5
≥ – 55_C
25_C to 125_C
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
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3
MC74HCT573A
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AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
– 55 to
25_C
v 85_C
v 125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Q
(Figures 1 and 5)
30
38
45
ns
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
30
38
45
ns
TPLZ,
TPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tTZL,
tTZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
28
35
42
ns
tTLH,
tTHL
Maximum Output Transition Time, any Output
(Figures 1 and 5)
12
15
18
ns
Cin
Maximum Input Capacitance
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
48
Power Dissipation Capacitance (Per Enabled Output)*
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
Symbol
Parameter
Fig.
Min
Max
v 85_C
Min
Max
v 125_C
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
10
13
15
ns
th
Minimum Hold Time, Latch Enable to Input D
4
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
15
19
22
ns
tr, tf
Maximum Input Rise and Fall Times
1
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4
500
500
500
ns
MC74HCT573A
SWITCHING WAVEFORMS
3.0 V
tr
tf
3.0 V
2.7 V
1.3 V
0.3 V
INPUT D
tPLH
1.3 V
GND
tw
GND
tPHL
90%
1.3 V
10%
Q
LATCH
ENABLE
tTLH
tTHL
1.3 V
Q
Figure 1.
OUTPUT
ENABLE
Figure 2.
3.0 V
1.3 V
tPZL
Q
tPLZ
tPZH
VALID
GND
HIGH
IMPEDANCE
1.3 V
Q
tPHZ
1.3 V
10%
VOL
90%
VOH
GND
EXPANDED LOGIC DIAGRAM
D0
D1
C L*
D2
*Includes all probe and jig capacitance
D3
Figure 5. Test Circuit
D4
D5
TEST POINT
C L*
3.0 V
Figure 4.
OUTPUT
DEVICE
UNDER
TEST
th
1.3 V
LATCH
ENABLE
TEST POINT
1 kΩ
GND
tSU
HIGH
IMPEDANCE
DEVICE
UNDER
TEST
3.0 V
1.3 V
INPUT D
Figure 3.
OUTPUT
tPHL
tPLH
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
D6
D7
2
3
4
5
6
7
8
9
LATCH ENABLE
*Includes all probe and jig capacitance
OUTPUT ENABLE
Figure 6. Test Circuit
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5
11
1
D
Q
LE
19
D
Q
LE
18
D
Q
LE
17
D
Q
LE
16
D
Q
LE
15
D
Q
LE
14
D
Q
LE
13
D
Q
LE
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MC74HCT573A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
−A−
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
−T−
K
SEATING
PLANE
G
M
N
E
F
D
J
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15_
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
SO−20
DW SUFFIX
CASE 751D−05
ISSUE F
A
20
q
X 45 _
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
0.25
E
h
H
M
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
B
M
D
18X
e
A1
SEATING
PLANE
C
T
http://onsemi.com
6
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT573A
PACKAGE DIMENSIONS
20X
0.15 (0.006) T U
2X
L
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE A
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
M
A
−V−
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
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MC74HCT573A/D
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