EMLSI EM680FU16A-70LF Low power, 512kx16 sram Datasheet

EM680FU16A Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
0.0
Initial Draft
0.1
0.1 Revision
Draft Date
Sep. 28 , 2007
Fix typo error
Remark
Preliminary
Nov. 12, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-719
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM680FU16A Series
Low Power, 512Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The EM680FU16A families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The families also supports low data retention voltage for battery
back-up operation with low data retention current.
Process Technology : 0.15µm Full CMOS
Organization : 512K x 16 bit
Power Supply Voltage : 2.7V ~ 3.3V
Low Data Retention Voltage : 1.5V(Min.)
Three state output and TTL Compatible
Package Type : 48-FPBGA 8.0x10.0
PRODUCT FAMILY
Power Dissipation
Operating
Temperature
Vcc
Range
Speed
Standby
(ISB1, Typ.)
Operating
(ICC1.Max)
EM680FU16A-45LF
Industrial (-40 ~ 85oC)
2.7V~3.3V
45ns
2 µA
3mA
48-FPBGA
EM680FU16A-55LF
Industrial (-40 ~ 85oC)
2.7V~3.3V
55ns
2 µA
3mA
48-FPBGA
EM680FU16A-70LF
Industrial (-40 ~ 85oC)
2.7V~3.3V
70ns
2 µA
3mA
48-FPBGA
PKG
Type
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CS2
B
I/O9
UB
A3
A4
CS1
I/O1
C
I/O10 I/O11
A5
A6
I/O2
I/O3
D
VSS
I/O12
A17
A7
I/O4
VCC
E
VCC
I/O13
DNU
A16
I/O5
VSS
Pre-charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
Row Select
Product
Family
I/O1 ~ I/O8
I/O9 ~ I/O16
F
I/O15 I/O14
A14
A15
I/O6
I/O7
G
I/O16 DNU
A12
A13
WE
I/O8
A9
A10
A11
DNU
Data
Cont
Data
Cont
VSS
Memory Array
2048 x 4096
I/O Circuit
Column Select
A11 A12 A13 A14 A15 A16 A17 A18
H
A18
A8
48-FPBGA : Top view (ball down)
Name
Function
CS1,CS2 Chip select inputs
Name
Function
Vcc
Power Supply
OE
Output Enable input
Vss
Ground
WE
Write Enable input
UB
Upper Byte (I/O9~16)
Address Inputs
LB
Lower Byte (I/O1~8)
A0~A18
I/O1~I/O16 Data Inputs/outputs
WE
OE
UB
LB
CS1
CS2
DNU Do Not Use
2
Control Logic
EM680FU16A Series
Low Power, 512Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Symbol
Voltage on Any Pin Relative to Vss
Minimum
Unit
VIN, VOUT
-0.2 to 4.0V
V
Voltage on Vcc supply relative to Vss
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
o
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS1
CS2
OE
WE
LB
UB
I/O1-8
I/O9-16
Mode
Power
H
X
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
L
X
X
X
X
High-Z
High-Z
Deselected
Stand by
X
X
X
X
H
H
High-Z
High-Z
Deselected
Stand by
L
H
H
H
L
X
High-Z
High-Z
Output Disabled
Active
L
H
H
H
X
L
High-Z
High-Z
Output Disabled
Active
L
H
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
H
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
H
L
H
L
L
Data Out
Data Out
Word Read
Active
L
H
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
H
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
H
X
L
L
L
Data In
Data In
Word Write
Active
NOTE: X means don’t care. (Must be low or high state)
3
EM680FU16A Series
Low Power, 512Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
1.
2.
3.
4.
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
3.3
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.22)
V
Input low voltage
VIL
-0.23)
-
0.6
V
TA= -40 to 85oC, otherwise specified.
Overshoot: VCC +2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
CIN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO=0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN=VSS to VCC
-1
-
1
uA
Output leakage current
ILO
CS1=VIH or CS2=VIL or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
-1
-
1
uA
Operating power supply
ICC
IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL
-
-
3
mA
ICC1
Cycle time=1µs, 100% duty, IIO=0mA,
CS1<0.2V, LB<0.2V or/and UB<0.2V, CS2>VCC-0.2V,
VIN<0.2V or VIN>VCC-0.2V
-
-
3
mA
45ns
-
-
40
ICC2
Cycle time = Min, IIO=0mA, 100% duty,
CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
55ns
-
-
30
70ns
-
-
20
Average operating current
mA
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.2
-
-
V
Standby Current (TTL)
ISB
CS1=VIH, CS2=VIL, Other inputs=VIH or VIL
-
-
0.3
mA
ISB1
CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled)
or 0V<CS2<0.2V (CS2 controlled),
Other inputs = 0~VCC
-
2
15
uA
Standby Current (CMOS)
(Typ. condition : VCC=3.0V @ 25oC)
(Max. condition : VCC=3.3V @ 85oC)
4
LF
EM680FU16A Series
Low Power, 512Kx16 SRAM
AC OPERATING CONDITIONS
VTM3)
Test Conditions (Test Load and Test Input/Output Reference)
R12)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL (70ns)
CL1) = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
R2=3150 ohm
2. R1=3070 ohm,
3. VTM=2.8V
4. CL = 5pF + 1 TTL (measurement with tLZ1,2, tHZ12, tOLZ, tOHZ, tWHZ)
R22)
CL1)
READ CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Min
Max
Min
Max
Min
Max
Unit
Read cycle time
tRC
45
-
55
-
70
-
ns
Address access time
tAA
-
45
-
55
-
70
ns
Chip select to output
tCO1, tCO2
-
45
-
55
-
70
ns
Output enable to valid output
tOE
-
30
-
35
-
35
ns
UB, LB Access time
tBA
-
45
-
55
-
70
ns
tLZ1, tLZ2
5
-
5
-
5
-
ns
UB, LB enable to low-Z output
tBLZ
5
-
5
-
5
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
5
-
ns
tHZ1, tHZ2
0
20
0
20
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
20
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
10
-
ns
Chip select to low-Z output
Chip disable to high-Z output
WRITE CYCLE (Vcc =2.7 to 3.3V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
Symbol
45ns
55ns
70ns
Unit
Min
Max
Min
Max
Min
Max
tWC
45
-
55
-
70
-
ns
tCW1, tCW2
45
-
45
-
60
-
ns
Address setup time
tAS
0
-
0
-
0
-
ns
Address valid to end of write
tAW
45
-
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
45
-
60
-
ns
Write pulse width
tWP
45
-
45
-
55
-
ns
Write recovery time
tWR
0
-
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
20
0
20
0
25
ns
Data to write time overlap
tDW
25
-
30
-
30
-
ns
Data hold from write time
tDH
0
-
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
5
-
ns
Write cycle time
Chip select to end of write
5
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS1=OE=VIL,
CS2=WE=VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO1,2
CS1
CS2
tHZ1,2
tBA
UB,LB
tBHZ
tOE
OE
Data Out
High-Z
tOHZ
tOLZ
Data Valid
tBLZ
tLZ1,2
NOTES (READ CYCLE)
1. tHZ1,2 and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ1,2(Max.) is less than tLZ1,2(Min.) both for a given device and from device to
device interconnection.
6
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tWR(4)
tCW1,2(2)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tAS(3)
Data in
tDW
High-Z
tDH
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 CONTROLLED)
tWC
Address
tAS(3)
tWR(4)
tCW1,2(2)
CS1
CS2
tAW
tBW
UB,LB
tWP(1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
EM680FU16A Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tWR(4)
tCW1,2(2)
CS1
CS2
tAW
tBW
UB,LB
tAS(3)
tWP(1)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS1, a high CS2 and low WE. A write begins at the latest
transition among CS1 goes low, CS2 goes high and WE goes low. A write ends at the earliest transition
among CS1 goes high, CS2 goes low and WE goes high. The tWP is measured from the beginning of write
to the end of write.
2. tCW1 is measured from the CS1 going low or CS2 going high to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS1 or WE
going high or CS2 going low.
8
EM680FU16A Series
Low Power, 512Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
IDR
Chip Deselect to Data Retention Time
tSDR
Operation Recovery Time
tRDR
Test Condition
Min
Typ
Max
Unit
CS1 ≥ Vcc-0.2V 1)
1.5
-
3.3
V
-
-
4
uA
0
-
-
tRC
-
-
VCC=1.5V, CS1 ≥ Vcc-0.2V 1)
See data retention wave form
1. CS1 ≥ Vcc-0.2V , CS2 ≥ Vcc-0.2V (CS1 controlled) or CS2 < 0.2V (CS2 controlled)
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
tRDR
Vcc
2.7V
2.2V
VDR
CS1 > Vcc-0.2V
CS1, LB / UB
GND
Data Retention Mode
Vcc
2.7V
CS2
tRDR
tSDR
VDR
0.4V
CS2 < 0.2V
GND
9
ns
EM680FU16A Series
Low Power, 512Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
48 Ball Fine Pitch BGA (0.75mm ball pitch)
Bottom View
A1 index Mark
B
B1
B
6
5
4
3
0.5
2
0.5
Top View
1
A
B
#A1
C
C1
C
C
D
C1/2
E
F
G
H
B/2
Detail A
D
E2
0.26
Side View
0.25 Typ.
E
E1
A
Min
Typ
Max
A
-
0.75
-
B
7.90
8.00
8.10
B1
-
3.75
-
C
9.90
10.00
10.10
C1
-
5.25
-
D
0.30
0.35
0.40
E
1.00
1.04
1.10
E1
-
0.79
-
E2
-
0.25
-
Y
-
-
0.08
Y
0.79Typ.
C
NOTES.
1. Bump counts : 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75x0.75) (typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity : 0.08(Max)
10
EM680FU16A Series
Low Power, 512Kx16 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Product Type
10. Speed
3. Density
4. Function
9. Package
8. Generation
5. Technology
7. Organization
6. Operating Voltage
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
1. Memory Component
EM --------------------- Memory
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------A ----------------------B ----------------------C ----------------------D ----------------------E ----------------------F ----------------------G ----------------------
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
2 ----------------------- Multiplexed
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
1st generation
2nd generation
3rd generation
4th generation
5th generation
6th generation
7th generation
8th generation
9. Package
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V ---------------------- 32 SOP
10. Speed
45 ---------------------55 ---------------------70 ---------------------85 ---------------------10 ---------------------12 ----------------------
5. Technology
F ------------------------- Full CMOS
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
45ns
55ns
70ns
85ns
100ns
120ns
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
Similar pages